diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-12 09:05:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-12 09:05:25 -0500 |
| commit | 4583a5114aa34efb3b83e9a2e40dd74f7c49facb (patch) | |
| tree | 2b1fef9b86d8c589f2dbc2e17c03c85a9e1900d3 /tests/long/fs | |
| parent | 9d6d8e02aab300c524ca9cf216a11e71d10826aa (diff) | |
| download | gem5-4583a5114aa34efb3b83e9a2e40dd74f7c49facb.tar.xz | |
stats: Bump regressions to match latest changes
Updates after timezone hick-up and sorting of dictionary items in the
SimObject.
Diffstat (limited to 'tests/long/fs')
9 files changed, 12410 insertions, 12421 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index a43b4e79e..405fa6e98 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,175 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.843665 # Number of seconds simulated -sim_ticks 2843665155500 # Number of ticks simulated -final_tick 2843665155500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.843655 # Number of seconds simulated +sim_ticks 2843654861000 # Number of ticks simulated +final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158211 # Simulator instruction rate (inst/s) -host_op_rate 191554 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3597700350 # Simulator tick rate (ticks/s) -host_mem_usage 605956 # Number of bytes of host memory used -host_seconds 790.41 # Real time elapsed on the host -sim_insts 125052080 # Number of instructions simulated -sim_ops 151406456 # Number of ops (including micro ops) simulated +host_inst_rate 157498 # Simulator instruction rate (inst/s) +host_op_rate 190690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3581426538 # Simulator tick rate (ticks/s) +host_mem_usage 613612 # Number of bytes of host memory used +host_seconds 794.00 # Real time elapsed on the host +sim_insts 125053138 # Number of instructions simulated +sim_ops 151407658 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1364476 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 533600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1164672 # Number of bytes read from this memory -system.physmem.bytes_read::total 13841116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 419072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 26240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 445312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7174080 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9510160 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 21845 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 168230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 18198 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216816 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112095 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 152755 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 479830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3786212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 187645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 409567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4867351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 147370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 9228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2522829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 815263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3344332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2522829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 815601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 486056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3786212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 187659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 409567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8211683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 216816 # Number of read requests accepted -system.physmem.writeReqs 152755 # Number of write requests accepted -system.physmem.readBursts 216816 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 152755 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13860032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16192 # Total number of bytes read from write queue -system.physmem.bytesWritten 9524672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13841116 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9510160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 253 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 216881 # Number of read requests accepted +system.physmem.writeReqs 152787 # Number of write requests accepted +system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue +system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13536 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13436 # Per bank write bursts -system.physmem.perBankRdBursts::1 13084 # Per bank write bursts -system.physmem.perBankRdBursts::2 14401 # Per bank write bursts -system.physmem.perBankRdBursts::3 13747 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13445 # Per bank write bursts +system.physmem.perBankRdBursts::1 13090 # Per bank write bursts +system.physmem.perBankRdBursts::2 14400 # Per bank write bursts +system.physmem.perBankRdBursts::3 13760 # Per bank write bursts system.physmem.perBankRdBursts::4 15799 # Per bank write bursts -system.physmem.perBankRdBursts::5 12797 # Per bank write bursts -system.physmem.perBankRdBursts::6 13572 # Per bank write bursts -system.physmem.perBankRdBursts::7 13744 # Per bank write bursts -system.physmem.perBankRdBursts::8 13565 # Per bank write bursts -system.physmem.perBankRdBursts::9 13602 # Per bank write bursts -system.physmem.perBankRdBursts::10 13295 # Per bank write bursts -system.physmem.perBankRdBursts::11 11895 # Per bank write bursts -system.physmem.perBankRdBursts::12 13378 # Per bank write bursts -system.physmem.perBankRdBursts::13 13725 # Per bank write bursts -system.physmem.perBankRdBursts::14 13486 # Per bank write bursts -system.physmem.perBankRdBursts::15 13037 # Per bank write bursts -system.physmem.perBankWrBursts::0 9315 # Per bank write bursts -system.physmem.perBankWrBursts::1 9418 # Per bank write bursts -system.physmem.perBankWrBursts::2 10151 # Per bank write bursts -system.physmem.perBankWrBursts::3 9572 # Per bank write bursts -system.physmem.perBankWrBursts::4 8971 # Per bank write bursts -system.physmem.perBankWrBursts::5 8910 # Per bank write bursts -system.physmem.perBankWrBursts::6 9379 # Per bank write bursts -system.physmem.perBankWrBursts::7 9378 # Per bank write bursts +system.physmem.perBankRdBursts::5 12812 # Per bank write bursts +system.physmem.perBankRdBursts::6 13576 # Per bank write bursts +system.physmem.perBankRdBursts::7 13750 # Per bank write bursts +system.physmem.perBankRdBursts::8 13572 # Per bank write bursts +system.physmem.perBankRdBursts::9 13600 # Per bank write bursts +system.physmem.perBankRdBursts::10 13300 # Per bank write bursts +system.physmem.perBankRdBursts::11 11904 # Per bank write bursts +system.physmem.perBankRdBursts::12 13370 # Per bank write bursts +system.physmem.perBankRdBursts::13 13720 # Per bank write bursts +system.physmem.perBankRdBursts::14 13497 # Per bank write bursts +system.physmem.perBankRdBursts::15 13045 # Per bank write bursts +system.physmem.perBankWrBursts::0 9322 # Per bank write bursts +system.physmem.perBankWrBursts::1 9428 # Per bank write bursts +system.physmem.perBankWrBursts::2 10143 # Per bank write bursts +system.physmem.perBankWrBursts::3 9576 # Per bank write bursts +system.physmem.perBankWrBursts::4 8974 # Per bank write bursts +system.physmem.perBankWrBursts::5 8900 # Per bank write bursts +system.physmem.perBankWrBursts::6 9376 # Per bank write bursts +system.physmem.perBankWrBursts::7 9386 # Per bank write bursts system.physmem.perBankWrBursts::8 9384 # Per bank write bursts -system.physmem.perBankWrBursts::9 9425 # Per bank write bursts -system.physmem.perBankWrBursts::10 9360 # Per bank write bursts -system.physmem.perBankWrBursts::11 8832 # Per bank write bursts -system.physmem.perBankWrBursts::12 9377 # Per bank write bursts -system.physmem.perBankWrBursts::13 9192 # Per bank write bursts -system.physmem.perBankWrBursts::14 9288 # Per bank write bursts -system.physmem.perBankWrBursts::15 8871 # Per bank write bursts +system.physmem.perBankWrBursts::9 9431 # Per bank write bursts +system.physmem.perBankWrBursts::10 9355 # Per bank write bursts +system.physmem.perBankWrBursts::11 8834 # Per bank write bursts +system.physmem.perBankWrBursts::12 9379 # Per bank write bursts +system.physmem.perBankWrBursts::13 9206 # Per bank write bursts +system.physmem.perBankWrBursts::14 9289 # Per bank write bursts +system.physmem.perBankWrBursts::15 8875 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2843662895000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2843652584000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 216229 # Read request sizes (log2) +system.physmem.readPktSize::6 216294 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148319 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62843 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148351 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -197,810 +179,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 240 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 252.591884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.134462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.650054 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46986 50.75% 50.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18789 20.30% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6843 7.39% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3586 3.87% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3022 3.26% 85.58% # Bytes accessed per row activation +system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1307 1.41% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1131 1.22% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8795 9.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92579 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7460 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.029759 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 529.579779 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7459 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7460 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.949464 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.624141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.915893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6155 82.51% 82.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 493 6.61% 89.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 89 1.19% 90.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 200 2.68% 92.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 188 2.52% 95.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.23% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 27 0.36% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.21% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 36 0.48% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.13% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.05% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 168 2.25% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7460 # Writes before turning the bus around for reads -system.physmem.totQLat 7660076750 # Total ticks spent queuing -system.physmem.totMemAccLat 11720633000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1082815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35371.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 84 1.13% 90.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 205 2.75% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 200 2.68% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.23% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.23% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.16% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 25 0.33% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.08% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.04% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.21% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads +system.physmem.totQLat 7683149500 # Total ticks spent queuing +system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54121.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.34 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 183124 # Number of row buffer hits during reads -system.physmem.writeRowHits 89683 # Number of row buffer hits during writes +system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing +system.physmem.readRowHits 183194 # Number of row buffer hits during reads +system.physmem.writeRowHits 89685 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.25 # Row buffer hit rate for writes -system.physmem.avgGap 7694496.85 # Average gap between requests +system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes +system.physmem.avgGap 7692449.94 # Average gap between requests system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2709761139750 # Time in different power states -system.physmem.memoryStateTime::REF 94956160000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states +system.physmem.memoryStateTime::REF 94955640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 38946040250 # Time in different power states +system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 358880760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 341016480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 195817875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 186070500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 862524000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 826667400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 486609120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 477763920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 185734248960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 185734248960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 81966350835 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81438405435 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1634297688000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1634760798000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1903902119550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1903764970695 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.524448 # Core power per rank (mW) -system.physmem.averagePower::1 669.476219 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 238011 # Transaction distribution -system.membus.trans_dist::ReadResp 238011 # Transaction distribution -system.membus.trans_dist::WriteReq 30931 # Transaction distribution -system.membus.trans_dist::WriteResp 30931 # Transaction distribution -system.membus.trans_dist::Writeback 112095 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79719 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39980 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13536 # Transaction distribution -system.membus.trans_dist::ReadExReq 30379 # Transaction distribution -system.membus.trans_dist::ReadExResp 13328 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704855 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 826435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 899141 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21031980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21223190 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23542486 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123442 # Total snoops (count) -system.membus.snoop_fanout::samples 498376 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 498376 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 498376 # Request fanout histogram -system.membus.reqLayer0.occupancy 87914995 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11673499 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1620072999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2120142312 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38549614 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 151709 # number of replacements -system.l2c.tags.tagsinuse 64474.290498 # Cycle average of tags in use -system.l2c.tags.total_refs 529875 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 216478 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.447708 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12364.739343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831819 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3875.049948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42732.474457 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.614781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 756.297533 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4653.252093 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.188671 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.652046 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011540 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983800 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 46265 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 18457 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6570 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39426 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2643 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15559 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.705948 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.281631 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6643854 # Number of tag accesses -system.l2c.tags.data_accesses 6643854 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 549 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 36725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207902 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 116 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 47 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11423 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45111 # number of ReadReq hits -system.l2c.ReadReq_hits::total 301987 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252491 # number of Writeback hits -system.l2c.Writeback_hits::total 252491 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 11970 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 853 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12823 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 185 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 180 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 3516 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 1122 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4638 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 40241 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 207902 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 47 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 12545 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 45111 # number of demand (read+write) hits -system.l2c.demand_hits::total 306625 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 549 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 114 # number of overall hits -system.l2c.overall_hits::cpu0.inst 40241 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 207902 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 116 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 47 # number of overall hits -system.l2c.overall_hits::cpu1.inst 12545 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 45111 # number of overall hits -system.l2c.overall_hits::total 306625 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 11298 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18199 # number of ReadReq misses -system.l2c.ReadReq_misses::total 199730 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 9030 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 470 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1259 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1729 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 7024 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 6416 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 13440 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 18322 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8252 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 18199 # number of demand (read+write) misses -system.l2c.demand_misses::total 213170 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 18322 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 168230 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8252 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 18199 # number of overall misses -system.l2c.overall_misses::total 213170 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 956701998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 150016000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 21240863385 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 10890561 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 2732384 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 13622945 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1227450 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 930960 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2158410 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 595061904 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 477250480 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1072312384 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1551763902 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 627266480 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22313175769 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1551763902 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1343500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 627266480 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22313175769 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 700 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 48023 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 131 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13259 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63310 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 501717 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 252491 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 252491 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 21000 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 3518 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 24518 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 655 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1439 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 10540 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 7538 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18078 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 700 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 115 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 58563 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376132 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 131 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 20797 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63310 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 519795 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 700 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 115 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 58563 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376132 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 131 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 20797 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63310 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 519795 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008696 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.235262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.138472 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.398093 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.757533 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.476996 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.717557 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.874913 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.825692 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.666414 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.851154 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.743445 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.008696 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.312860 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.396788 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.410104 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.008696 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.312860 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.396788 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.410104 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84678.881041 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81708.061002 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 106347.886572 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1206.042193 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1025.284803 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1164.852074 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2611.595745 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 739.444003 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1248.357432 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84718.380410 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74384.426434 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 79785.147619 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 104673.151799 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 104673.151799 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 758 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 36.095238 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112095 # number of writebacks -system.l2c.writebacks::total 112095 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 11298 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1836 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 199729 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9030 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 470 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1259 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1729 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 7024 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 6416 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 13440 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 18322 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 8252 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 213169 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 18322 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 8252 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 213169 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 816212498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 127225500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 18781676635 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91207456 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26838142 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 118045598 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4758966 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12646753 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 17405719 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 507430588 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396239520 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 903670108 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1323643086 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 523465020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 19685346743 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1323643086 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 523465020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 19685346743 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518668247 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263087751 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5781755998 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4095979500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150492500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4246472000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614647747 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413580251 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10028227998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235262 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138472 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.398091 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.757533 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.476996 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.717557 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.874913 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.825692 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.666414 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.851154 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.743445 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.410102 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.410102 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72243.981059 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69294.934641 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94035.801686 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10100.493466 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.597373 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.680889 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10125.459574 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10045.077840 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10066.928282 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72242.395786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61758.029925 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67237.359226 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actEnergy::0 358956360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 341235720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 195859125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 186190125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 862929600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 826854600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 486680400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 477919440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 81937929780 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81435296655 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1634313275250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1634754181500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1903888862355 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.523453 # Core power per rank (mW) +system.physmem.averagePower::1 669.476347 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 668242 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 668227 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30931 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30931 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252491 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 92430 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40345 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 132775 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 38935 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 38935 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370727 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368021 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1738748 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41983735 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7870623 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49854358 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291977 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1090667 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033442 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.179788 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1054193 96.66% 96.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36474 3.34% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1090667 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1589069612 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2362873368 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 802585372 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31012 # Transaction distribution -system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59405 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 35 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326655076 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36825386 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 34893743 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17129146 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1674704 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20005904 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14465623 # Number of BTB hits +system.cpu0.branchPred.lookups 34892527 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.306770 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10813555 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 822515 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1024,25 +386,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23970791 # DTB read hits -system.cpu0.dtb.read_misses 62431 # DTB read misses -system.cpu0.dtb.write_hits 17948475 # DTB write hits -system.cpu0.dtb.write_misses 6765 # DTB write misses +system.cpu0.dtb.read_hits 23969265 # DTB read hits +system.cpu0.dtb.read_misses 62663 # DTB read misses +system.cpu0.dtb.write_hits 17948332 # DTB write hits +system.cpu0.dtb.write_misses 6711 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3473 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1381 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1976 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24033222 # DTB read accesses -system.cpu0.dtb.write_accesses 17955240 # DTB write accesses +system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24031928 # DTB read accesses +system.cpu0.dtb.write_accesses 17955043 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41919266 # DTB hits -system.cpu0.dtb.misses 69196 # DTB misses -system.cpu0.dtb.accesses 41988462 # DTB accesses +system.cpu0.dtb.hits 41917597 # DTB hits +system.cpu0.dtb.misses 69374 # DTB misses +system.cpu0.dtb.accesses 41986971 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1064,8 +426,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 70366530 # ITB inst hits -system.cpu0.itb.inst_misses 3846 # ITB inst misses +system.cpu0.itb.inst_hits 70358748 # ITB inst hits +system.cpu0.itb.inst_misses 3854 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1078,79 +440,256 @@ system.cpu0.itb.flush_entries 2220 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7369 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70370376 # ITB inst accesses -system.cpu0.itb.hits 70366530 # DTB hits -system.cpu0.itb.misses 3846 # DTB misses -system.cpu0.itb.accesses 70370376 # DTB accesses -system.cpu0.numCycles 229133691 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses +system.cpu0.itb.hits 70358748 # DTB hits +system.cpu0.itb.misses 3854 # DTB misses +system.cpu0.itb.accesses 70362602 # DTB accesses +system.cpu0.numCycles 229119066 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 109191897 # Number of instructions committed -system.cpu0.committedOps 132018821 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8795011 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1826 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5458210303 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.098450 # CPI: cycles per instruction -system.cpu0.ipc 0.476542 # IPC: instructions per cycle +system.cpu0.committedInsts 109189984 # Number of instructions committed +system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.098352 # CPI: cycles per instruction +system.cpu0.ipc 0.476564 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed -system.cpu0.tickCycles 193242697 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 35890994 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 1983122 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.796419 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 68375163 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1983634 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.469647 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed +system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 714801 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 83782876 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83782876 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 22802755 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22802755 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862558 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16862558 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381551 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 381551 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362630 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362630 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 39665313 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 39665313 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 39665313 # number of overall hits +system.cpu0.dcache.overall_hits::total 39665313 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 537301 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 537301 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 532764 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 532764 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6412 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6412 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20204 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20204 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 1070065 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1070065 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 1070065 # number of overall misses +system.cpu0.dcache.overall_misses::total 1070065 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609674711 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6609674711 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8019150247 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8019150247 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 105707749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 105707749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 437634051 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 437634051 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 14628824958 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14628824958 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 14628824958 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14628824958 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23340056 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23340056 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395322 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17395322 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387963 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387963 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382834 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382834 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 40735378 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40735378 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 40735378 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40735378 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023021 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.023021 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030627 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030627 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016527 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016527 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052775 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052775 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026269 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026269 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026269 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026269 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 517954 # number of writebacks +system.cpu0.dcache.writebacks::total 517954 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42678 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42678 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230706 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 230706 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273384 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 273384 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273384 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 273384 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494623 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 494623 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302058 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 302058 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6411 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6411 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20204 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20204 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796681 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 796681 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796681 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 796681 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5117531439 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5117531439 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4270825900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4270825900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 92832750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92832750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 396783949 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 396783949 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9388357339 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9388357339 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9388357339 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9388357339 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191310497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191310497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803760492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803760492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995070989 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995070989 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021192 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021192 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016525 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052775 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052775 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019557 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019557 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1983566 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.796833 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 68366923 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1984078 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.457780 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796419 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999602 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999602 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796833 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 142701293 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 142701293 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 68375163 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 68375163 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 68375163 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 68375163 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 68375163 # number of overall hits -system.cpu0.icache.overall_hits::total 68375163 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1983656 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1983656 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1983656 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1983656 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1983656 # number of overall misses -system.cpu0.icache.overall_misses::total 1983656 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16542962894 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16542962894 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16542962894 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16542962894 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16542962894 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16542962894 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70358819 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70358819 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70358819 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70358819 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70358819 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70358819 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028193 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028193 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028193 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028193 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028193 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028193 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.632927 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.632927 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8339.632927 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8339.632927 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 142686127 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 142686127 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 68366923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 68366923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 68366923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 68366923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 68366923 # number of overall hits +system.cpu0.icache.overall_hits::total 68366923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1984094 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1984094 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1984094 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1984094 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1984094 # number of overall misses +system.cpu0.icache.overall_misses::total 1984094 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16546799645 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16546799645 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1159,376 +698,326 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1983656 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1983656 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1983656 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1983656 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1983656 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13565509604 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13565509604 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13565509604 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13565509604 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13565509604 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13565509604 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028193 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028193 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.640169 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2764616 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2669805 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 518092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 696796 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 70569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42644 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 93797 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291655 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 282058 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3973433 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393866 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6546649 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127149824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86895095 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313964 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 214376507 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1084116 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4385551 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.219745 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.414074 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3421847 78.03% 78.03% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 963704 21.97% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4385551 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2275908733 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 119359000 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2981732395 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1235696460 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7392491 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 89085972 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17333419 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425629 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16380209 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9025 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6465 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512088 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329549 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 409658 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16201.472263 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3013143 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 425913 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.074550 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2824446064500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4208.967244 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.817277 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.069510 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2196.768436 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.849796 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.256895 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.replacements 409357 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # 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number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77521 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 2613740 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2695501 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 970 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 166 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94231 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 95367 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27951 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27951 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17951 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17951 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3482 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 341 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.547058 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444397 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 55309059 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 55309059 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77781 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4268 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390782 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2472831 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 517951 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 517951 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4630 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 4630 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2244 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2244 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223140 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 223140 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77781 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4268 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 2613922 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034839 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034161 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856683 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856683 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.886557 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.886557 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.857849 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.857849 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888922 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888922 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160660 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160660 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046156 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160439 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160439 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046153 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226643 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24521.881235 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24519.564225 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41623.888313 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17051.028765 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17051.028765 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13230.155535 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13230.155535 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226671 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27546.638258 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27546.638258 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25520.359892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38344.387212 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1536,192 +1025,67 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 714989 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.379861 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40475201 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715501 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.569035 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.379861 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965586 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965586 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83786238 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83786238 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22803865 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22803865 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862785 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16862785 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381543 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 381543 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362585 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362585 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39666650 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 39666650 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39666650 # number of overall hits -system.cpu0.dcache.overall_hits::total 39666650 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 537471 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 537471 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 532850 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 532850 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6422 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6422 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20250 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20250 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1070321 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1070321 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1070321 # number of overall misses -system.cpu0.dcache.overall_misses::total 1070321 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609205728 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6609205728 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8024129751 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8024129751 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 106247249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 106247249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438093543 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 438093543 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14633335479 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14633335479 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14633335479 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14633335479 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23341336 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23341336 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395635 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17395635 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387965 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387965 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40736971 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40736971 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40736971 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40736971 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023027 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.023027 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030631 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030631 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016553 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016553 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052895 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052895 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026274 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026274 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026274 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026274 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12296.860162 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12296.860162 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15058.890403 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15058.890403 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16544.261756 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16544.261756 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21634.249037 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21634.249037 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13671.912892 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13671.912892 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 518095 # number of writebacks -system.cpu0.dcache.writebacks::total 518095 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42683 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42683 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230741 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 230741 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273424 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 273424 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273424 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 273424 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494788 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 494788 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302109 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 302109 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6421 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6421 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20250 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20250 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796897 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 796897 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796897 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 796897 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5118044180 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118044180 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4273159157 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4273159157 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 93352250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93352250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397142457 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397142457 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9391203337 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9391203337 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9391203337 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9391203337 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191390497 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191390497 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803718496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803718496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995108993 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995108993 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021198 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021198 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017367 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017367 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016550 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016550 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052895 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052895 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019562 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019562 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10343.913312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10343.913312 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14144.428524 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14144.428524 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14538.584333 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14538.584333 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19611.973185 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19611.973185 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4041852 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2340524 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 248983 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2647417 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1629039 # Number of BTB hits +system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.branchPred.lookups 4040174 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.533147 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 795039 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 55831 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1745,25 +1109,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4061119 # DTB read hits -system.cpu1.dtb.read_misses 20366 # DTB read misses -system.cpu1.dtb.write_hits 3327004 # DTB write hits -system.cpu1.dtb.write_misses 1507 # DTB write misses +system.cpu1.dtb.read_hits 4061400 # DTB read hits +system.cpu1.dtb.read_misses 20326 # DTB read misses +system.cpu1.dtb.write_hits 3327397 # DTB write hits +system.cpu1.dtb.write_misses 1493 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2038 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 134 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4081485 # DTB read accesses -system.cpu1.dtb.write_accesses 3328511 # DTB write accesses +system.cpu1.dtb.read_accesses 4081726 # DTB read accesses +system.cpu1.dtb.write_accesses 3328890 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7388123 # DTB hits -system.cpu1.dtb.misses 21873 # DTB misses -system.cpu1.dtb.accesses 7409996 # DTB accesses +system.cpu1.dtb.hits 7388797 # DTB hits +system.cpu1.dtb.misses 21819 # DTB misses +system.cpu1.dtb.accesses 7410616 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1785,8 +1149,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7667797 # ITB inst hits -system.cpu1.itb.inst_misses 2228 # ITB inst misses +system.cpu1.itb.inst_hits 7665717 # ITB inst hits +system.cpu1.itb.inst_misses 2240 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1795,82 +1159,256 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1890 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7670025 # ITB inst accesses -system.cpu1.itb.hits 7667797 # DTB hits -system.cpu1.itb.misses 2228 # DTB misses -system.cpu1.itb.accesses 7670025 # DTB accesses -system.cpu1.numCycles 40526065 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses +system.cpu1.itb.hits 7665717 # DTB hits +system.cpu1.itb.misses 2240 # DTB misses +system.cpu1.itb.accesses 7667957 # DTB accesses +system.cpu1.numCycles 40520229 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15860183 # Number of instructions committed -system.cpu1.committedOps 19387635 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1556469 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2802 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5646205885 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.555208 # CPI: cycles per instruction -system.cpu1.ipc 0.391358 # IPC: instructions per cycle +system.cpu1.committedInsts 15863154 # Number of instructions committed +system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.554361 # CPI: cycles per instruction +system.cpu1.ipc 0.391487 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2803 # number of quiesce instructions executed -system.cpu1.tickCycles 29467033 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 11059032 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 893075 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.459055 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6772156 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 893587 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.578620 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed +system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 188500 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits +system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses +system.cpu1.dcache.overall_misses::total 321494 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks +system.cpu1.dcache.writebacks::total 115754 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49471 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 49471 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64927 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 64927 # 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number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492548242 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 303500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 303500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4201413870 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4201413870 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4201413870 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4201413870 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329634997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329634997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202961999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202961999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532596996 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532596996 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042343 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042343 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028199 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028199 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054922 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054922 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250723 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250723 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.036009 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036009 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 893030 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.459009 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6770083 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 893542 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.576681 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459055 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459009 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16225073 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16225073 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6772156 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6772156 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6772156 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6772156 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6772156 # number of overall hits -system.cpu1.icache.overall_hits::total 6772156 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 893587 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 893587 # 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average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8131.667927 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8131.667927 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8131.667927 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16220792 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6770083 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6770083 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6770083 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6770083 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6770083 # 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number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7266670468 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7663625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7663625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7663625 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7663625 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7663625 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7663625 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116595 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.116595 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116595 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.116595 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116595 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.116595 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8132.433023 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8132.433023 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8132.433023 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8132.433023 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1879,362 +1417,310 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893587 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 893587 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 893587 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 893587 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 893587 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 893587 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923590752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923590752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923590752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5923590752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923590752 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5923590752 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116569 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.116569 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.116569 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.002830 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1582924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1137885 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 115746 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 150971 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 76810 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 64398 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787404 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 768912 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6948 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51790 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2615054 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57196928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24920351 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10668 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 94516 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82222463 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 838516 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2085340 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.363825 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.481099 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1326642 63.62% 63.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 758698 36.38% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2085340 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 782793185 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78444000 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1341767498 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381370915 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4282497 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 28163996 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7065047 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40428 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914930 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1457 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7064659 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40510 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914419 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1409 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2607 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105625 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724673 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2627 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105694 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724613 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 79629 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15528.716598 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1138081 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 94994 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.980557 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 80002 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15534.005683 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1138706 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 95380 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.938624 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6912.222509 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 24.793124 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.117245 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2315.760796 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6275.822923 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.421889 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001513 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.141343 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383046 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.947798 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10144 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5192 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6818 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3193 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6881.050205 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.485106 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.098583 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2338.762949 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6287.608842 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.419986 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001617 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142747 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383765 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.948120 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10071 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6676 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3263 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1854 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.619141 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.316895 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21374644 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21374644 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23037 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2415 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993214 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1018666 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 115746 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 115746 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1782 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1782 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 772 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 772 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27747 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27747 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23037 # 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average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27041.387971 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27041.387971 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # 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average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2242,232 +1728,213 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 188481 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.009191 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6997616 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 188846 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.054616 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 475.009191 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927752 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.927752 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14853075 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14853075 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3751603 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3751603 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051213 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3051213 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88863 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88863 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69198 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69198 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 6802816 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6802816 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 6802816 # number of overall hits -system.cpu1.dcache.overall_hits::total 6802816 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 182008 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 182008 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 139434 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139434 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5163 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5163 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23176 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23176 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 321442 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 321442 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 321442 # number of overall misses -system.cpu1.dcache.overall_misses::total 321442 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2744686684 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2744686684 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3345931004 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3345931004 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93833250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 93833250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540125753 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 540125753 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 353500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 353500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6090617688 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6090617688 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6090617688 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6090617688 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3933611 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3933611 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3190647 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3190647 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94026 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 94026 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92374 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92374 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7124258 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7124258 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7124258 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7124258 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046270 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046270 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043701 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043701 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054910 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054910 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250893 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250893 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045119 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.045119 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045119 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.045119 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15080.033207 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15080.033207 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23996.521681 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23996.521681 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18174.171993 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18174.171993 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23305.391483 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23305.391483 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18947.796766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18947.796766 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 115746 # number of writebacks -system.cpu1.dcache.writebacks::total 115746 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15462 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15462 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49475 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 49475 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 64937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 64937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166546 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166546 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89959 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89959 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5163 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5163 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23176 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23176 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256505 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 256505 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256505 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256505 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202025254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202025254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2000006836 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2000006836 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83498750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83498750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492542247 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492542247 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 337500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 337500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4202032090 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4202032090 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4202032090 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4202032090 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329591498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329591498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202938498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202938498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532529996 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532529996 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042339 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042339 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028195 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028195 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054910 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054910 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250893 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250893 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.036004 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036004 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13221.724052 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13221.724052 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22232.426283 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22232.426283 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16172.525663 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16172.525663 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21252.254358 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21252.254358 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 838592 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution +system.iobus.trans_dist::WriteReq 59407 # Transaction distribution +system.iobus.trans_dist::WriteResp 59440 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36417 # number of replacements -system.iocache.tags.tagsinuse 0.992209 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992209 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062013 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062013 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328483 # Number of tag accesses -system.iocache.tags.data_accesses 328483 # Number of data accesses +system.iocache.tags.tag_accesses 328467 # Number of tag accesses +system.iocache.tags.data_accesses 328467 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses system.iocache.ReadReq_misses::total 243 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 35 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 35 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31692627 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31692627 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31692627 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31692627 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31692627 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31692627 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36259 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36259 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000965 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000965 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130422.333333 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130422.333333 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130422.333333 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130422.333333 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128617.806584 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128617.806584 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128617.806584 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2482,28 +1949,565 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19056127 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19056127 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2259252335 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2259252335 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19056127 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19056127 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19056127 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19056127 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18617627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18617627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261621825 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261621825 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18617627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18617627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18617627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18617627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78420.275720 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78420.275720 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 151810 # number of replacements +system.l2c.tags.tagsinuse 64480.586594 # Cycle average of tags in use +system.l2c.tags.total_refs 529933 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 216565 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.446993 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12374.174406 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3874.361594 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.891665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 757.615436 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4654.298093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.188815 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059118 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.651968 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011560 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071019 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983896 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 46322 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 18386 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6596 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39440 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2604 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15495 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.706818 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.280548 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6644341 # Number of tag accesses +system.l2c.tags.data_accesses 6644341 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 563 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 36701 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207577 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 56 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11433 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45418 # number of ReadReq hits +system.l2c.ReadReq_hits::total 301993 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252536 # number of Writeback hits +system.l2c.Writeback_hits::total 252536 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 11942 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 830 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12772 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 205 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 179 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 3525 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 1107 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4632 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 40226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 207577 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 56 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 12540 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 45418 # number of demand (read+write) hits +system.l2c.demand_hits::total 306625 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 563 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 116 # number of overall hits +system.l2c.overall_hits::cpu0.inst 40226 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 207577 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 129 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 56 # number of overall hits +system.l2c.overall_hits::cpu1.inst 12540 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 45418 # number of overall hits +system.l2c.overall_hits::total 306625 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 11286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1852 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18208 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199810 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 9028 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11693 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 461 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1254 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 7011 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 6410 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 13421 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 18297 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8262 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 18208 # number of demand (read+write) misses +system.l2c.demand_misses::total 213231 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 18297 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 168297 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8262 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 18208 # number of overall misses +system.l2c.overall_misses::total 213231 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 955847998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 151717498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 21276600608 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 10528075 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 2736385 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 13264460 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1131453 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1006958 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2138411 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 592519659 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 475914481 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1068434140 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1548367657 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1150500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 627631979 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22345034748 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1548367657 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1150500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 627631979 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22345034748 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 714 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 117 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47987 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 375874 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 56 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13285 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63626 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 501803 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 252536 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 252536 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 20970 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 3495 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24465 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 666 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 1433 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2099 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 10536 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 7517 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18053 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 117 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 58523 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 375874 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 144 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 56 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 20802 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63626 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 519856 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 117 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 58523 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 375874 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 144 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 56 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 20802 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63626 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 519856 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008547 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.235189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.139405 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.398184 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430520 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.762518 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.477948 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.692192 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.875087 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.817056 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.665433 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.852734 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.743422 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.008547 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.312646 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.397173 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.410173 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.008547 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.312646 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.397173 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.410173 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76700 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 106484.162995 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1166.158064 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1026.786116 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1134.393227 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2454.344902 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 802.996810 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1246.886880 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 79609.130467 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 104792.618090 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 104792.618090 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 845 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 32.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 112127 # number of writebacks +system.l2c.writebacks::total 112127 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # 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number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91196953 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26828647 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 118025600 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4664957 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12607247 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 17272204 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 505062337 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 394979019 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 900041356 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1320537835 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 965000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 523708017 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 19716579214 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1320537835 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 965000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 523708017 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 19716579214 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518590247 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263108750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5781698997 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096001500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150494000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4246495500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614591747 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413602750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10028194497 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.139405 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.398182 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430520 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.762518 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.477948 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.692192 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.875087 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817056 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.665433 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.852734 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.743422 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.410171 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.410171 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 238091 # Transaction distribution +system.membus.trans_dist::ReadResp 238091 # Transaction distribution +system.membus.trans_dist::WriteReq 30933 # Transaction distribution +system.membus.trans_dist::WriteResp 30933 # Transaction distribution +system.membus.trans_dist::Writeback 112127 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution +system.membus.trans_dist::ReadExReq 30363 # Transaction distribution +system.membus.trans_dist::ReadExResp 13313 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123399 # Total snoops (count) +system.membus.snoop_fanout::samples 498406 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 498406 # Request fanout histogram +system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291964 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 69d9fc0b1..8921a3479 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852223 # Number of seconds simulated -sim_ticks 2852222670000 # Number of ticks simulated -final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852237 # Number of seconds simulated +sim_ticks 2852237227000 # Number of ticks simulated +final_tick 2852237227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 166317 # Simulator instruction rate (inst/s) -host_op_rate 201081 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4259610797 # Simulator tick rate (ticks/s) -host_mem_usage 558772 # Number of bytes of host memory used -host_seconds 669.60 # Real time elapsed on the host -sim_insts 111365458 # Number of instructions simulated -sim_ops 134642914 # Number of ops (including micro ops) simulated +host_inst_rate 157725 # Simulator instruction rate (inst/s) +host_op_rate 190692 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4039440180 # Simulator tick rate (ticks/s) +host_mem_usage 566224 # Number of bytes of host memory used +host_seconds 706.10 # Real time elapsed on the host +sim_insts 111368950 # Number of instructions simulated +sim_ops 134647110 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.dtb.walker 6208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10897572 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory -system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::total 10904868 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1667392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1667392 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5682816 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 8018676 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 97 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 170794 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170908 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 88794 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 129399 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3820710 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3823268 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 584591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 584591 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1992407 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170902 # Number of read requests accepted -system.physmem.writeReqs 129383 # Number of write requests accepted -system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue -system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::realview.ide 812813 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811364 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1992407 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3826854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 813150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6634632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170908 # Number of read requests accepted +system.physmem.writeReqs 129399 # Number of write requests accepted +system.physmem.readBursts 170908 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 129399 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10927552 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10560 # Total number of bytes read from write queue +system.physmem.bytesWritten 8032256 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10904868 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8018676 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10513 # Per bank write bursts -system.physmem.perBankRdBursts::1 10240 # Per bank write bursts -system.physmem.perBankRdBursts::2 10772 # Per bank write bursts -system.physmem.perBankRdBursts::3 10550 # Per bank write bursts -system.physmem.perBankRdBursts::4 13501 # Per bank write bursts -system.physmem.perBankRdBursts::5 10124 # Per bank write bursts -system.physmem.perBankRdBursts::6 11177 # Per bank write bursts -system.physmem.perBankRdBursts::7 10891 # Per bank write bursts -system.physmem.perBankRdBursts::8 10227 # Per bank write bursts -system.physmem.perBankRdBursts::9 10892 # Per bank write bursts -system.physmem.perBankRdBursts::10 10093 # Per bank write bursts -system.physmem.perBankRdBursts::11 9609 # Per bank write bursts -system.physmem.perBankRdBursts::12 10331 # Per bank write bursts -system.physmem.perBankRdBursts::13 11217 # Per bank write bursts -system.physmem.perBankRdBursts::14 10288 # Per bank write bursts -system.physmem.perBankRdBursts::15 10317 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4597 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10514 # Per bank write bursts +system.physmem.perBankRdBursts::1 10246 # Per bank write bursts +system.physmem.perBankRdBursts::2 10769 # Per bank write bursts +system.physmem.perBankRdBursts::3 10552 # Per bank write bursts +system.physmem.perBankRdBursts::4 13499 # Per bank write bursts +system.physmem.perBankRdBursts::5 10126 # Per bank write bursts +system.physmem.perBankRdBursts::6 11178 # Per bank write bursts +system.physmem.perBankRdBursts::7 10889 # Per bank write bursts +system.physmem.perBankRdBursts::8 10228 # Per bank write bursts +system.physmem.perBankRdBursts::9 10887 # Per bank write bursts +system.physmem.perBankRdBursts::10 10100 # Per bank write bursts +system.physmem.perBankRdBursts::11 9610 # Per bank write bursts +system.physmem.perBankRdBursts::12 10315 # Per bank write bursts +system.physmem.perBankRdBursts::13 11222 # Per bank write bursts +system.physmem.perBankRdBursts::14 10292 # Per bank write bursts +system.physmem.perBankRdBursts::15 10316 # Per bank write bursts system.physmem.perBankWrBursts::0 7730 # Per bank write bursts -system.physmem.perBankWrBursts::1 7662 # Per bank write bursts -system.physmem.perBankWrBursts::2 8408 # Per bank write bursts -system.physmem.perBankWrBursts::3 8127 # Per bank write bursts -system.physmem.perBankWrBursts::4 7860 # Per bank write bursts +system.physmem.perBankWrBursts::1 7667 # Per bank write bursts +system.physmem.perBankWrBursts::2 8410 # Per bank write bursts +system.physmem.perBankWrBursts::3 8128 # Per bank write bursts +system.physmem.perBankWrBursts::4 7856 # Per bank write bursts system.physmem.perBankWrBursts::5 7340 # Per bank write bursts -system.physmem.perBankWrBursts::6 8206 # Per bank write bursts -system.physmem.perBankWrBursts::7 8039 # Per bank write bursts -system.physmem.perBankWrBursts::8 7784 # Per bank write bursts -system.physmem.perBankWrBursts::9 8077 # Per bank write bursts -system.physmem.perBankWrBursts::10 7518 # Per bank write bursts +system.physmem.perBankWrBursts::6 8209 # Per bank write bursts +system.physmem.perBankWrBursts::7 8042 # Per bank write bursts +system.physmem.perBankWrBursts::8 7786 # Per bank write bursts +system.physmem.perBankWrBursts::9 8073 # Per bank write bursts +system.physmem.perBankWrBursts::10 7525 # Per bank write bursts system.physmem.perBankWrBursts::11 7421 # Per bank write bursts -system.physmem.perBankWrBursts::12 7767 # Per bank write bursts -system.physmem.perBankWrBursts::13 8402 # Per bank write bursts -system.physmem.perBankWrBursts::14 7544 # Per bank write bursts +system.physmem.perBankWrBursts::12 7760 # Per bank write bursts +system.physmem.perBankWrBursts::13 8405 # Per bank write bursts +system.physmem.perBankWrBursts::14 7549 # Per bank write bursts system.physmem.perBankWrBursts::15 7603 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2852222186000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2852236741500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 170347 # Read request sizes (log2) +system.physmem.readPktSize::6 170353 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 125002 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 164585 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6110 # What read queue length does an incoming req see +system.physmem.writePktSize::6 125018 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164527 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6169 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,117 +158,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2508 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7495 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 6726 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6577 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6482 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6500 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 212 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14417 23.70% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 3 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60829 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 311.689227 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.313026 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.369125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22276 36.62% 36.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14416 23.70% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6737 11.08% 71.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3572 5.87% 77.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2597 4.27% 81.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1607 2.64% 84.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1084 1.78% 85.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1076 1.77% 87.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7464 12.27% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60829 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6321 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.008859 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 576.510415 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6319 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5533 87.67% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 0.55% 88.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 30 0.48% 88.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 215 3.41% 92.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 199 3.15% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 15 0.24% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.27% 95.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.30% 96.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 19 0.30% 96.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.10% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.06% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 155 2.46% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.08% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.10% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.05% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 12 0.19% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.05% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.08% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.10% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads -system.physmem.totQLat 1715938250 # Total ticks spent queuing -system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6321 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6321 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.855086 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.377929 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.560499 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5522 87.36% 87.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 41 0.65% 88.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 34 0.54% 88.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 217 3.43% 91.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 214 3.39% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 10 0.16% 95.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 16 0.25% 95.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 20 0.32% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 24 0.38% 96.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.03% 96.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 162 2.56% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.05% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.19% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.08% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.11% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6321 # Writes before turning the bus around for reads +system.physmem.totQLat 1722371500 # Total ticks spent queuing +system.physmem.totMemAccLat 4923802750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 853715000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10087.51 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28837.51 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s @@ -278,36 +276,36 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing -system.physmem.readRowHits 140944 # Number of row buffer hits during reads -system.physmem.writeRowHits 94455 # Number of row buffer hits during writes +system.physmem.avgWrQLen 26.39 # Average write queue length when enqueuing +system.physmem.readRowHits 140948 # Number of row buffer hits during reads +system.physmem.writeRowHits 94469 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes -system.physmem.avgGap 9498383.82 # Average gap between requests +system.physmem.writeRowHitRate 75.26 # Row buffer hit rate for writes +system.physmem.avgGap 9497736.45 # Average gap between requests system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states -system.physmem.memoryStateTime::REF 95241900000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2712717626000 # Time in different power states +system.physmem.memoryStateTime::REF 95242420000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states +system.physmem.memoryStateTime::ACT 44277091000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.406404 # Core power per rank (mW) -system.physmem.averagePower::1 669.363949 # Core power per rank (mW) +system.physmem.actEnergy::0 234707760 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 225159480 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 128064750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122854875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 684629400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 647158200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 410715360 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 402550560 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 186294173520 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 186294173520 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 83068916085 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 82611072135 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1638474130500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1638875748000 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1909295337375 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1909178716770 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.403001 # Core power per rank (mW) +system.physmem.averagePower::1 669.362113 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory @@ -320,207 +318,22 @@ system.realview.nvmem.bw_inst_read::cpu.inst 157 system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 71842 # Transaction distribution -system.membus.trans_dist::ReadResp 71842 # Transaction distribution -system.membus.trans_dist::WriteReq 27607 # Transaction distribution -system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 88778 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution -system.membus.trans_dist::ReadExReq 129869 # Transaction distribution -system.membus.trans_dist::ReadExResp 129869 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 297178 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 297178 # Request fanout histogram -system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 30769128 # Number of BP lookups -system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits +system.cpu.branchPred.lookups 30773662 # Number of BP lookups +system.cpu.branchPred.condPredicted 16735793 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2481146 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18414792 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13204104 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.703791 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7765871 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1476448 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -544,25 +357,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24572928 # DTB read hits -system.cpu.dtb.read_misses 58429 # DTB read misses -system.cpu.dtb.write_hits 19368405 # DTB write hits -system.cpu.dtb.write_misses 5913 # DTB write misses +system.cpu.dtb.read_hits 24574985 # DTB read hits +system.cpu.dtb.read_misses 58557 # DTB read misses +system.cpu.dtb.write_hits 19368965 # DTB write hits +system.cpu.dtb.write_misses 5915 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1821 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24631357 # DTB read accesses -system.cpu.dtb.write_accesses 19374318 # DTB write accesses +system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24633542 # DTB read accesses +system.cpu.dtb.write_accesses 19374880 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43941333 # DTB hits -system.cpu.dtb.misses 64342 # DTB misses -system.cpu.dtb.accesses 44005675 # DTB accesses +system.cpu.dtb.hits 43943950 # DTB hits +system.cpu.dtb.misses 64472 # DTB misses +system.cpu.dtb.accesses 44008422 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -584,8 +397,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 57038768 # ITB inst hits -system.cpu.itb.inst_misses 5411 # ITB inst misses +system.cpu.itb.inst_hits 57039019 # ITB inst hits +system.cpu.itb.inst_misses 5418 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -594,83 +407,250 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2977 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2981 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8664 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8633 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57044179 # ITB inst accesses -system.cpu.itb.hits 57038768 # DTB hits -system.cpu.itb.misses 5411 # DTB misses -system.cpu.itb.accesses 57044179 # DTB accesses -system.cpu.numCycles 313347638 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57044437 # ITB inst accesses +system.cpu.itb.hits 57039019 # DTB hits +system.cpu.itb.misses 5418 # DTB misses +system.cpu.itb.accesses 57044437 # DTB accesses +system.cpu.numCycles 313379229 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 111365458 # Number of instructions committed -system.cpu.committedOps 134642914 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7897593 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 111368950 # Number of instructions committed +system.cpu.committedOps 134647110 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7900477 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5391144295 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.813688 # CPI: cycles per instruction -system.cpu.ipc 0.355405 # IPC: instructions per cycle +system.cpu.quiesceCycles 5391141904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.813883 # CPI: cycles per instruction +system.cpu.ipc 0.355381 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 224151816 # Number of cycles that the object actually ticked -system.cpu.idleCycles 89195822 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 2897350 # number of replacements -system.cpu.icache.tags.tagsinuse 511.427915 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54131849 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897862 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.679926 # Average number of references to valid blocks. +system.cpu.tickCycles 224160135 # Number of cycles that the object actually ticked +system.cpu.idleCycles 89219094 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 841413 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.953450 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42452187 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 841925 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.422766 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 279721250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953450 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # 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number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8654598086 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8654598086 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21588798306 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21588798306 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117927750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 117927750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 52502 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 52502 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 30243396392 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30243396392 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 30243396392 # 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miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026374 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.026374 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026374 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14827.286362 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14827.286362 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39881.251639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39881.251639 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14184.237431 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14184.237431 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26251 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26251 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26882.517208 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26882.517208 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26882.517208 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 697938 # number of writebacks +system.cpu.dcache.writebacks::total 697938 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 45858 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45858 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 242707 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 242707 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 288565 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 288565 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 288565 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 288565 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 537836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298620 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298620 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8314 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8314 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 836456 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 836456 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 836456 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 836456 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6884995145 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6884995145 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11268709155 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11268709155 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101270250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101270250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18153704300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18153704300 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18153704300 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18153704300 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790985000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790985000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439182000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439182000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230167000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230167000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022501 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015923 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015923 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017835 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019609 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019609 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019609 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12801.290998 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12801.290998 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37735.949216 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37735.949216 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12180.689199 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12180.689199 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24249 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24249 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21703.119232 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21703.119232 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 2897611 # number of replacements +system.cpu.icache.tags.tagsinuse 511.427780 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54131846 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2898123 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.678243 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 15213015250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.427915 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998883 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998883 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 511.427780 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998882 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998882 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 200 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 59927594 # Number of tag accesses -system.cpu.icache.tags.data_accesses 59927594 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54131849 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54131849 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54131849 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54131849 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54131849 # number of overall hits -system.cpu.icache.overall_hits::total 54131849 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897873 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897873 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897873 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897873 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897873 # number of overall misses -system.cpu.icache.overall_misses::total 2897873 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39140139756 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39140139756 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39140139756 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39140139756 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39140139756 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39140139756 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57029722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57029722 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57029722 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57029722 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57029722 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57029722 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050813 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050813 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050813 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050813 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050813 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050813 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.506240 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.506240 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.506240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.506240 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.506240 # average overall miss latency +system.cpu.icache.tags.tag_accesses 59928115 # Number of tag accesses +system.cpu.icache.tags.data_accesses 59928115 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54131846 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54131846 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54131846 # 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number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -679,225 +659,176 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897873 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897873 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897873 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897873 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897873 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897873 # 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number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2898135 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33339952973 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33339952973 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33339952973 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33339952973 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33339952973 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33339952973 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222062750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222062750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222062750 # 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average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.231937 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.231937 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050818 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050818 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050818 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050818 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11503.933727 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11503.933727 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11503.933727 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11503.933727 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11503.933727 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11503.933727 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295755 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5801712 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2503299 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 155961 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8476265 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185653696 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98670557 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276272 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284619693 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60174 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4573282 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4573282 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3010555155 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4356749506 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1339516197 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 97514 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65073.344541 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4041263 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162774 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.827448 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 97521 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65074.207270 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4042767 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162784 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.835162 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47542.577135 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 54.389093 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.009502 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 17476.368811 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.725442 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000830 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47538.276045 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 53.278527 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000399 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 17482.652299 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.725377 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000813 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266668 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992940 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 44 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65216 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 44 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.266764 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992954 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 40 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65223 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 40 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2322 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6967 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55801 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995117 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36568997 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36568997 # 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Number of tag accesses +system.cpu.l2cache.tags.data_accesses 36581031 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69052 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4779 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 3406716 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3480547 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 697938 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 697938 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.inst 45 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.inst 164068 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164068 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 68967 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4789 # 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Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 358 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 175160699 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 175160699 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 23317429 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23317429 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 18211581 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18211581 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457826 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457826 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 460320 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460322 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460322 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42653384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42653384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42653384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42653384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024398 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024398 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028863 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028863 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017842 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017842 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.026361 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026361 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.026361 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026361 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14821.128911 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14821.128911 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39884.829257 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39884.829257 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14186.245040 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14186.245040 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst 26501 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26886.467834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26886.467834 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26886.467834 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # 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number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 288570 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 288570 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 537236 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 537236 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 298568 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298568 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 8317 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8317 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 835804 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 835804 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 835804 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 835804 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 6874982646 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6874982646 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11266915159 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11266915159 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 101324000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 101324000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18141897805 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18141897805 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18141897805 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18141897805 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5791016000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791016000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439188000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439188000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230204000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230204000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022478 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 3576313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3576217 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295804 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295804 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802238 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2505111 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15298 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156293 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8478940 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185670592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98744797 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276596 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284711109 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 60360 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4574965 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.007969 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088914 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4538506 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36459 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4574965 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3011909666 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 4357140777 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1340495452 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 10517000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 87146500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 30195 # Transaction distribution +system.iobus.trans_dist::ReadResp 30195 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36804753 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.031563 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 1.031563 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064473 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064473 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1188,12 +1103,12 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 27956377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 27956377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 27956377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 27956377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 27956377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 27956377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1208,12 +1123,12 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 119471.696581 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 119471.696581 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 119471.696581 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 119471.696581 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1228,28 +1143,111 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 15787377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 15787377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2211427725 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2211427725 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 15787377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 15787377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 15787377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 15787377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67467.423077 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 67467.423077 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 71836 # Transaction distribution +system.membus.trans_dist::ReadResp 71836 # Transaction distribution +system.membus.trans_dist::WriteReq 27607 # Transaction distribution +system.membus.trans_dist::WriteResp 27607 # Transaction distribution +system.membus.trans_dist::Writeback 88794 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4595 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution +system.membus.trans_dist::ReadExReq 129881 # Transaction distribution +system.membus.trans_dist::ReadExResp 129881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448536 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 628865 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16604248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16768029 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19087325 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 219 # Total snoops (count) +system.membus.snoop_fanout::samples 297195 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 297195 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 297195 # Request fanout histogram +system.membus.reqLayer0.occupancy 87032500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1386266250 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1718628403 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38334247 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index b1bf82ddf..7a2aefe62 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -4,66 +4,66 @@ sim_seconds 2.826844 # Nu sim_ticks 2826844351500 # Number of ticks simulated final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73855 # Simulator instruction rate (inst/s) -host_op_rate 89582 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1844239732 # Simulator tick rate (ticks/s) -host_mem_usage 559768 # Number of bytes of host memory used -host_seconds 1532.80 # Real time elapsed on the host -sim_insts 113205077 # Number of instructions simulated -sim_ops 137311743 # Number of ops (including micro ops) simulated +host_inst_rate 74392 # Simulator instruction rate (inst/s) +host_op_rate 90233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1857645684 # Simulator tick rate (ticks/s) +host_mem_usage 566256 # Number of bytes of host memory used +host_seconds 1521.74 # Real time elapsed on the host +sim_insts 113204796 # Number of instructions simulated +sim_ops 137311416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 172165 # Number of read requests accepted system.physmem.writeReqs 131231 # Number of write requests accepted system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10989 # Per bank write bursts @@ -75,7 +75,7 @@ system.physmem.perBankRdBursts::5 10546 # Pe system.physmem.perBankRdBursts::6 11171 # Per bank write bursts system.physmem.perBankRdBursts::7 11539 # Per bank write bursts system.physmem.perBankRdBursts::8 10356 # Per bank write bursts -system.physmem.perBankRdBursts::9 11055 # Per bank write bursts +system.physmem.perBankRdBursts::9 11056 # Per bank write bursts system.physmem.perBankRdBursts::10 10496 # Per bank write bursts system.physmem.perBankRdBursts::11 9259 # Per bank write bursts system.physmem.perBankRdBursts::12 10183 # Per bank write bursts @@ -115,8 +115,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 126850 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see @@ -162,32 +162,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see @@ -211,44 +211,44 @@ system.physmem.wrQLenPdf::60 20 # Wh system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads @@ -266,13 +266,13 @@ system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Wr system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads -system.physmem.totQLat 2071957750 # Total ticks spent queuing -system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads +system.physmem.totQLat 2072280000 # Total ticks spent queuing +system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s @@ -283,35 +283,35 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing -system.physmem.readRowHits 141999 # Number of row buffer hits during reads -system.physmem.writeRowHits 95218 # Number of row buffer hits during writes +system.physmem.readRowHits 142002 # Number of row buffer hits during reads +system.physmem.writeRowHits 95212 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes system.physmem.avgGap 9317341.50 # Average gap between requests -system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states system.physmem.memoryStateTime::REF 94394300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states +system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.335912 # Core power per rank (mW) -system.physmem.averagePower::1 669.239814 # Core power per rank (mW) +system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.336036 # Core power per rank (mW) +system.physmem.averagePower::1 669.240113 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory @@ -324,207 +324,22 @@ system.realview.nvmem.bw_inst_read::cpu.inst 45 system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 67834 # Transaction distribution -system.membus.trans_dist::ReadResp 67833 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 90626 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135127 # Transaction distribution -system.membus.trans_dist::ReadExResp 135127 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 205 # Total snoops (count) -system.membus.snoop_fanout::samples 300222 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 300222 # Request fanout histogram -system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46964481 # Number of BP lookups -system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits +system.cpu.branchPred.lookups 46964274 # Number of BP lookups +system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -548,9 +363,9 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24601451 # DTB read hits +system.cpu.checker.dtb.read_hits 24601402 # DTB read hits system.cpu.checker.dtb.read_misses 8241 # DTB read misses -system.cpu.checker.dtb.write_hits 19645361 # DTB write hits +system.cpu.checker.dtb.write_hits 19645330 # DTB write hits system.cpu.checker.dtb.write_misses 1441 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -561,12 +376,12 @@ system.cpu.checker.dtb.align_faults 0 # Nu system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24609692 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19646802 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24609643 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19646771 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44246812 # DTB hits +system.cpu.checker.dtb.hits 44246732 # DTB hits system.cpu.checker.dtb.misses 9682 # DTB misses -system.cpu.checker.dtb.accesses 44256494 # DTB accesses +system.cpu.checker.dtb.accesses 44256414 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -588,7 +403,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 115909457 # ITB inst hits +system.cpu.checker.itb.inst_hits 115909165 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -605,11 +420,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115914283 # ITB inst accesses -system.cpu.checker.itb.hits 115909457 # DTB hits +system.cpu.checker.itb.inst_accesses 115913991 # ITB inst accesses +system.cpu.checker.itb.hits 115909165 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115914283 # DTB accesses -system.cpu.checker.numCycles 139168167 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115913991 # DTB accesses +system.cpu.checker.numCycles 139167829 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -635,9 +450,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25471928 # DTB read hits -system.cpu.dtb.read_misses 60410 # DTB read misses -system.cpu.dtb.write_hits 19919780 # DTB write hits +system.cpu.dtb.read_hits 25471879 # DTB read hits +system.cpu.dtb.read_misses 60408 # DTB read misses +system.cpu.dtb.write_hits 19919747 # DTB write hits system.cpu.dtb.write_misses 9388 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA @@ -648,12 +463,12 @@ system.cpu.dtb.align_faults 351 # Nu system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532338 # DTB read accesses -system.cpu.dtb.write_accesses 19929168 # DTB write accesses +system.cpu.dtb.read_accesses 25532287 # DTB read accesses +system.cpu.dtb.write_accesses 19929135 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45391708 # DTB hits -system.cpu.dtb.misses 69798 # DTB misses -system.cpu.dtb.accesses 45461506 # DTB accesses +system.cpu.dtb.hits 45391626 # DTB hits +system.cpu.dtb.misses 69796 # DTB misses +system.cpu.dtb.accesses 45461422 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -675,7 +490,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66240861 # ITB inst hits +system.cpu.itb.inst_hits 66240582 # ITB inst hits system.cpu.itb.inst_misses 11936 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -692,91 +507,91 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66252797 # ITB inst accesses -system.cpu.itb.hits 66240861 # DTB hits +system.cpu.itb.inst_accesses 66252518 # ITB inst accesses +system.cpu.itb.hits 66240582 # DTB hits system.cpu.itb.misses 11936 # DTB misses -system.cpu.itb.accesses 66252797 # DTB accesses -system.cpu.numCycles 260549216 # number of cpu cycles simulated +system.cpu.itb.accesses 66252518 # DTB accesses +system.cpu.numCycles 260548868 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full +system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -784,9 +599,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -815,13 +630,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -849,97 +664,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued +system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued system.cpu.iq.rate 0.550285 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 200927 # number of nop insts executed -system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544157 # Number of branches executed -system.cpu.iew.exec_stores 20882594 # Number of stores executed +system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544085 # Number of branches executed +system.cpu.iew.exec_stores 20882571 # Number of stores executed system.cpu.iew.exec_rate 0.546668 # Inst execution rate -system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301722 # num instructions producing a value -system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value +system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301578 # num instructions producing a value +system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113359982 # Number of instructions committed -system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113359701 # Number of instructions committed +system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45531388 # Number of memory references committed -system.cpu.commit.loads 24928306 # Number of loads committed +system.cpu.commit.refs 45531319 # Number of memory references committed +system.cpu.commit.loads 24928258 # Number of loads committed system.cpu.commit.membars 814674 # Number of memory barriers committed -system.cpu.commit.branches 26060542 # Number of branches committed +system.cpu.commit.branches 26060472 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120282409 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896404 # Number of function calls committed. +system.cpu.commit.int_insts 120282111 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896381 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -967,90 +782,222 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373371044 # The number of ROB reads -system.cpu.rob.rob_writes 293051212 # The number of ROB writes -system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113205077 # Number of Instructions Simulated -system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads +system.cpu.rob.rob_reads 373370450 # The number of ROB reads +system.cpu.rob.rob_writes 293050441 # The number of ROB writes +system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113204796 # Number of Instructions Simulated +system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155870959 # number of integer regfile reads -system.cpu.int_regfile_writes 88663006 # number of integer regfile writes +system.cpu.int_regfile_reads 155870535 # number of integer regfile reads +system.cpu.int_regfile_writes 88662744 # number of integer regfile writes system.cpu.fp_regfile_reads 9591 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503160198 # number of cc regfile reads -system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes -system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads +system.cpu.cc_regfile_reads 503158962 # number of cc regfile reads +system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes +system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65488 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3525412 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1894038 # number of replacements +system.cpu.dcache.tags.replacements 837744 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits +system.cpu.dcache.overall_hits::total 39265000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4451395 # number of overall misses +system.cpu.dcache.overall_misses::total 4451395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897569146 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks +system.cpu.dcache.writebacks::total 695413 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414154 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713416 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713416 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832722 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832722 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5341815166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5341815166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883724205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883724205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479869001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479869001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225539371 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17225539371 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18705408372 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18705408372 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792724250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792724250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440459453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440459453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233183703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233183703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 1894031 # number of replacements system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 64256441 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894543 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.916591 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy @@ -1061,44 +1008,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 170 system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits -system.cpu.icache.overall_hits::total 64256715 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses -system.cpu.icache.overall_misses::total 1981457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 68132454 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68132454 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64256441 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64256441 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64256441 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64256441 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64256441 # 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number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26762198879 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66237893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66237893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66237893 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66237893 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66237893 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66237893 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.357398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.357398 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked @@ -1107,24 +1054,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86889 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86889 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86889 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86889 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86889 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86889 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894563 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894563 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894563 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894563 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894563 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894563 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22159944091 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22159944091 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22159944091 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22159944091 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22159944091 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22159944091 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles @@ -1135,28 +1082,28 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 98619 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65077.788294 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3020947 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.439298 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617940 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy @@ -1173,31 +1120,31 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468096 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695413 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695413 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # 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average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1425,191 +1372,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 837746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits -system.cpu.dcache.overall_hits::total 39265074 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses -system.cpu.dcache.overall_misses::total 4451402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks -system.cpu.dcache.writebacks::total 695414 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65488 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 3525400 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1695,6 +1612,89 @@ system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 67834 # Transaction distribution +system.membus.trans_dist::ReadResp 67833 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 90626 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution +system.membus.trans_dist::ReadExReq 135127 # Transaction distribution +system.membus.trans_dist::ReadExResp 135127 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 205 # Total snoops (count) +system.membus.snoop_fanout::samples 300222 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 300222 # Request fanout histogram +system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3996d6a6b..3b1cffd2f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.824341 # Number of seconds simulated -sim_ticks 2824340874000 # Number of ticks simulated -final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.824366 # Number of seconds simulated +sim_ticks 2824365837500 # Number of ticks simulated +final_tick 2824365837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96866 # Simulator instruction rate (inst/s) -host_op_rate 117519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2277239721 # Simulator tick rate (ticks/s) -host_mem_usage 609056 # Number of bytes of host memory used -host_seconds 1240.25 # Real time elapsed on the host -sim_insts 120137719 # Number of instructions simulated -sim_ops 145752951 # Number of ops (including micro ops) simulated +host_inst_rate 90810 # Simulator instruction rate (inst/s) +host_op_rate 110172 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2134851185 # Simulator tick rate (ticks/s) +host_mem_usage 669748 # Number of bytes of host memory used +host_seconds 1322.98 # Real time elapsed on the host +sim_insts 120140086 # Number of instructions simulated +sim_ops 145755972 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 286496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1047804 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10514048 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory -system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 32208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 549728 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1343808 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 13778252 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 286496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 32208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7259968 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 9596048 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6722 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 16897 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 164282 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory -system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 20997 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 218146 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 113437 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 154097 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 101437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 370987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3722623 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 11404 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 194638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 475791 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4878352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 101437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11404 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112841 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2570477 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820834 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3397594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2570477 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 101437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 377256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3722623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 218132 # Number of read requests accepted -system.physmem.writeReqs 154134 # Number of write requests accepted -system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue -system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 11404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 194652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 475791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 821174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8275946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 218146 # Number of read requests accepted +system.physmem.writeReqs 154097 # Number of write requests accepted +system.physmem.readBursts 218146 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 154097 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13946112 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15232 # Total number of bytes read from write queue +system.physmem.bytesWritten 9610368 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13778252 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9596048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 238 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13731 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 13753 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13737 # Per bank write bursts system.physmem.perBankRdBursts::1 13637 # Per bank write bursts -system.physmem.perBankRdBursts::2 14382 # Per bank write bursts -system.physmem.perBankRdBursts::3 14282 # Per bank write bursts -system.physmem.perBankRdBursts::4 15946 # Per bank write bursts -system.physmem.perBankRdBursts::5 13017 # Per bank write bursts -system.physmem.perBankRdBursts::6 13909 # Per bank write bursts -system.physmem.perBankRdBursts::7 13917 # Per bank write bursts -system.physmem.perBankRdBursts::8 13612 # Per bank write bursts -system.physmem.perBankRdBursts::9 13371 # Per bank write bursts -system.physmem.perBankRdBursts::10 12787 # Per bank write bursts -system.physmem.perBankRdBursts::11 11726 # Per bank write bursts -system.physmem.perBankRdBursts::12 13349 # Per bank write bursts -system.physmem.perBankRdBursts::13 14174 # Per bank write bursts -system.physmem.perBankRdBursts::14 13344 # Per bank write bursts -system.physmem.perBankRdBursts::15 12704 # Per bank write bursts -system.physmem.perBankWrBursts::0 9692 # Per bank write bursts -system.physmem.perBankWrBursts::1 9790 # Per bank write bursts -system.physmem.perBankWrBursts::2 10299 # Per bank write bursts -system.physmem.perBankWrBursts::3 9942 # Per bank write bursts -system.physmem.perBankWrBursts::4 9060 # Per bank write bursts -system.physmem.perBankWrBursts::5 9040 # Per bank write bursts -system.physmem.perBankWrBursts::6 9465 # Per bank write bursts -system.physmem.perBankWrBursts::7 9428 # Per bank write bursts +system.physmem.perBankRdBursts::2 14389 # Per bank write bursts +system.physmem.perBankRdBursts::3 14286 # Per bank write bursts +system.physmem.perBankRdBursts::4 15951 # Per bank write bursts +system.physmem.perBankRdBursts::5 13008 # Per bank write bursts +system.physmem.perBankRdBursts::6 13922 # Per bank write bursts +system.physmem.perBankRdBursts::7 13905 # Per bank write bursts +system.physmem.perBankRdBursts::8 13614 # Per bank write bursts +system.physmem.perBankRdBursts::9 13369 # Per bank write bursts +system.physmem.perBankRdBursts::10 12796 # Per bank write bursts +system.physmem.perBankRdBursts::11 11719 # Per bank write bursts +system.physmem.perBankRdBursts::12 13344 # Per bank write bursts +system.physmem.perBankRdBursts::13 14168 # Per bank write bursts +system.physmem.perBankRdBursts::14 13355 # Per bank write bursts +system.physmem.perBankRdBursts::15 12708 # Per bank write bursts +system.physmem.perBankWrBursts::0 9678 # Per bank write bursts +system.physmem.perBankWrBursts::1 9778 # Per bank write bursts +system.physmem.perBankWrBursts::2 10288 # Per bank write bursts +system.physmem.perBankWrBursts::3 9945 # Per bank write bursts +system.physmem.perBankWrBursts::4 9066 # Per bank write bursts +system.physmem.perBankWrBursts::5 9050 # Per bank write bursts +system.physmem.perBankWrBursts::6 9464 # Per bank write bursts +system.physmem.perBankWrBursts::7 9420 # Per bank write bursts system.physmem.perBankWrBursts::8 9418 # Per bank write bursts -system.physmem.perBankWrBursts::9 9301 # Per bank write bursts -system.physmem.perBankWrBursts::10 9150 # Per bank write bursts -system.physmem.perBankWrBursts::11 8663 # Per bank write bursts -system.physmem.perBankWrBursts::12 9463 # Per bank write bursts -system.physmem.perBankWrBursts::13 9594 # Per bank write bursts -system.physmem.perBankWrBursts::14 9165 # Per bank write bursts -system.physmem.perBankWrBursts::15 8718 # Per bank write bursts +system.physmem.perBankWrBursts::9 9295 # Per bank write bursts +system.physmem.perBankWrBursts::10 9149 # Per bank write bursts +system.physmem.perBankWrBursts::11 8660 # Per bank write bursts +system.physmem.perBankWrBursts::12 9452 # Per bank write bursts +system.physmem.perBankWrBursts::13 9588 # Per bank write bursts +system.physmem.perBankWrBursts::14 9180 # Per bank write bursts +system.physmem.perBankWrBursts::15 8731 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 2824339295000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2824364779500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 214462 # Read request sizes (log2) +system.physmem.readPktSize::6 214476 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149698 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 53523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 76682 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 11067 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2474 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 1103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 481 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149661 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 53531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 76693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 20729 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 11073 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9725 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -191,117 +191,113 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6932 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2958 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10781 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 11406 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 9525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 183 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 13 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92801 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 253.842782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.815283 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 308.388546 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46919 50.56% 50.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18870 20.33% 70.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6768 7.29% 78.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3705 3.99% 82.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3168 3.41% 85.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2103 2.27% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1242 1.34% 89.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1089 1.17% 90.37% # Bytes accessed per row activation +system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 14 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 253.712882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.703009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.429657 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46968 50.59% 50.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18903 20.36% 70.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6762 7.28% 78.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3669 3.95% 82.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3165 3.41% 85.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2101 2.26% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1261 1.36% 89.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1081 1.16% 90.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92801 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7531 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.931483 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 528.461754 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7530 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::total 92847 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.938645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 528.498472 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7529 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7531 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7531 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.942637 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.618581 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.035986 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6139 81.52% 81.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 568 7.54% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 91 1.21% 90.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 228 3.03% 93.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 184 2.44% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 18 0.24% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 26 0.35% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.15% 96.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 33 0.44% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.07% 96.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.13% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 156 2.07% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 9 0.12% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.05% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.17% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.05% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.01% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 4 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.08% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7531 # Writes before turning the bus around for reads -system.physmem.totQLat 8907181250 # Total ticks spent queuing -system.physmem.totMemAccLat 12992581250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1089440000 # Total ticks spent in databus transfers -system.physmem.avgQLat 40879.63 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7530 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7530 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.941833 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.646034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.689402 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6119 81.26% 81.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 568 7.54% 88.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 1.21% 90.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 218 2.90% 92.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 217 2.88% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 12 0.16% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 20 0.27% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 25 0.33% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 26 0.35% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.08% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.07% 97.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 2.08% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.09% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 8 0.11% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.05% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 13 0.17% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 6 0.08% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7530 # Writes before turning the bus around for reads +system.physmem.totQLat 8946488000 # Total ticks spent queuing +system.physmem.totMemAccLat 13032263000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1089540000 # Total ticks spent in databus transfers +system.physmem.avgQLat 41056.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 59806.26 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s @@ -310,37 +306,37 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.07 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing -system.physmem.readRowHits 185267 # Number of row buffer hits during reads -system.physmem.writeRowHits 90008 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes -system.physmem.avgGap 7586884.90 # Average gap between requests -system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states -system.physmem.memoryStateTime::REF 94310840000 # Time in different power states +system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.08 # Average write queue length when enqueuing +system.physmem.readRowHits 185273 # Number of row buffer hits during reads +system.physmem.writeRowHits 89950 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.02 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.89 # Row buffer hit rate for writes +system.physmem.avgGap 7587422.14 # Average gap between requests +system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2697372741500 # Time in different power states +system.physmem.memoryStateTime::REF 94311620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states +system.physmem.memoryStateTime::ACT 32676864750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.432189 # Core power per rank (mW) -system.physmem.averagePower::1 669.368701 # Core power per rank (mW) +system.physmem.actEnergy::0 364906080 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 337017240 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 199105500 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 183888375 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 880113000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 819569400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 496944720 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 476105040 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184473528720 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184473528720 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 78935898240 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 78466357035 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625374711500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1625786589750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1890725207760 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1890543055560 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.434632 # Core power per rank (mW) +system.physmem.averagePower::1 669.370138 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory @@ -359,770 +355,22 @@ system.realview.nvmem.bw_inst_read::total 113 # I system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 237823 # Transaction distribution -system.membus.trans_dist::ReadResp 237823 # Transaction distribution -system.membus.trans_dist::WriteReq 30977 # Transaction distribution -system.membus.trans_dist::WriteResp 30977 # Transaction distribution -system.membus.trans_dist::Writeback 113474 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution -system.membus.trans_dist::ReadExReq 31194 # Transaction distribution -system.membus.trans_dist::ReadExResp 14874 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122973 # Total snoops (count) -system.membus.snoop_fanout::samples 500866 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 500866 # Request fanout histogram -system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 153419 # number of replacements -system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use -system.l2c.tags.total_refs 521049 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.021568 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.032724 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599342 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6602520 # Number of tag accesses -system.l2c.tags.data_accesses 6602520 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits -system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits -system.l2c.Writeback_hits::total 252802 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 182592 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 97 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 55 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 44326 # number of demand (read+write) hits -system.l2c.demand_hits::total 299572 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits -system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits -system.l2c.overall_hits::cpu0.data 42648 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 182592 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 97 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 55 # number of overall hits -system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits -system.l2c.overall_hits::cpu1.data 12782 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 44326 # number of overall hits -system.l2c.overall_hits::total 299572 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 3733 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164277 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 479 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21024 # number of ReadReq misses -system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 3733 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 164277 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 479 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses -system.l2c.demand_misses::total 214569 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses -system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses -system.l2c.overall_misses::cpu0.data 16404 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 479 # number of overall misses -system.l2c.overall_misses::cpu1.data 8598 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses -system.l2c.overall_misses::total 214569 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 768250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 150000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 47537750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 122331750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 22797831231 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 6376742 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2877882 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9254624 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1147452 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1135953 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2283405 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 711214419 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 562948982 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1274163401 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2727250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 613750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 350075996 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1472784163 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 768250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 150000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 47537750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 685280732 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 24071994632 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2727250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 613750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 350075996 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1472784163 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 768250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 150000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 47537750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 685280732 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2522463904 # number of overall miss cycles -system.l2c.overall_miss_latency::total 24071994632 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 316 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 130 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 16292 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 47653 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 346869 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 107 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 57 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 4588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12936 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65350 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 494298 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 252802 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 252802 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 20556 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3555 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 24111 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 933 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1376 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2309 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 11399 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 8444 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 19843 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 316 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 130 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 16292 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 59052 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 346869 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 107 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 57 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 4588 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 21380 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65350 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 514141 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 316 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 130 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 16292 # 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miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.181458 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.473600 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.093458 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.035088 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.104403 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.106911 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.321714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.403799 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430580 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795499 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.484385 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.802787 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291335 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31016 # Transaction distribution -system.iobus.trans_dist::ReadResp 31016 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 24028098 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits +system.cpu0.branchPred.lookups 24027931 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15718166 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 977317 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14657289 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 10772949 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 73.498919 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3877670 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 32392 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1146,25 +394,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17721911 # DTB read hits -system.cpu0.dtb.read_misses 56434 # DTB read misses -system.cpu0.dtb.write_hits 14647364 # DTB write hits -system.cpu0.dtb.write_misses 8710 # DTB write misses +system.cpu0.dtb.read_hits 17722563 # DTB read hits +system.cpu0.dtb.read_misses 56347 # DTB read misses +system.cpu0.dtb.write_hits 14648246 # DTB write hits +system.cpu0.dtb.write_misses 8736 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3529 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 316 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2360 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17778345 # DTB read accesses -system.cpu0.dtb.write_accesses 14656074 # DTB write accesses +system.cpu0.dtb.perms_faults 858 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17778910 # DTB read accesses +system.cpu0.dtb.write_accesses 14656982 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32369275 # DTB hits -system.cpu0.dtb.misses 65144 # DTB misses -system.cpu0.dtb.accesses 32434419 # DTB accesses +system.cpu0.dtb.hits 32370809 # DTB hits +system.cpu0.dtb.misses 65083 # DTB misses +system.cpu0.dtb.accesses 32435892 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1186,8 +434,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 37749203 # ITB inst hits -system.cpu0.itb.inst_misses 10291 # ITB inst misses +system.cpu0.itb.inst_hits 37749898 # ITB inst hits +system.cpu0.itb.inst_misses 10270 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1196,143 +444,143 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses -system.cpu0.itb.hits 37749203 # DTB hits -system.cpu0.itb.misses 10291 # DTB misses -system.cpu0.itb.accesses 37759494 # DTB accesses -system.cpu0.numCycles 126930318 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 37760168 # ITB inst accesses +system.cpu0.itb.hits 37749898 # DTB hits +system.cpu0.itb.misses 10270 # DTB misses +system.cpu0.itb.accesses 37760168 # DTB accesses +system.cpu0.numCycles 126937172 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 18140410 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112713647 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 24027931 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14650619 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 104775763 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2822832 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 131776 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 38634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 364177 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 430173 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 37568 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37750515 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 265085 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3932 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 125329917 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.084963 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.263075 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 62773644 50.09% 50.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21461872 17.12% 67.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8766803 6.99% 74.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32327598 25.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups +system.cpu0.fetch.rateDist::total 125329917 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.189290 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.887948 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19211260 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58677383 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41416135 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4957927 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1067212 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3055574 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 348409 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110727822 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3998029 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1067212 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 24961632 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12004838 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 36556596 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40485229 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10254410 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105647594 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1060765 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1435224 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 161199 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 61281 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6055537 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109729609 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 482383818 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120922156 # Number of integer rename lookups system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle +system.cpu0.rename.CommittedMaps 98138163 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11591443 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1228785 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1087461 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12318010 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18735902 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16202980 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1699572 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2289990 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102687216 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1694558 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100671408 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 483936 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9020941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 22487287 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 122833 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 125329917 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.803251 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.034851 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 69186063 55.20% 55.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23179586 18.49% 73.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22515563 17.97% 91.66% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9334163 7.45% 99.11% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1114503 0.89% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 39 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 125329917 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9379139 40.75% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5583986 24.26% 65.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8051096 34.98% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66410061 65.97% 65.97% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93146 0.09% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued @@ -1356,101 +604,101 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.06% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8111 0.01% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18430824 18.31% 84.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15726990 15.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued -system.cpu0.iq.rate 0.793096 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads +system.cpu0.iq.FU_type_0::total 100671408 # Type of FU issued +system.cpu0.iq.rate 0.793081 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23014301 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228608 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 350139117 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 113410576 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98583429 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 31853 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 123662855 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 20581 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365420 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2006460 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2583 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19225 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1022371 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 106487 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 336614 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1067212 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1617559 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 190582 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104556500 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18735902 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16202980 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876211 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 27258 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 139659 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19225 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 291750 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 400567 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 692317 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99574081 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17974103 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1032379 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 174730 # number of nop insts executed -system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16843179 # Number of branches executed -system.cpu0.iew.exec_stores 15534759 # Number of stores executed -system.cpu0.iew.exec_rate 0.784450 # Inst execution rate -system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 51320532 # num instructions producing a value -system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value +system.cpu0.iew.exec_nop 174726 # number of nop insts executed +system.cpu0.iew.exec_refs 33509859 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16843488 # Number of branches executed +system.cpu0.iew.exec_stores 15535756 # Number of stores executed +system.cpu0.iew.exec_rate 0.784436 # Inst execution rate +system.cpu0.iew.wb_sent 99043344 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98593152 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51321674 # num instructions producing a value +system.cpu0.iew.wb_consumers 84801576 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.776708 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605197 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 8525747 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1571725 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 633113 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 123576047 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.768210 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.481297 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 79251877 64.13% 64.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24711108 20.00% 84.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8248464 6.67% 90.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3214478 2.60% 93.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3439388 2.78% 96.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1513562 1.22% 97.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1143910 0.93% 98.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 534023 0.43% 98.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1519237 1.23% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78899754 # Number of instructions committed -system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 123576047 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 78902307 # Number of instructions committed +system.cpu0.commit.committedOps 94932349 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31908645 # Number of memory references committed -system.cpu0.commit.loads 16728770 # Number of loads committed -system.cpu0.commit.membars 647107 # Number of memory barriers committed -system.cpu0.commit.branches 16205360 # Number of branches committed +system.cpu0.commit.refs 31910051 # Number of memory references committed +system.cpu0.commit.loads 16729442 # Number of loads committed +system.cpu0.commit.membars 647161 # Number of memory barriers committed +system.cpu0.commit.branches 16205593 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1929507 # Number of function calls committed. +system.cpu0.commit.int_insts 81881586 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1929479 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 62923469 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 90718 0.10% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction @@ -1474,508 +722,650 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8111 0.01% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16729442 17.62% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15180609 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 94932349 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1519237 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 221323955 # The number of ROB reads -system.cpu0.rob.rob_writes 208662740 # The number of ROB writes -system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 78777703 # Number of Instructions Simulated -system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads -system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes +system.cpu0.rob.rob_reads 221333052 # The number of ROB reads +system.cpu0.rob.rob_writes 208669303 # The number of ROB writes +system.cpu0.timesIdled 109478 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1607255 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5521794529 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78780256 # Number of Instructions Simulated +system.cpu0.committedOps 94810298 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.611282 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.611282 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.620624 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.620624 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110616528 # number of integer regfile reads +system.cpu0.int_regfile_writes 59738270 # number of integer regfile writes system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes -system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads -system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes -system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes -system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 1263367 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks. +system.cpu0.cc_regfile_reads 350776322 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41073406 # number of cc regfile writes +system.cpu0.misc_regfile_reads 245816593 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224552 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 712837 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.082878 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28842463 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 713349 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.432471 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082878 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 63484078 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63484078 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15589241 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15589241 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12071944 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12071944 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310964 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 310964 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363200 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363200 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360654 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 360654 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27661185 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27661185 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27972149 # number of overall hits +system.cpu0.dcache.overall_hits::total 27972149 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 638343 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 638343 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1832165 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1832165 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146120 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 146120 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20612 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20612 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2470508 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2470508 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2616628 # number of overall misses +system.cpu0.dcache.overall_misses::total 2616628 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8099233830 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8099233830 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24956974532 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24956974532 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395327755 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 395327755 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453888287 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 453888287 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 344500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 344500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 33056208362 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 33056208362 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 33056208362 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 33056208362 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16227584 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16227584 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904109 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13904109 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457084 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 457084 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388176 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388176 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381266 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381266 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30131693 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30131693 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30588777 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30588777 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039337 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039337 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131771 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.131771 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319679 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319679 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054062 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054062 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081990 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.081990 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085542 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.085542 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13380.328403 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13380.328403 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12633.132552 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12633.132552 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1355 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3366874 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 191323 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.357143 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 17.597853 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 513073 # number of writebacks +system.cpu0.dcache.writebacks::total 513073 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 248142 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 248142 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519584 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1519584 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1767726 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767726 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1767726 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390201 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 390201 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312581 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312581 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101511 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101511 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6555 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6555 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20612 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20612 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 702782 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 702782 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 804293 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 804293 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170777489 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170777489 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4999843092 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4999843092 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1415062493 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1415062493 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97847997 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97847997 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411963713 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411963713 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 324500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 324500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9170620581 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9170620581 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10585683074 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10585683074 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217063246 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217063246 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187063995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187063995 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404127241 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404127241 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022481 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022481 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222084 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222084 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016887 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016887 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054062 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054062 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023324 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023324 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026294 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026294 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10688.792415 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10688.792415 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15995.351899 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15995.351899 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13939.991656 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13939.991656 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14927.230664 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19986.595818 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19986.595818 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13049.025987 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13049.025987 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13161.476072 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13161.476072 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1263629 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.774279 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36446507 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1264141 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.831046 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774279 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999559 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 131 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 132 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 76757150 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 76757150 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36446077 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36446077 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36446077 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36446077 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36446077 # number of overall hits -system.cpu0.icache.overall_hits::total 36446077 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1300540 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1300540 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1300540 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1300540 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1300540 # number of overall misses -system.cpu0.icache.overall_misses::total 1300540 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11011983856 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11011983856 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11011983856 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11011983856 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11011983856 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11011983856 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37746617 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37746617 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37746617 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37746617 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37746617 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37746617 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034454 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034454 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034454 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034454 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034454 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034454 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8467.239651 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8467.239651 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8467.239651 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8467.239651 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8467.239651 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 724812 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 76758780 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76758780 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36446507 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36446507 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36446507 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36446507 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36446507 # number of overall hits +system.cpu0.icache.overall_hits::total 36446507 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1300794 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1300794 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1300794 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1300794 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1300794 # number of overall misses +system.cpu0.icache.overall_misses::total 1300794 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11016728605 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 11016728605 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11016728605 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 11016728605 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11016728605 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 11016728605 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37747301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37747301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37747301 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37747301 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37747301 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37747301 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034461 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034461 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034461 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034461 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034461 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034461 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8469.233872 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8469.233872 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8469.233872 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8469.233872 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8469.233872 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 724171 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 84 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 96016 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 96135 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.548867 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.532855 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 42 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36623 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 36623 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 36623 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 36623 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 36623 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 36623 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1263917 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1263917 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1263917 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1263917 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1263917 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1263917 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8916921322 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8916921322 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8916921322 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8916921322 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8916921322 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8916921322 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 36615 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 36615 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 36615 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 36615 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 36615 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 36615 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1264179 # 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number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244130748 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 244130748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033484 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033484 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033484 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033484 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.989625 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.989625 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.989625 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033491 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.033491 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033491 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.033491 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7054.494505 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7054.494505 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7054.494505 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11566475 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 526266 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10413579 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118534 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 11567606 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 525705 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 10416149 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 118627 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25521 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 482570 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 881997 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 25546 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 481574 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 882370 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 397205 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16210.584505 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2245016 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 413453 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.429918 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2809067534500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4582.280464 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 7.704235 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.810288 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 954.063900 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1415.763715 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9248.961904 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.279680 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000470 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000110 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.058231 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086411 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.564512 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989416 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8114 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8126 # Occupied blocks per task id +system.cpu0.l2cache.tags.replacements 396542 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16205.769061 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2244815 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 412792 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.438126 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2809084521500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4618.987809 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 8.979975 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 2.443926 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 942.112111 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1410.719068 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9222.526172 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.281921 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000548 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000149 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.057502 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.086103 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.562898 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989122 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8075 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 8170 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 46 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 255 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3376 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 3995 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 442 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 500 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3733 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3570 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 262 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.495239 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.495972 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 43582923 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 43582923 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54301 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12378 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242064 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 407333 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1716076 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 512970 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 512970 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15323 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 15323 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2128 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2128 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216744 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 216744 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54301 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12378 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1242064 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 624077 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1932820 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54301 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12378 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1242064 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 624077 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1932820 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 556 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 204 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21825 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 90809 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 113394 # number of ReadReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 189 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 3306 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 4046 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 488 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 491 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3813 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3549 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 254 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.492859 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.498657 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 43582688 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 43582688 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 54105 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12184 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1242379 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 407374 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1716042 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 513072 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 513072 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 15340 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 15340 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2133 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2133 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 216716 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 216716 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 54105 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12184 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1242379 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 624090 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1932758 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 54105 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12184 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1242379 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 624090 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1932758 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 529 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 208 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 21771 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 90784 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 113292 # number of ReadReq misses system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27941 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27958 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27958 # number of UpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18479 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 18479 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 52711 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 52711 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 556 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 204 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 21825 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 143520 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 166105 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 556 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 204 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 21825 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 143520 # number of overall misses -system.cpu0.l2cache.overall_misses::total 166105 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 14566249 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 5056249 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 811526688 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2694555362 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 3525704548 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 501364439 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 501364439 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 362083288 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 362083288 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 361000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 361000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2596231534 # 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average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1985,208 +1375,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 712829 # number of replacements -system.cpu0.dcache.tags.tagsinuse 493.082766 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28841671 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 713341 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082766 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits -system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses -system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks -system.cpu0.dcache.writebacks::total 512971 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 33910931 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits +system.cpu0.toL2Bus.trans_dist::ReadReq 2021884 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1920690 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 513073 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 646583 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 80962 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43193 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 104964 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291894 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 281156 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534332 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360691 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28712 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120464 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 5044199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953568 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86204446 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49568 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 167426118 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1040274 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3610797 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.254659 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.435670 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 2691274 74.53% 74.53% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 919523 25.47% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3610797 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1890423984 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117333499 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 1901305348 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1220101128 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 16329482 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 65866183 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.branchPred.lookups 33911271 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11563003 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 305102 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18755199 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 14959397 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 79.761334 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12490268 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7230 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2210,25 +1459,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10163466 # DTB read hits -system.cpu1.dtb.read_misses 18799 # DTB read misses -system.cpu1.dtb.write_hits 6542146 # DTB write hits -system.cpu1.dtb.write_misses 2834 # DTB write misses +system.cpu1.dtb.read_hits 10163694 # DTB read hits +system.cpu1.dtb.read_misses 18763 # DTB read misses +system.cpu1.dtb.write_hits 6542250 # DTB write hits +system.cpu1.dtb.write_misses 2833 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10182265 # DTB read accesses -system.cpu1.dtb.write_accesses 6544980 # DTB write accesses +system.cpu1.dtb.perms_faults 411 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10182457 # DTB read accesses +system.cpu1.dtb.write_accesses 6545083 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16705612 # DTB hits -system.cpu1.dtb.misses 21633 # DTB misses -system.cpu1.dtb.accesses 16727245 # DTB accesses +system.cpu1.dtb.hits 16705944 # DTB hits +system.cpu1.dtb.misses 21596 # DTB misses +system.cpu1.dtb.accesses 16727540 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -2250,8 +1499,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 43642051 # ITB inst hits -system.cpu1.itb.inst_misses 6989 # ITB inst misses +system.cpu1.itb.inst_hits 43642438 # ITB inst hits +system.cpu1.itb.inst_misses 7000 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -2260,98 +1509,98 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1205 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 538 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses -system.cpu1.itb.hits 43642051 # DTB hits -system.cpu1.itb.misses 6989 # DTB misses -system.cpu1.itb.accesses 43649040 # DTB accesses -system.cpu1.numCycles 104614253 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 43649438 # ITB inst accesses +system.cpu1.itb.hits 43642438 # DTB hits +system.cpu1.itb.misses 7000 # DTB misses +system.cpu1.itb.accesses 43649438 # DTB accesses +system.cpu1.numCycles 104622324 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9983715 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 109168018 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33911271 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27449665 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 91793931 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3775602 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78298 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 31640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 200637 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 294928 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 7575 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43641835 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 116209 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2258 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104278525 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.296897 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339782 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 47329971 45.39% 45.39% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 14035379 13.46% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7536372 7.23% 66.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35376803 33.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 104278525 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.324130 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.043449 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13017622 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 61671390 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26724772 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1111637 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1753104 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 754173 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 68061604 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1168958 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1753104 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17450100 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2254257 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 56981217 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23380222 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2459625 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 55156752 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 230613 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 263389 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 35416 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 18082 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1432431 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 55002738 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 260522478 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58680214 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed +system.cpu1.rename.CommittedMaps 52222609 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2780129 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1878054 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle +system.cpu1.rename.skidInsts 13101359 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10457131 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6914141 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 629237 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 831086 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 54264809 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 589071 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53908897 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 111732 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2292977 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5809537 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 48790 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104278525 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.516970 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.852578 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 71027306 68.11% 68.11% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16528003 15.85% 83.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13076309 12.54% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3359364 3.22% 99.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 287531 0.28% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -2359,162 +1608,162 @@ system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104278525 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2925381 45.12% 45.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1673591 25.81% 70.94% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1884116 29.06% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36727260 68.13% 68.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46535 0.09% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10380151 19.25% 87.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6751543 12.52% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued -system.cpu1.iq.rate 0.515306 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads +system.cpu1.iq.FU_type_0::total 53908897 # Type of FU issued +system.cpu1.iq.rate 0.515271 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6483765 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.120273 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 218686026 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 57154966 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51920427 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5790 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 60388895 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3701 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 91393 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 490676 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10193 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 356081 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 51970 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 70495 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1753104 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 548003 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 114295 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54906042 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10457131 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6914141 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 301584 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 9824 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 96972 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10193 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 54960 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 127313 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 182273 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53638837 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10278190 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 248481 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 52155 # number of nop insts executed -system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11807834 # Number of branches executed -system.cpu1.iew.exec_stores 6687115 # Number of stores executed -system.cpu1.iew.exec_rate 0.512725 # Inst execution rate -system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25229731 # num instructions producing a value -system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value +system.cpu1.iew.exec_nop 52162 # number of nop insts executed +system.cpu1.iew.exec_refs 16965416 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11807917 # Number of branches executed +system.cpu1.iew.exec_stores 6687226 # Number of stores executed +system.cpu1.iew.exec_rate 0.512690 # Inst execution rate +system.cpu1.iew.wb_sent 53497875 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51922213 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25229776 # num instructions producing a value +system.cpu1.iew.wb_consumers 38490454 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.496282 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655481 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3658692 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 540281 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 170405 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102346479 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.498098 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.159114 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 76767559 75.01% 75.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14288132 13.96% 88.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6080244 5.94% 94.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 703970 0.69% 95.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980102 1.93% 97.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1566998 1.53% 99.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 444730 0.43% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 123732 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 391012 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 41392870 # Number of instructions committed -system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102346479 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41392684 # Number of instructions committed +system.cpu1.commit.committedOps 50978528 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16524628 # Number of memory references committed -system.cpu1.commit.loads 9966511 # Number of loads committed -system.cpu1.commit.membars 209715 # Number of memory barriers committed -system.cpu1.commit.branches 11639820 # Number of branches committed +system.cpu1.commit.refs 16524515 # Number of memory references committed +system.cpu1.commit.loads 9966455 # Number of loads committed +system.cpu1.commit.membars 209698 # Number of memory barriers committed +system.cpu1.commit.branches 11639872 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3366594 # Number of function calls committed. +system.cpu1.commit.int_insts 45828467 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3366626 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34405041 67.49% 67.49% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 45633 0.09% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction @@ -2542,503 +1791,643 @@ system.cpu1.commit.op_class_0::SimdFloatMisc 3339 0.01% 67.59% system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9966455 19.55% 87.14% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6558060 12.86% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction -system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 50978528 # Class of committed instruction +system.cpu1.commit.bw_lim_events 391012 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 136550879 # The number of ROB reads -system.cpu1.rob.rob_writes 111203214 # The number of ROB writes -system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 41360016 # Number of Instructions Simulated -system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads -system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes +system.cpu1.rob.rob_reads 136555973 # The number of ROB reads +system.cpu1.rob.rob_writes 111202855 # The number of ROB writes +system.cpu1.timesIdled 53415 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 343799 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5543567058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41359830 # Number of Instructions Simulated +system.cpu1.committedOps 50945674 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.529564 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.529564 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.395325 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.395325 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 56285102 # number of integer regfile reads +system.cpu1.int_regfile_writes 35740910 # number of integer regfile writes system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads system.cpu1.fp_regfile_writes 520 # number of floating regfile writes -system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads -system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes -system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads -system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes -system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 835314 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.icache.tags.replacements 607233 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks. +system.cpu1.cc_regfile_reads 191162273 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15560809 # number of cc regfile writes +system.cpu1.misc_regfile_reads 205875636 # number of misc regfile reads +system.cpu1.misc_regfile_writes 388862 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 191071 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.558495 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15741437 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 82.245811 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558495 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32983767 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32983767 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 9574609 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9574609 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5910607 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5910607 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49573 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49573 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79145 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79145 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15485216 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15485216 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15534789 # number of overall hits +system.cpu1.dcache.overall_hits::total 15534789 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 219415 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 219415 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 398307 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 398307 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30093 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30093 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18121 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18121 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23394 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23394 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 617722 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 617722 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 647815 # number of overall misses +system.cpu1.dcache.overall_misses::total 647815 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3455998019 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3455998019 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8728631208 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 8728631208 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363006249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 363006249 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542688316 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 542688316 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 504500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 504500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12184629227 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12184629227 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12184629227 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12184629227 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9794024 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9794024 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308914 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6308914 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79666 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79666 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97266 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97266 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94395 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94395 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16102938 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16102938 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16182604 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16182604 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022403 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022403 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063134 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.063134 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377740 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377740 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186304 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186304 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247831 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247831 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038361 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038361 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040032 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.040032 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1112453 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39616 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.648649 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 28.080902 # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 117473 # number of writebacks +system.cpu1.dcache.writebacks::total 117473 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79558 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79558 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306502 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306502 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 386060 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 386060 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 386060 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 386060 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139857 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 139857 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91805 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91805 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28628 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28628 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4934 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4934 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23394 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 231662 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 231662 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 260290 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 260290 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829354050 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829354050 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2195265722 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2195265722 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493416244 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493416244 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87143250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87143250 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494733684 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494733684 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 482500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 482500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024619772 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4024619772 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518036016 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4518036016 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298838492 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298838492 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826630495 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826630495 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125468987 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125468987 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014280 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014280 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014552 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014552 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359350 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359350 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050727 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050727 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247831 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247831 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014386 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014386 # 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average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21147.887664 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17372.809403 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17372.809403 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17357.701087 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17357.701087 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 607164 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.524787 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 43017402 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 607676 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 70.790030 # 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number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4104857215 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4104857215 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4104857215 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4104857215 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4104857215 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8190250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8190250 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8190250 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 8190250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013926 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013926 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6750.884758 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6750.884758 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6750.884758 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013924 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013924 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013924 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013924 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6754.976254 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6754.976254 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6754.976254 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6754.976254 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841881 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43251 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4640074 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42977 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 4841342 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43201 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 4639993 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 42894 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6024 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109555 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564023 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 5995 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 109259 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564002 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 85866 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15600.635673 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 846675 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 100980 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 8.384581 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 85775 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15600.933964 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 846435 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 100895 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 8.389266 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6012.739780 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.101116 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.182282 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 726.495477 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1966.711133 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.405886 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.366989 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000555 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 5997.093337 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 10.379548 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.187782 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 717.531946 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1990.637648 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6884.103702 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.366034 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000634 # 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Occupied blocks per task id system.cpu1.l2cache.tags.occ_task_id_blocks::1023 25 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5563 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 306 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8131 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1089 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5554 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 314 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 8089 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1138 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 415 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4194 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 954 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.581421 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 428 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4157 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 969 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.582336 # Percentage of cache occupancy per task id system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001526 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.339539 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 16877479 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 16877479 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16335 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7409 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601802 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 101305 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 726851 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 117435 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 117435 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2252 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 2252 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 837 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 837 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28910 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28910 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16335 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7409 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 601802 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 130215 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 755761 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16335 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7409 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 601802 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130215 # number of overall hits -system.cpu1.l2cache.overall_hits::total 755761 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 472 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5943 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 72078 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 78769 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28388 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28388 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22558 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22558 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.338989 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 16876081 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 16876081 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16270 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7392 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 601743 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 101269 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 726674 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 117472 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 117472 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2261 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2261 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 802 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 802 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28891 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 28891 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 16270 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7392 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 601743 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130160 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 755565 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16270 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7392 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 601743 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130160 # number of overall hits +system.cpu1.l2cache.overall_hits::total 755565 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 463 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 277 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 5933 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 72130 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 78803 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28401 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28401 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22590 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22590 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 2 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32913 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32913 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 472 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 5943 # 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average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16069.541397 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14701.156825 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20053.664598 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25915.436797 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -3048,218 +2437,181 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 191071 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits -system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 398300 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses -system.cpu1.dcache.overall_misses::total 647985 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks -system.cpu1.dcache.writebacks::total 117436 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 1294408 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 865128 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117472 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 157468 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84838 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41861 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 87109 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 79574 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66376 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215557 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825064 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17352 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37871 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2095844 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38892880 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25436874 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66932 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 64427362 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 834611 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1797339 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.418381 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.493294 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1045366 58.16% 58.16% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 751973 41.84% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1797339 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 659657903 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81258998 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 912908354 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 403842529 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 9825216 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 21209360 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 31016 # Transaction distribution +system.iobus.trans_dist::ReadResp 31016 # Transaction distribution +system.iobus.trans_dist::WriteReq 59408 # Transaction distribution +system.iobus.trans_dist::WriteResp 59439 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 31 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326664315 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36832361 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36453 # number of replacements -system.iocache.tags.tagsinuse 14.560234 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.560247 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36469 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 254140674000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.560234 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 14.560247 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.910015 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.910015 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328359 # Number of tag accesses -system.iocache.tags.data_accesses 328359 # Number of data accesses +system.iocache.tags.tag_accesses 328487 # Number of tag accesses +system.iocache.tags.data_accesses 328487 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 247 # number of ReadReq misses system.iocache.ReadReq_misses::total 247 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 15 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 15 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 31 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 31 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 247 # number of demand (read+write) misses system.iocache.demand_misses::total 247 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 247 # number of overall misses @@ -3272,16 +2624,16 @@ system.iocache.overall_miss_latency::realview.ide 30832377 system.iocache.overall_miss_latency::total 30832377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 247 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 247 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36239 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36239 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36255 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36255 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 247 # number of demand (read+write) accesses system.iocache.demand_accesses::total 247 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 247 # number of overall (read+write) accesses system.iocache.overall_accesses::total 247 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000414 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000414 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000855 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000855 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses @@ -3308,8 +2660,8 @@ system.iocache.overall_mshr_misses::realview.ide 247 system.iocache.overall_mshr_misses::total 247 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 17987377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 17987377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2254879547 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2254879547 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2253111299 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2253111299 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 17987377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 17987377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 17987377 # number of overall MSHR miss cycles @@ -3329,9 +2681,654 @@ system.iocache.demand_avg_mshr_miss_latency::total 72823.388664 system.iocache.overall_avg_mshr_miss_latency::realview.ide 72823.388664 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 72823.388664 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 153470 # number of replacements +system.l2c.tags.tagsinuse 64454.116988 # Cycle average of tags in use +system.l2c.tags.total_refs 519887 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 218097 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.383742 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 14115.348135 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.484821 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 2.876495 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1418.724430 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2146.622945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39266.214752 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.503287 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 292.346121 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 885.503464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6306.489787 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.215383 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.021648 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.032755 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.599155 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000084 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.004461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013512 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096229 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983492 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 44297 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 20314 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 7726 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 36160 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4599 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15358 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.675919 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.309967 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6595063 # Number of tag accesses +system.l2c.tags.data_accesses 6595063 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 12554 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 38932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 181919 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 84 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 48 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 4143 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11543 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44205 # number of ReadReq hits +system.l2c.ReadReq_hits::total 293833 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252624 # number of Writeback hits +system.l2c.Writeback_hits::total 252624 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 720 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12425 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 181 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 174 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 355 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3713 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1233 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4946 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 12554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 42645 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 181919 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 84 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 48 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 4143 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 12776 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 44205 # number of demand (read+write) hits +system.l2c.demand_hits::total 298779 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 272 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits +system.l2c.overall_hits::cpu0.inst 12554 # number of overall hits +system.l2c.overall_hits::cpu0.data 42645 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 181919 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 84 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 48 # number of overall hits +system.l2c.overall_hits::cpu1.inst 4143 # number of overall hits +system.l2c.overall_hits::cpu1.data 12776 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 44205 # number of overall hits +system.l2c.overall_hits::total 298779 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 3728 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8660 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 164285 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1392 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 21015 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199613 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8842 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2853 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1205 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1954 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 7764 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 7212 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 14976 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 34 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 3728 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 16424 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 164285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 8604 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 21015 # number of demand (read+write) misses +system.l2c.demand_misses::total 214589 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 34 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.inst 3728 # number of overall misses +system.l2c.overall_misses::cpu0.data 16424 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 164285 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 483 # number of overall misses +system.l2c.overall_misses::cpu1.data 8604 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 21015 # number of overall misses +system.l2c.overall_misses::total 214589 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2728250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 375000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 350452746 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 764076744 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 769500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 49625500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 122837500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 22837051971 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 6562735 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2836384 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 9399119 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1040457 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1019459 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2059916 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 712108661 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 561982732 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1274091393 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2728250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 375000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 350452746 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1476185405 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 769500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 49625500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 684820232 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2533288397 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 24111143364 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2728250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 375000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 350452746 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1476185405 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 19012823834 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 769500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # 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number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12935 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 65220 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 493446 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 252624 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 252624 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 20547 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3573 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24120 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 930 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1379 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2309 # 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number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 65220 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 513368 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 306 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 138 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 16282 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 59069 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 346204 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 94 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 49 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 4626 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 21380 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 65220 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 513368 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.036232 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.228965 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.181963 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.474532 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.106383 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020408 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.104410 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.107615 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.322217 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.404529 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.430330 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.798489 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.484867 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.805376 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.873822 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.846254 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.676483 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.853996 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.751732 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.111111 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.036232 # 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mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.417956 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.111111 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.036232 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.228965 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.278031 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.474524 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.106383 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.020408 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103978 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.402432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321941 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.417956 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75820.619471 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75815.373563 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 102121.617279 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10123.926487 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10123.137153 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10261.951936 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10057.006639 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10135.565507 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79341.104456 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65306.401276 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72582.405248 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81652.694742 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77484.934482 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103439.981763 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64450 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 90414.760915 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67006.597629 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 108384.157118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 100059.867975 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 237839 # Transaction distribution +system.membus.trans_dist::ReadResp 237839 # Transaction distribution +system.membus.trans_dist::WriteReq 30978 # Transaction distribution +system.membus.trans_dist::WriteResp 30978 # Transaction distribution +system.membus.trans_dist::Writeback 113437 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79519 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40695 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13753 # Transaction distribution +system.membus.trans_dist::ReadExReq 31200 # Transaction distribution +system.membus.trans_dist::ReadExResp 14872 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13742 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708866 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 830616 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 903326 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21055004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21245656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23564952 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123021 # Total snoops (count) +system.membus.snoop_fanout::samples 500917 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 500917 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 500917 # Request fanout histogram +system.membus.reqLayer0.occupancy 81243492 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 11638997 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1642210248 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 2114152611 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38560639 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 659694 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 659679 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30978 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30978 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252624 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 91840 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41050 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 132890 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 40171 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 40171 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1298541 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426600 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1725141 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40737982 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8560538 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49298520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291438 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1083643 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033661 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.180356 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1047166 96.63% 96.63% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36477 3.37% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1083643 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1586607093 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2272505602 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 846502909 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b8a9581f1..b94dfc3eb 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,78 +4,66 @@ sim_seconds 2.826844 # Nu sim_ticks 2826844351500 # Number of ticks simulated final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97337 # Simulator instruction rate (inst/s) -host_op_rate 118064 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2430592330 # Simulator tick rate (ticks/s) -host_mem_usage 558776 # Number of bytes of host memory used -host_seconds 1163.03 # Real time elapsed on the host -sim_insts 113205077 # Number of instructions simulated -sim_ops 137311743 # Number of ops (including micro ops) simulated +host_inst_rate 107954 # Simulator instruction rate (inst/s) +host_op_rate 130942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2695726613 # Simulator tick rate (ticks/s) +host_mem_usage 568304 # Number of bytes of host memory used +host_seconds 1048.64 # Real time elapsed on the host +sim_insts 113204796 # Number of instructions simulated +sim_ops 137311416 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 172165 # Number of read requests accepted system.physmem.writeReqs 131231 # Number of write requests accepted system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 10989 # Per bank write bursts @@ -87,7 +75,7 @@ system.physmem.perBankRdBursts::5 10546 # Pe system.physmem.perBankRdBursts::6 11171 # Per bank write bursts system.physmem.perBankRdBursts::7 11539 # Per bank write bursts system.physmem.perBankRdBursts::8 10356 # Per bank write bursts -system.physmem.perBankRdBursts::9 11055 # Per bank write bursts +system.physmem.perBankRdBursts::9 11056 # Per bank write bursts system.physmem.perBankRdBursts::10 10496 # Per bank write bursts system.physmem.perBankRdBursts::11 9259 # Per bank write bursts system.physmem.perBankRdBursts::12 10183 # Per bank write bursts @@ -127,8 +115,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 126850 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see @@ -174,32 +162,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see @@ -223,44 +211,44 @@ system.physmem.wrQLenPdf::60 20 # Wh system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads @@ -278,13 +266,13 @@ system.physmem.wrPerTurnAround::124-127 1 0.02% 99.91% # Wr system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads -system.physmem.totQLat 2071957750 # Total ticks spent queuing -system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads +system.physmem.totQLat 2072280000 # Total ticks spent queuing +system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s @@ -295,236 +283,63 @@ system.physmem.busUtilRead 0.03 # Da system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing -system.physmem.readRowHits 141999 # Number of row buffer hits during reads -system.physmem.writeRowHits 95218 # Number of row buffer hits during writes +system.physmem.readRowHits 142002 # Number of row buffer hits during reads +system.physmem.writeRowHits 95212 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes system.physmem.avgGap 9317341.50 # Average gap between requests -system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states +system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states system.physmem.memoryStateTime::REF 94394300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states +system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ) +system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ) system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ) system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ) system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.335912 # Core power per rank (mW) -system.physmem.averagePower::1 669.239814 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 67834 # Transaction distribution -system.membus.trans_dist::ReadResp 67833 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 90626 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution -system.membus.trans_dist::ReadExReq 135127 # Transaction distribution -system.membus.trans_dist::ReadExResp 135127 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 205 # Total snoops (count) -system.membus.snoop_fanout::samples 300222 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 300222 # Request fanout histogram -system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.336036 # Core power per rank (mW) +system.physmem.averagePower::1 669.240113 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 46964481 # Number of BP lookups -system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits +system.cpu.branchPred.lookups 46964274 # Number of BP lookups +system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -548,9 +363,9 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25471928 # DTB read hits -system.cpu.dtb.read_misses 60410 # DTB read misses -system.cpu.dtb.write_hits 19919780 # DTB write hits +system.cpu.dtb.read_hits 25471879 # DTB read hits +system.cpu.dtb.read_misses 60408 # DTB read misses +system.cpu.dtb.write_hits 19919747 # DTB write hits system.cpu.dtb.write_misses 9388 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -561,12 +376,12 @@ system.cpu.dtb.align_faults 351 # Nu system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532338 # DTB read accesses -system.cpu.dtb.write_accesses 19929168 # DTB write accesses +system.cpu.dtb.read_accesses 25532287 # DTB read accesses +system.cpu.dtb.write_accesses 19929135 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45391708 # DTB hits -system.cpu.dtb.misses 69798 # DTB misses -system.cpu.dtb.accesses 45461506 # DTB accesses +system.cpu.dtb.hits 45391626 # DTB hits +system.cpu.dtb.misses 69796 # DTB misses +system.cpu.dtb.accesses 45461422 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -588,7 +403,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 66240861 # ITB inst hits +system.cpu.itb.inst_hits 66240582 # ITB inst hits system.cpu.itb.inst_misses 11936 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -605,91 +420,91 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66252797 # ITB inst accesses -system.cpu.itb.hits 66240861 # DTB hits +system.cpu.itb.inst_accesses 66252518 # ITB inst accesses +system.cpu.itb.hits 66240582 # DTB hits system.cpu.itb.misses 11936 # DTB misses -system.cpu.itb.accesses 66252797 # DTB accesses -system.cpu.numCycles 260549216 # number of cpu cycles simulated +system.cpu.itb.accesses 66252518 # DTB accesses +system.cpu.numCycles 260548868 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full +system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -697,9 +512,9 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available @@ -728,13 +543,13 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -762,97 +577,97 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 8590 0.01% 67.07% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued +system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued system.cpu.iq.rate 0.550285 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 200927 # number of nop insts executed -system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544157 # Number of branches executed -system.cpu.iew.exec_stores 20882594 # Number of stores executed +system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed +system.cpu.iew.exec_branches 26544085 # Number of branches executed +system.cpu.iew.exec_stores 20882571 # Number of stores executed system.cpu.iew.exec_rate 0.546668 # Inst execution rate -system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301722 # num instructions producing a value -system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value +system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63301578 # num instructions producing a value +system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113359982 # Number of instructions committed -system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113359701 # Number of instructions committed +system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45531388 # Number of memory references committed -system.cpu.commit.loads 24928306 # Number of loads committed +system.cpu.commit.refs 45531319 # Number of memory references committed +system.cpu.commit.loads 24928258 # Number of loads committed system.cpu.commit.membars 814674 # Number of memory barriers committed -system.cpu.commit.branches 26060542 # Number of branches committed +system.cpu.commit.branches 26060472 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120282409 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896404 # Number of function calls committed. +system.cpu.commit.int_insts 120282111 # Number of committed integer instructions. +system.cpu.commit.function_calls 4896381 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -880,86 +695,222 @@ system.cpu.commit.op_class_0::SimdFloatMisc 8589 0.01% 66.88% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction +system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373371044 # The number of ROB reads -system.cpu.rob.rob_writes 293051212 # The number of ROB writes -system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113205077 # Number of Instructions Simulated -system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads +system.cpu.rob.rob_reads 373370450 # The number of ROB reads +system.cpu.rob.rob_writes 293050441 # The number of ROB writes +system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113204796 # Number of Instructions Simulated +system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155870959 # number of integer regfile reads -system.cpu.int_regfile_writes 88663005 # number of integer regfile writes +system.cpu.int_regfile_reads 155870535 # number of integer regfile reads +system.cpu.int_regfile_writes 88662743 # number of integer regfile writes system.cpu.fp_regfile_reads 9591 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503160195 # number of cc regfile reads -system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes -system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads +system.cpu.cc_regfile_reads 503158959 # number of cc regfile reads +system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes +system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65488 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3525412 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1894038 # number of replacements +system.cpu.dcache.tags.replacements 837744 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23329792 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38918357 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits +system.cpu.dcache.overall_hits::total 39265000 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4451395 # number of overall misses +system.cpu.dcache.overall_misses::total 4451395 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897569146 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks +system.cpu.dcache.writebacks::total 695413 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414154 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 713416 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 713416 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 832722 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 832722 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5341815166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5341815166 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883724205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883724205 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479869001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479869001 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225539371 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17225539371 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18705408372 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18705408372 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792724250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792724250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440459453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440459453 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233183703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233183703 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.137326 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.137326 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39710.100865 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39710.100865 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12403.978015 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12403.978015 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24145.154259 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24145.154259 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.968880 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.968880 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 1894031 # number of replacements system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 64256441 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1894543 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.916591 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy @@ -970,44 +921,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 170 system.cpu.icache.tags.age_task_id_blocks_1024::2 208 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68132740 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68132740 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64256715 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64256715 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64256715 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64256715 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64256715 # number of overall hits -system.cpu.icache.overall_hits::total 64256715 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981457 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981457 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981457 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981457 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981457 # number of overall misses -system.cpu.icache.overall_misses::total 1981457 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26763157130 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26763157130 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26763157130 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26763157130 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26763157130 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26763157130 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66238172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66238172 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66238172 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66238172 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66238172 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66238172 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 68132454 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68132454 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64256441 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64256441 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64256441 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64256441 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64256441 # number of overall hits +system.cpu.icache.overall_hits::total 64256441 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1981452 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1981452 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1981452 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1981452 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1981452 # number of overall misses +system.cpu.icache.overall_misses::total 1981452 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26762198879 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26762198879 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26762198879 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26762198879 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26762198879 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26762198879 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66237893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66237893 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66237893 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66237893 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66237893 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66237893 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029914 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.029914 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.029914 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.029914 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.029914 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.029914 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.806925 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13506.806925 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13506.806925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.806925 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13506.806925 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13506.357398 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13506.357398 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13506.357398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13506.357398 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13506.357398 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 1929 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 105 # number of cycles access was blocked @@ -1016,24 +967,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 18.371429 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86887 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86887 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86887 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86887 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86887 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86887 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22160408840 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22160408840 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22160408840 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22160408840 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22160408840 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22160408840 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86889 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 86889 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 86889 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 86889 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 86889 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 86889 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894563 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1894563 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1894563 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1894563 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1894563 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1894563 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22159944091 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22159944091 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22159944091 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22159944091 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22159944091 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22159944091 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles @@ -1044,28 +995,28 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.801301 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.801301 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.801301 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.801301 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11696.599211 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11696.599211 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11696.599211 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11696.599211 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 98619 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65077.788296 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3020959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 65077.788294 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3020947 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163832 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.439371 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.439298 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540904 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 49562.540884 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 10.218344 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798460 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612651 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617936 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10310.612666 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5191.617940 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.756264 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000156 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy @@ -1082,31 +1033,31 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7006 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55046 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994873 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28437367 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28437367 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53840 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 28437271 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28437271 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53838 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11660 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874571 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528036 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2468107 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695414 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695414 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1874564 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528034 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2468096 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 695413 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 695413 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 34 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 34 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 159688 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 159688 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53840 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 53838 # 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average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1334,191 +1285,157 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 837746 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits -system.cpu.dcache.overall_hits::total 39265074 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses -system.cpu.dcache.overall_misses::total 4451402 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks -system.cpu.dcache.writebacks::total 695414 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713418 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 65488 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3525400 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 30181 # Transaction distribution +system.iobus.trans_dist::ReadResp 30181 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1604,6 +1521,89 @@ system.iocache.demand_avg_mshr_miss_latency::total 68024.440909 system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 67834 # Transaction distribution +system.membus.trans_dist::ReadResp 67833 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 90626 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution +system.membus.trans_dist::ReadExReq 135127 # Transaction distribution +system.membus.trans_dist::ReadExResp 135127 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 205 # Total snoops (count) +system.membus.snoop_fanout::samples 300222 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 300222 # Request fanout histogram +system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 271261101..de918fa9c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,155 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.817969 # Number of seconds simulated -sim_ticks 2817968959500 # Number of ticks simulated -final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817967 # Number of seconds simulated +sim_ticks 2817967230500 # Number of ticks simulated +final_tick 2817967230500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 311387 # Simulator instruction rate (inst/s) -host_op_rate 378101 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6951332904 # Simulator tick rate (ticks/s) -host_mem_usage 560824 # Number of bytes of host memory used -host_seconds 405.39 # Real time elapsed on the host -sim_insts 126231916 # Number of instructions simulated -sim_ops 153276567 # Number of ops (including micro ops) simulated +host_inst_rate 295085 # Simulator instruction rate (inst/s) +host_op_rate 358305 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6587585543 # Simulator tick rate (ticks/s) +host_mem_usage 567284 # Number of bytes of host memory used +host_seconds 427.77 # Real time elapsed on the host +sim_insts 126228232 # Number of instructions simulated +sim_ops 153272049 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 652964 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4386528 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory -system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.inst 516736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4232960 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 10978952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 652964 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 516736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1300644 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5946048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281908 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 69058 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8074 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 66140 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 180519 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 92907 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133512 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1556605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 231715 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1556628 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 183167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 183372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1502132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3896054 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 231715 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 183372 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461554 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2110049 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 822698 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2938965 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2110049 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 231715 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1562844 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 92768 # Number of read requests accepted -system.physmem.writeReqs 67796 # Number of write requests accepted -system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu2.inst 183372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1502132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 823039 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6835019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 92786 # Number of read requests accepted +system.physmem.writeReqs 67811 # Number of write requests accepted +system.physmem.readBursts 92786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 67811 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5933952 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue -system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side +system.physmem.bytesWritten 4338688 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5938244 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4339784 # Total written bytes from the system interface side system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6044 # Per bank write bursts -system.physmem.perBankRdBursts::1 5813 # Per bank write bursts -system.physmem.perBankRdBursts::2 5577 # Per bank write bursts -system.physmem.perBankRdBursts::3 6085 # Per bank write bursts -system.physmem.perBankRdBursts::4 5556 # Per bank write bursts -system.physmem.perBankRdBursts::5 5466 # Per bank write bursts -system.physmem.perBankRdBursts::6 6173 # Per bank write bursts -system.physmem.perBankRdBursts::7 6793 # Per bank write bursts -system.physmem.perBankRdBursts::8 6458 # Per bank write bursts -system.physmem.perBankRdBursts::9 6393 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 2462 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 6041 # Per bank write bursts +system.physmem.perBankRdBursts::1 5815 # Per bank write bursts +system.physmem.perBankRdBursts::2 5576 # Per bank write bursts +system.physmem.perBankRdBursts::3 6089 # Per bank write bursts +system.physmem.perBankRdBursts::4 5555 # Per bank write bursts +system.physmem.perBankRdBursts::5 5469 # Per bank write bursts +system.physmem.perBankRdBursts::6 6176 # Per bank write bursts +system.physmem.perBankRdBursts::7 6795 # Per bank write bursts +system.physmem.perBankRdBursts::8 6466 # Per bank write bursts +system.physmem.perBankRdBursts::9 6395 # Per bank write bursts system.physmem.perBankRdBursts::10 5737 # Per bank write bursts -system.physmem.perBankRdBursts::11 5119 # Per bank write bursts -system.physmem.perBankRdBursts::12 5308 # Per bank write bursts +system.physmem.perBankRdBursts::11 5121 # Per bank write bursts +system.physmem.perBankRdBursts::12 5306 # Per bank write bursts system.physmem.perBankRdBursts::13 5463 # Per bank write bursts -system.physmem.perBankRdBursts::14 5329 # Per bank write bursts -system.physmem.perBankRdBursts::15 5386 # Per bank write bursts -system.physmem.perBankWrBursts::0 4258 # Per bank write bursts -system.physmem.perBankWrBursts::1 3939 # Per bank write bursts -system.physmem.perBankWrBursts::2 4228 # Per bank write bursts -system.physmem.perBankWrBursts::3 4685 # Per bank write bursts -system.physmem.perBankWrBursts::4 4137 # Per bank write bursts +system.physmem.perBankRdBursts::14 5326 # Per bank write bursts +system.physmem.perBankRdBursts::15 5388 # Per bank write bursts +system.physmem.perBankWrBursts::0 4259 # Per bank write bursts +system.physmem.perBankWrBursts::1 3941 # Per bank write bursts +system.physmem.perBankWrBursts::2 4227 # Per bank write bursts +system.physmem.perBankWrBursts::3 4690 # Per bank write bursts +system.physmem.perBankWrBursts::4 4139 # Per bank write bursts system.physmem.perBankWrBursts::5 4140 # Per bank write bursts -system.physmem.perBankWrBursts::6 4393 # Per bank write bursts -system.physmem.perBankWrBursts::7 4905 # Per bank write bursts -system.physmem.perBankWrBursts::8 4554 # Per bank write bursts -system.physmem.perBankWrBursts::9 4640 # Per bank write bursts -system.physmem.perBankWrBursts::10 4209 # Per bank write bursts -system.physmem.perBankWrBursts::11 3550 # Per bank write bursts -system.physmem.perBankWrBursts::12 4025 # Per bank write bursts +system.physmem.perBankWrBursts::6 4396 # Per bank write bursts +system.physmem.perBankWrBursts::7 4907 # Per bank write bursts +system.physmem.perBankWrBursts::8 4559 # Per bank write bursts +system.physmem.perBankWrBursts::9 4641 # Per bank write bursts +system.physmem.perBankWrBursts::10 4210 # Per bank write bursts +system.physmem.perBankWrBursts::11 3556 # Per bank write bursts +system.physmem.perBankWrBursts::12 4023 # Per bank write bursts system.physmem.perBankWrBursts::13 4273 # Per bank write bursts -system.physmem.perBankWrBursts::14 3934 # Per bank write bursts -system.physmem.perBankWrBursts::15 3898 # Per bank write bursts +system.physmem.perBankWrBursts::14 3931 # Per bank write bursts +system.physmem.perBankWrBursts::15 3900 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 8 # Number of times write queue was full causing retry -system.physmem.totGap 2816402817000 # Total gap between requests +system.physmem.totGap 2816401088000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 92767 # Read request sizes (log2) +system.physmem.readPktSize::6 92785 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67794 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 61106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 515 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67809 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 61124 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 516 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::11 49 # Wh system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1440 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3367 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3366 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4627 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4221 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3325 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see @@ -242,44 +242,44 @@ system.physmem.wrQLenPdf::60 24 # Wh system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 32876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.458450 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.413676 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.664106 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12770 38.84% 38.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7721 23.49% 62.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 2991 9.10% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1712 5.21% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1344 4.09% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 774 2.35% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 537 1.63% 84.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 552 1.68% 86.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4475 13.61% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 32876 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.482642 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 540.024143 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 3254 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 3255 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3255 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.827035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.877074 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.588559 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 2714 83.38% 83.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 41 1.26% 84.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.98% 85.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 140 4.30% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 131 4.02% 94.25% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.09% 95.55% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads @@ -297,13 +297,13 @@ system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Wr system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads -system.physmem.totQLat 1185318250 # Total ticks spent queuing -system.physmem.totMemAccLat 2923443250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12786.60 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 3255 # Writes before turning the bus around for reads +system.physmem.totQLat 1187084500 # Total ticks spent queuing +system.physmem.totMemAccLat 2925547000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 463590000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12803.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31536.60 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31553.17 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s @@ -314,35 +314,35 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing -system.physmem.readRowHits 76736 # Number of row buffer hits during reads -system.physmem.writeRowHits 50876 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes -system.physmem.avgGap 17540686.69 # Average gap between requests +system.physmem.readRowHits 76742 # Number of row buffer hits during reads +system.physmem.writeRowHits 50891 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes +system.physmem.avgGap 17537071.60 # Average gap between requests system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2704844337250 # Time in different power states -system.physmem.memoryStateTime::REF 94098160000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2704795503250 # Time in different power states +system.physmem.memoryStateTime::REF 94097900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 19026368250 # Time in different power states +system.physmem.memoryStateTime::ACT 19068171250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 70810447635 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 69981022395 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1628666801250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1629394367250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1884329288175 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1884181443990 # Total energy per rank (pJ) -system.physmem.averagePower::0 668.683537 # Core power per rank (mW) -system.physmem.averagePower::1 668.631072 # Core power per rank (mW) +system.physmem.actEnergy::0 130016880 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 118525680 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 70941750 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 64671750 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 370624800 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 352544400 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 224849520 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 214442640 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 184055492400 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 184055492400 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 70844118390 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 70005569445 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1628632585500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1629368154750 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1884328629240 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1884179401065 # Total energy per rank (pJ) +system.physmem.averagePower::0 668.685154 # Core power per rank (mW) +system.physmem.averagePower::1 668.632198 # Core power per rank (mW) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -355,675 +355,13 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 7 system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 74236 # Transaction distribution -system.membus.trans_dist::ReadResp 74235 # Transaction distribution -system.membus.trans_dist::WriteReq 27571 # Transaction distribution -system.membus.trans_dist::WriteResp 27571 # Transaction distribution -system.membus.trans_dist::Writeback 92896 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution -system.membus.trans_dist::ReadExReq 137042 # Transaction distribution -system.membus.trans_dist::ReadExResp 137042 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579191 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652018 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17102699 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19429163 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125 # Total snoops (count) -system.membus.snoop_fanout::samples 304844 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 304844 # Request fanout histogram -system.membus.reqLayer0.occupancy 40698500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 463500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 735391250 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 906935534 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 100821 # number of replacements -system.l2c.tags.tagsinuse 65118.790980 # Cycle average of tags in use -system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49797.187018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2854.503750 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966166 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3505.210474 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1537.513263 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3115 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8083 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53656 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27447983 # Number of tag accesses -system.l2c.tags.data_accesses 27447983 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2545 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 856871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 242835 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1453 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 248099 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 77823 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 27437 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6484 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 674506 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 203103 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2346863 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 692569 # number of Writeback hits -system.l2c.Writeback_hits::total 692569 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 40 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 54 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 81755 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19470 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 56351 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157576 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2545 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 856871 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 324590 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 248099 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 97293 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 27437 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6484 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 674506 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 259454 # number of demand (read+write) hits -system.l2c.demand_hits::total 2504439 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4963 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2545 # number of overall hits -system.l2c.overall_hits::cpu0.inst 856871 # number of overall hits -system.l2c.overall_hits::cpu0.data 324590 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1453 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 744 # number of overall hits -system.l2c.overall_hits::cpu1.inst 248099 # number of overall hits -system.l2c.overall_hits::cpu1.data 97293 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 27437 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 6484 # number of overall hits -system.l2c.overall_hits::cpu2.inst 674506 # number of overall hits -system.l2c.overall_hits::cpu2.data 259454 # number of overall hits -system.l2c.overall_hits::total 2504439 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9638 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6914 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2046 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2575 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 95 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 8072 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 4575 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33921 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 366 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1066 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62387 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5817198029 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943995500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1580248500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2524244000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 723617500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1233115000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1956732500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1667613000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2813363500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4480976500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.032028 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021817 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.007272 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989189 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.963834 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.516781 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420225 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525365 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.258007 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.035036 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.035036 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62166.504854 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.973994 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.793832 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2443720 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2443717 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616607 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6218457 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213301511 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51755 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30188 # Transaction distribution -system.iobus.trans_dist::ReadResp 30188 # Transaction distribution -system.iobus.trans_dist::WriteReq 59010 # Transaction distribution -system.iobus.trans_dist::WriteResp 45563 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1047,25 +385,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14476225 # DTB read hits -system.cpu0.dtb.read_misses 4878 # DTB read misses -system.cpu0.dtb.write_hits 11074159 # DTB write hits -system.cpu0.dtb.write_misses 931 # DTB write misses +system.cpu0.dtb.read_hits 14476193 # DTB read hits +system.cpu0.dtb.read_misses 4879 # DTB read misses +system.cpu0.dtb.write_hits 11073999 # DTB write hits +system.cpu0.dtb.write_misses 930 # DTB write misses system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 946 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14481103 # DTB read accesses -system.cpu0.dtb.write_accesses 11075090 # DTB write accesses +system.cpu0.dtb.read_accesses 14481072 # DTB read accesses +system.cpu0.dtb.write_accesses 11074929 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25550384 # DTB hits +system.cpu0.dtb.hits 25550192 # DTB hits system.cpu0.dtb.misses 5809 # DTB misses -system.cpu0.dtb.accesses 25556193 # DTB accesses +system.cpu0.dtb.accesses 25556001 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1087,8 +425,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 67954632 # ITB inst hits -system.cpu0.itb.inst_misses 2810 # ITB inst misses +system.cpu0.itb.inst_hits 67954476 # ITB inst hits +system.cpu0.itb.inst_misses 2811 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1104,38 +442,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67957442 # ITB inst accesses -system.cpu0.itb.hits 67954632 # DTB hits -system.cpu0.itb.misses 2810 # DTB misses -system.cpu0.itb.accesses 67957442 # DTB accesses -system.cpu0.numCycles 82556870 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67957287 # ITB inst accesses +system.cpu0.itb.hits 67954476 # DTB hits +system.cpu0.itb.misses 2811 # DTB misses +system.cpu0.itb.accesses 67957287 # DTB accesses +system.cpu0.numCycles 82556827 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66160123 # Number of instructions committed -system.cpu0.committedOps 80652277 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70891568 # Number of integer alu accesses +system.cpu0.committedInsts 66160398 # Number of instructions committed +system.cpu0.committedOps 80652664 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70891762 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses -system.cpu0.num_func_calls 7292026 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8778447 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70891568 # number of integer instructions +system.cpu0.num_func_calls 7292056 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8778747 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70891762 # number of integer instructions system.cpu0.num_fp_insts 5582 # number of float instructions -system.cpu0.num_int_register_reads 131506227 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49334420 # number of times the integer registers were written +system.cpu0.num_int_register_reads 131506051 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49334508 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245867738 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29383072 # number of times the CC registers were written -system.cpu0.num_mem_refs 26220754 # number of memory refs -system.cpu0.num_load_insts 14652166 # Number of load instructions -system.cpu0.num_store_insts 11568588 # Number of store instructions -system.cpu0.num_idle_cycles 77950731.061702 # Number of idle cycles -system.cpu0.num_busy_cycles 4606138.938298 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055794 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944206 # Percentage of idle cycles -system.cpu0.Branches 16465385 # Number of branches fetched +system.cpu0.num_cc_register_reads 245869189 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29383374 # number of times the CC registers were written +system.cpu0.num_mem_refs 26220572 # number of memory refs +system.cpu0.num_load_insts 14652138 # Number of load instructions +system.cpu0.num_store_insts 11568434 # Number of store instructions +system.cpu0.num_idle_cycles 77950738.874403 # Number of idle cycles +system.cpu0.num_busy_cycles 4606088.125597 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055793 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944207 # Percentage of idle cycles +system.cpu0.Branches 16465662 # Number of branches fetched system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55784741 67.97% 67.97% # Class of executed instruction -system.cpu0.op_class::IntMult 58719 0.07% 68.05% # Class of executed instruction +system.cpu0.op_class::IntAlu 55785323 67.97% 67.97% # Class of executed instruction +system.cpu0.op_class::IntMult 58705 0.07% 68.05% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction @@ -1163,427 +501,290 @@ system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction -system.cpu0.op_class::MemRead 14652166 17.85% 85.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 11568588 14.10% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14652138 17.85% 85.90% # Class of executed instruction +system.cpu0.op_class::MemWrite 11568434 14.10% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82070947 # Class of executed instruction +system.cpu0.op_class::total 82071333 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3056 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1798781 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.545341 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100889008 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1799292 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.071504 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.678395 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.508688 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.358258 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932966 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.042009 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024137 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999112 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 162 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104537930 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104537930 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67090158 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21677954 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 12120896 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100889008 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67090158 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21677954 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 12120896 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100889008 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67090158 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21677954 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 12120896 # number of overall hits -system.cpu0.icache.overall_hits::total 100889008 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 866515 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 250147 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 732935 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1849597 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 866515 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 250147 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 732935 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1849597 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 866515 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 250147 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 732935 # number of overall misses -system.cpu0.icache.overall_misses::total 1849597 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3389079250 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10061046680 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13450125930 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 3389079250 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 10061046680 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13450125930 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 3389079250 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 10061046680 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13450125930 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956673 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 21928101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12853831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102738605 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67956673 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 21928101 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12853831 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102738605 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67956673 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 21928101 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12853831 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102738605 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012751 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011408 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057021 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.018003 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012751 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011408 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057021 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.018003 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012751 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011408 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057021 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.018003 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.350570 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.065401 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7271.922440 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7271.922440 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.350570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.065401 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7271.922440 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5408 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 341 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.859238 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50271 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50271 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 50271 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50271 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 50271 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50271 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250147 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682664 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 932811 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 250147 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 682664 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 932811 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 250147 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 682664 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 932811 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888042750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8209155812 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11097198562 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888042750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8209155812 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11097198562 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888042750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8209155812 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11097198562 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009079 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009079 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011408 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053110 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009079 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.513401 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11545.382315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.177557 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.513401 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 833731 # number of replacements +system.cpu0.dcache.tags.replacements 833736 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 47004235 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834243 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.343577 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 47002068 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 834248 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.340642 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853552 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.631337 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.511911 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853503 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.630840 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.512458 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948933 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032483 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018578 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032482 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018579 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 195 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198572858 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198572858 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13788624 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4405133 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8515109 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26708866 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10680775 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3155078 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5164116 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18999969 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190600 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60611 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130493 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381704 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235254 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80501 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 135396 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451151 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236603 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 83020 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140074 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459697 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24469399 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7560211 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13679225 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45708835 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24659999 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7620822 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13809718 # number of overall hits -system.cpu0.dcache.overall_hits::total 46090539 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 190274 # number of ReadReq misses +system.cpu0.dcache.tags.tag_accesses 198562219 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 198562219 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 13788602 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 4405053 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 8513889 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 26707544 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10680609 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3155163 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 5163362 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18999134 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190594 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60628 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130484 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 381706 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235265 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80498 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 135390 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 451153 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236615 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 83018 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140051 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459684 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 24469211 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 7560216 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 13677251 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 45706678 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 24659805 # 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number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132211248 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178650248 # number of LoadLockedReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 335697 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 93353 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1845576 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2274626 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 390719 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 113491 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1911114 # number of overall misses +system.cpu0.dcache.overall_misses::total 2415324 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905367250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5265516623 # 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number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805301500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022754369 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7574271637 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9597026006 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275974119 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8232846143 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10508820262 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1018414500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1694074000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712488500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777507500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1315307000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092814500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1795922000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3009381000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805303000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018218 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008073 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010646 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017900 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008074 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010645 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017902 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244576 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224044 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121872 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244496 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224072 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121879 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019870 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019906 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009047 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # 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average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36480.166618 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45391.659659 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43423.987715 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.063291 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15002.220335 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14326.207587 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012183 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018085 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007794 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014609 # 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average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.736450 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7270.895923 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5362 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 334 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.053892 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50167 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50167 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 50167 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50167 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 50167 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50167 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250233 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682211 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 932444 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 250233 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 682211 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 932444 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 250233 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 682211 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 932444 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888910000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8203668345 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11092578345 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888910000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8203668345 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11092578345 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888910000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8203668345 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11092578345 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009076 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009076 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009076 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.240788 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.240788 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.240788 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1617,25 +955,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4634872 # DTB read hits -system.cpu1.dtb.read_misses 1584 # DTB read misses -system.cpu1.dtb.write_hits 3276619 # DTB write hits -system.cpu1.dtb.write_misses 228 # DTB write misses +system.cpu1.dtb.read_hits 4634797 # DTB read hits +system.cpu1.dtb.read_misses 1583 # DTB read misses +system.cpu1.dtb.write_hits 3276695 # DTB write hits +system.cpu1.dtb.write_misses 231 # DTB write misses system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 105 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1208 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1209 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 225 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 51 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4636456 # DTB read accesses -system.cpu1.dtb.write_accesses 3276847 # DTB write accesses +system.cpu1.dtb.perms_faults 52 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4636380 # DTB read accesses +system.cpu1.dtb.write_accesses 3276926 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7911491 # DTB hits -system.cpu1.dtb.misses 1812 # DTB misses -system.cpu1.dtb.accesses 7913303 # DTB accesses +system.cpu1.dtb.hits 7911492 # DTB hits +system.cpu1.dtb.misses 1814 # DTB misses +system.cpu1.dtb.accesses 7913306 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1657,55 +995,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 21928101 # ITB inst hits -system.cpu1.itb.inst_misses 848 # ITB inst misses +system.cpu1.itb.inst_hits 21927829 # ITB inst hits +system.cpu1.itb.inst_misses 850 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 104 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 105 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 700 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 702 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21928949 # ITB inst accesses -system.cpu1.itb.hits 21928101 # DTB hits -system.cpu1.itb.misses 848 # DTB misses -system.cpu1.itb.accesses 21928949 # DTB accesses -system.cpu1.numCycles 158012618 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 21928679 # ITB inst accesses +system.cpu1.itb.hits 21927829 # DTB hits +system.cpu1.itb.misses 850 # DTB misses +system.cpu1.itb.accesses 21928679 # DTB accesses +system.cpu1.numCycles 158012697 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21219739 # Number of instructions committed -system.cpu1.committedOps 25418009 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22602370 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1626 # Number of float alu accesses -system.cpu1.num_func_calls 2405283 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2700826 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22602370 # number of integer instructions -system.cpu1.num_fp_insts 1626 # number of float instructions -system.cpu1.num_int_register_reads 41665136 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15857680 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1178 # number of times the floating registers were read +system.cpu1.committedInsts 21219424 # Number of instructions committed +system.cpu1.committedOps 25417661 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22602393 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1642 # Number of float alu accesses +system.cpu1.num_func_calls 2405355 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2700524 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22602393 # number of integer instructions +system.cpu1.num_fp_insts 1642 # number of float instructions +system.cpu1.num_int_register_reads 41665364 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15857744 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1194 # number of times the floating registers were read system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92378683 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written -system.cpu1.num_mem_refs 8126078 # number of memory refs -system.cpu1.num_load_insts 4682102 # Number of load instructions -system.cpu1.num_store_insts 3443976 # Number of store instructions -system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles -system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles -system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles -system.cpu1.Branches 5257577 # Number of branches fetched +system.cpu1.num_cc_register_reads 92377254 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9370530 # number of times the CC registers were written +system.cpu1.num_mem_refs 8126107 # number of memory refs +system.cpu1.num_load_insts 4682037 # Number of load instructions +system.cpu1.num_store_insts 3444070 # Number of store instructions +system.cpu1.num_idle_cycles 151526887.882406 # Number of idle cycles +system.cpu1.num_busy_cycles 6485809.117594 # Number of busy cycles +system.cpu1.not_idle_fraction 0.041046 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.958954 # Percentage of idle cycles +system.cpu1.Branches 5257446 # Number of branches fetched system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17988055 68.83% 68.83% # Class of executed instruction -system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction +system.cpu1.op_class::IntAlu 17987711 68.83% 68.83% # Class of executed instruction +system.cpu1.op_class::IntMult 19014 0.07% 68.90% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction @@ -1729,26 +1067,26 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1154 0.00% 68.91% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction -system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction -system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 4682037 17.92% 86.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 3444070 13.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26134331 # Class of executed instruction +system.cpu1.op_class::total 26134022 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17411527 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits +system.cpu2.branchPred.lookups 17408373 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9463731 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 400017 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10864152 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8142904 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 74.952044 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4071247 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21277 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1772,25 +1110,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9691496 # DTB read hits -system.cpu2.dtb.read_misses 37543 # DTB read misses -system.cpu2.dtb.write_hits 7160478 # DTB write hits -system.cpu2.dtb.write_misses 5658 # DTB write misses +system.cpu2.dtb.read_hits 9689518 # DTB read hits +system.cpu2.dtb.read_misses 37575 # DTB read misses +system.cpu2.dtb.write_hits 7159699 # DTB write hits +system.cpu2.dtb.write_misses 5670 # DTB write misses system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch +system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 968 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9729039 # DTB read accesses -system.cpu2.dtb.write_accesses 7166136 # DTB write accesses +system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9727093 # DTB read accesses +system.cpu2.dtb.write_accesses 7165369 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16851974 # DTB hits -system.cpu2.dtb.misses 43201 # DTB misses -system.cpu2.dtb.accesses 16895175 # DTB accesses +system.cpu2.dtb.hits 16849217 # DTB hits +system.cpu2.dtb.misses 43245 # DTB misses +system.cpu2.dtb.accesses 16892462 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1812,158 +1150,158 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 12855360 # ITB inst hits -system.cpu2.itb.inst_misses 6344 # ITB inst misses +system.cpu2.itb.inst_hits 12852348 # ITB inst hits +system.cpu2.itb.inst_misses 6327 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1763 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1147 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses -system.cpu2.itb.hits 12855360 # DTB hits -system.cpu2.itb.misses 6344 # DTB misses -system.cpu2.itb.accesses 12861704 # DTB accesses -system.cpu2.numCycles 69831868 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12858675 # ITB inst accesses +system.cpu2.itb.hits 12852348 # DTB hits +system.cpu2.itb.misses 6327 # DTB misses +system.cpu2.itb.accesses 12858675 # DTB accesses +system.cpu2.numCycles 69828422 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26736882 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69116574 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17408373 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12214151 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39634943 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2070237 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 91943 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 273 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 329325 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 101475 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12850788 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 270289 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2773 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67931271 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.222867 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.347613 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49354668 72.65% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2396025 3.53% 76.18% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1561758 2.30% 78.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4875455 7.18% 85.66% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1102436 1.62% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 704861 1.04% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3873045 5.70% 94.02% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 751493 1.11% 95.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3311530 4.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67931271 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249302 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.989806 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18645308 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36894831 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10382963 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1080745 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 927203 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1311099 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 109436 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59339671 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 354865 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 927203 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19270411 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4356096 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27085706 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10825258 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 5466363 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56871138 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2407 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 944494 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 157128 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 3862497 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58808456 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 261172418 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63777133 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4183 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48694532 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10113908 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 954202 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 890607 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6274956 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10279229 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7930666 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1385426 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1931872 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54639620 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 672070 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 52007794 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68359 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7304876 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18433205 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 69298 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67931271 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.765594 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.467899 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47467453 69.88% 69.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6844404 10.08% 79.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5089744 7.49% 87.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4188713 6.17% 93.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1618102 2.38% 95.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1074322 1.58% 97.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1126267 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 361985 0.53% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 160281 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67931271 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 78971 9.77% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.77% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 376071 46.54% 56.32% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 352950 43.68% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34454774 66.25% 66.25% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39220 0.08% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued @@ -1976,10 +1314,10 @@ system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Ty system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued @@ -1987,101 +1325,101 @@ system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Ty system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2865 0.01% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9972711 19.18% 85.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7538110 14.49% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued -system.cpu2.iq.rate 0.744849 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 52007794 # Type of FU issued +system.cpu2.iq.rate 0.744794 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 807993 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015536 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172813810 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62649489 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50408450 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9401 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4928 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4143 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52810613 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5066 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 267388 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1612297 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1915 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38614 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 794248 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 131416 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 121570 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 927203 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3248790 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 940039 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55419045 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 93730 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10279229 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7930666 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 359745 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 34744 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 896292 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38614 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 184316 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 163000 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 347316 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51571999 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9796032 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 392652 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 107408 # number of nop insts executed -system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9489180 # Number of branches executed -system.cpu2.iew.exec_stores 7465028 # Number of stores executed -system.cpu2.iew.exec_rate 0.738611 # Inst execution rate -system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26486298 # num instructions producing a value -system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value +system.cpu2.iew.exec_nop 107355 # number of nop insts executed +system.cpu2.iew.exec_refs 17260233 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9488063 # Number of branches executed +system.cpu2.iew.exec_stores 7464201 # Number of stores executed +system.cpu2.iew.exec_rate 0.738553 # Inst execution rate +system.cpu2.iew.wb_sent 51114762 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50412593 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26484469 # num instructions producing a value +system.cpu2.iew.wb_consumers 46017701 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.721949 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575528 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8145270 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 602772 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 292077 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66207003 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713906 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.618708 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48127722 72.69% 72.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 8087932 12.22% 84.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3990373 6.03% 90.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1725495 2.61% 93.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 876020 1.32% 94.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 623327 0.94% 95.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1254839 1.90% 97.70% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 299711 0.45% 98.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1221584 1.85% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38915831 # Number of instructions committed -system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66207003 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38912247 # Number of instructions committed +system.cpu2.commit.committedOps 47265561 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15804910 # Number of memory references committed -system.cpu2.commit.loads 8667813 # Number of loads committed -system.cpu2.commit.membars 226604 # Number of memory barriers committed -system.cpu2.commit.branches 8912074 # Number of branches committed -system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1635579 # Number of function calls committed. +system.cpu2.commit.refs 15803350 # Number of memory references committed +system.cpu2.commit.loads 8666932 # Number of loads committed +system.cpu2.commit.membars 226535 # Number of memory barriers committed +system.cpu2.commit.branches 8911403 # Number of branches committed +system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41364475 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1635441 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31421440 66.48% 66.48% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 37906 0.08% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction @@ -2105,45 +1443,137 @@ system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2865 0.01% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8666932 18.34% 84.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7136418 15.10% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47265561 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1221584 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 113043839 # The number of ROB reads -system.cpu2.rob.rob_writes 112575250 # The number of ROB writes -system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.rob.rob_reads 113032454 # The number of ROB reads +system.cpu2.rob.rob_writes 112549271 # The number of ROB writes +system.cpu2.timesIdled 280538 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1897151 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38852054 # Number of Instructions Simulated -system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads -system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes -system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads -system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes +system.cpu2.committedInsts 38848410 # Number of Instructions Simulated +system.cpu2.committedOps 47201724 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.797459 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.797459 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.556341 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.556341 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56460891 # number of integer regfile reads +system.cpu2.int_regfile_writes 31949429 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15783 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes +system.cpu2.cc_regfile_reads 182431289 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19284860 # number of cc regfile writes +system.cpu2.misc_regfile_reads 124219174 # number of misc regfile reads +system.cpu2.misc_regfile_writes 483131 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30188 # Transaction distribution +system.iobus.trans_dist::ReadResp 30188 # Transaction distribution +system.iobus.trans_dist::WriteReq 59010 # Transaction distribution +system.iobus.trans_dist::WriteResp 45563 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.992769 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.992769 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062048 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062048 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2224,6 +1654,576 @@ system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 100842 # number of replacements +system.l2c.tags.tagsinuse 65118.786988 # Cycle average of tags in use +system.l2c.tags.total_refs 2894514 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166082 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.428222 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 49797.172619 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5291.834831 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2854.505423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1121.422857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 949.240769 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966175 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3505.217048 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1537.518652 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3121 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8094 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53637 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27443398 # Number of tag accesses +system.l2c.tags.data_accesses 27443398 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4964 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2546 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 856761 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 242820 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1454 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 747 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 248185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 77821 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 27355 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 6441 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 674046 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 203120 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2346260 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 692581 # number of Writeback hits +system.l2c.Writeback_hits::total 692581 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 41 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 55 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 81743 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19467 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 56360 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 157570 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4964 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2546 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 856761 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 324563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 1454 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 747 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 248185 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 97288 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 27355 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 6441 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 674046 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 259480 # number of demand (read+write) hits +system.l2c.demand_hits::total 2503830 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4964 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2546 # number of overall hits +system.l2c.overall_hits::cpu0.inst 856761 # number of overall hits +system.l2c.overall_hits::cpu0.data 324563 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 1454 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 747 # number of overall hits +system.l2c.overall_hits::cpu1.inst 248185 # number of overall hits +system.l2c.overall_hits::cpu1.data 97288 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 27355 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 6441 # number of overall hits +system.l2c.overall_hits::cpu2.inst 674046 # number of overall hits +system.l2c.overall_hits::cpu2.data 259480 # number of overall hits +system.l2c.overall_hits::total 2503830 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 9639 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6915 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2046 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2575 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 95 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 8081 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 4586 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33943 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1284 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 369 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1064 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 62393 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14107 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 62372 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 138872 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 9639 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69308 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2046 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16682 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 95 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 8081 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 66958 # number of demand (read+write) misses +system.l2c.demand_misses::total 172815 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 9639 # number of overall misses +system.l2c.overall_misses::cpu0.data 69308 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2046 # number of overall misses +system.l2c.overall_misses::cpu1.data 16682 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 95 # number of overall misses +system.l2c.overall_misses::cpu2.inst 8081 # number of overall misses +system.l2c.overall_misses::cpu2.data 66958 # number of overall misses +system.l2c.overall_misses::total 172815 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 148469000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 192657500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7339250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 615860500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 368031996 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1332432746 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 326986 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 349985 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 994427496 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 4664036226 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 5658463722 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 148469000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1187084996 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 7339250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 615860500 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021867 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.007283 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989276 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.962896 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.516955 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420176 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525318 # 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mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.204982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.035049 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62308.543689 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67932.187583 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64142.652936 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.169173 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.838102 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57700.290919 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62432.939043 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 61559.974346 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 74258 # Transaction distribution +system.membus.trans_dist::ReadResp 74257 # Transaction distribution +system.membus.trans_dist::WriteReq 27571 # Transaction distribution +system.membus.trans_dist::WriteResp 27571 # Transaction distribution +system.membus.trans_dist::Writeback 92907 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4549 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4552 # Transaction distribution +system.membus.trans_dist::ReadExReq 137040 # Transaction distribution +system.membus.trans_dist::ReadExResp 137040 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 579244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 652071 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16941564 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17104683 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19431147 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125 # Total snoops (count) +system.membus.snoop_fanout::samples 304876 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 304876 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 304876 # Request fanout histogram +system.membus.reqLayer0.occupancy 40704500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 459000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 735607750 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 907107038 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 2443155 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2443152 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 692581 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296442 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296442 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615657 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484160 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29265 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88229 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6217311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115156920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97909811 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49244 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155812 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213271787 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51771 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3431211 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102567 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3394727 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3431211 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2367804213 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 4198919632 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2015022352 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 11862428 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 39524153 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index c06812645..caba31176 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,153 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.804327 # Number of seconds simulated -sim_ticks 2804326619500 # Number of ticks simulated -final_tick 2804326619500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804324 # Number of seconds simulated +sim_ticks 2804324203000 # Number of ticks simulated +final_tick 2804324203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119116 # Simulator instruction rate (inst/s) -host_op_rate 144575 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2855979889 # Simulator tick rate (ticks/s) -host_mem_usage 563896 # Number of bytes of host memory used -host_seconds 981.91 # Real time elapsed on the host -sim_insts 116961561 # Number of instructions simulated -sim_ops 141959724 # Number of ops (including micro ops) simulated +host_inst_rate 115850 # Simulator instruction rate (inst/s) +host_op_rate 140611 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2777671240 # Simulator tick rate (ticks/s) +host_mem_usage 569464 # Number of bytes of host memory used +host_seconds 1009.60 # Real time elapsed on the host +sim_insts 116961789 # Number of instructions simulated +sim_ops 141959973 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4288 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 740544 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5179680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 739200 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5181280 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 636864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4641732 # Number of bytes read from this memory -system.physmem.bytes_read::total 11208612 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 740544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 636864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1377408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6113984 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 637568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4639684 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 11207460 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 739200 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 637568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1376768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6111936 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8449844 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 8447796 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 67 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11571 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 81451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 11550 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 81476 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 69 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9951 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 72528 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175654 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 95531 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9962 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 72496 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 175636 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 95499 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136136 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 136104 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1529 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 264072 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1847032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 263593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1847604 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 227101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1655204 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3996900 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 264072 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 227101 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491172 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2180197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 227352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1654475 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3996492 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 263593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 227352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 490945 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2179468 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3013145 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2180197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 827042 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 826700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3012418 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2179468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1529 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 264072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1853278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 263593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1853850 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 227101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1655207 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7010045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175655 # Number of read requests accepted -system.physmem.writeReqs 136136 # Number of write requests accepted -system.physmem.readBursts 175655 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 136136 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11233984 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7936 # Total number of bytes read from write queue -system.physmem.bytesWritten 8463616 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11208676 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8449844 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 124 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3872 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4658 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11108 # Per bank write bursts -system.physmem.perBankRdBursts::1 11142 # Per bank write bursts -system.physmem.perBankRdBursts::2 11724 # Per bank write bursts -system.physmem.perBankRdBursts::3 11223 # Per bank write bursts -system.physmem.perBankRdBursts::4 11369 # Per bank write bursts -system.physmem.perBankRdBursts::5 11393 # Per bank write bursts -system.physmem.perBankRdBursts::6 11953 # Per bank write bursts -system.physmem.perBankRdBursts::7 11818 # Per bank write bursts -system.physmem.perBankRdBursts::8 10217 # Per bank write bursts -system.physmem.perBankRdBursts::9 10450 # Per bank write bursts -system.physmem.perBankRdBursts::10 10599 # Per bank write bursts -system.physmem.perBankRdBursts::11 9773 # Per bank write bursts -system.physmem.perBankRdBursts::12 10412 # Per bank write bursts -system.physmem.perBankRdBursts::13 11414 # Per bank write bursts -system.physmem.perBankRdBursts::14 10639 # Per bank write bursts -system.physmem.perBankRdBursts::15 10297 # Per bank write bursts -system.physmem.perBankWrBursts::0 8312 # Per bank write bursts -system.physmem.perBankWrBursts::1 8440 # Per bank write bursts -system.physmem.perBankWrBursts::2 9043 # Per bank write bursts -system.physmem.perBankWrBursts::3 8548 # Per bank write bursts -system.physmem.perBankWrBursts::4 8346 # Per bank write bursts -system.physmem.perBankWrBursts::5 8542 # Per bank write bursts +system.physmem.bw_total::cpu1.inst 227352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1654478 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 827043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7008910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175637 # Number of read requests accepted +system.physmem.writeReqs 136104 # Number of write requests accepted +system.physmem.readBursts 175637 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 136104 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11232064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8704 # Total number of bytes read from write queue +system.physmem.bytesWritten 8461376 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11207524 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8447796 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 136 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3870 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4652 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11117 # Per bank write bursts +system.physmem.perBankRdBursts::1 11147 # Per bank write bursts +system.physmem.perBankRdBursts::2 11719 # Per bank write bursts +system.physmem.perBankRdBursts::3 11225 # Per bank write bursts +system.physmem.perBankRdBursts::4 11363 # Per bank write bursts +system.physmem.perBankRdBursts::5 11390 # Per bank write bursts +system.physmem.perBankRdBursts::6 11955 # Per bank write bursts +system.physmem.perBankRdBursts::7 11820 # Per bank write bursts +system.physmem.perBankRdBursts::8 10213 # Per bank write bursts +system.physmem.perBankRdBursts::9 10442 # Per bank write bursts +system.physmem.perBankRdBursts::10 10593 # Per bank write bursts +system.physmem.perBankRdBursts::11 9765 # Per bank write bursts +system.physmem.perBankRdBursts::12 10406 # Per bank write bursts +system.physmem.perBankRdBursts::13 11413 # Per bank write bursts +system.physmem.perBankRdBursts::14 10638 # Per bank write bursts +system.physmem.perBankRdBursts::15 10295 # Per bank write bursts +system.physmem.perBankWrBursts::0 8316 # Per bank write bursts +system.physmem.perBankWrBursts::1 8444 # Per bank write bursts +system.physmem.perBankWrBursts::2 9040 # Per bank write bursts +system.physmem.perBankWrBursts::3 8545 # Per bank write bursts +system.physmem.perBankWrBursts::4 8340 # Per bank write bursts +system.physmem.perBankWrBursts::5 8537 # Per bank write bursts system.physmem.perBankWrBursts::6 8974 # Per bank write bursts system.physmem.perBankWrBursts::7 8818 # Per bank write bursts -system.physmem.perBankWrBursts::8 7763 # Per bank write bursts -system.physmem.perBankWrBursts::9 7812 # Per bank write bursts -system.physmem.perBankWrBursts::10 7942 # Per bank write bursts -system.physmem.perBankWrBursts::11 7398 # Per bank write bursts -system.physmem.perBankWrBursts::12 7887 # Per bank write bursts -system.physmem.perBankWrBursts::13 8744 # Per bank write bursts -system.physmem.perBankWrBursts::14 8046 # Per bank write bursts -system.physmem.perBankWrBursts::15 7629 # Per bank write bursts +system.physmem.perBankWrBursts::8 7762 # Per bank write bursts +system.physmem.perBankWrBursts::9 7809 # Per bank write bursts +system.physmem.perBankWrBursts::10 7936 # Per bank write bursts +system.physmem.perBankWrBursts::11 7396 # Per bank write bursts +system.physmem.perBankWrBursts::12 7882 # Per bank write bursts +system.physmem.perBankWrBursts::13 8742 # Per bank write bursts +system.physmem.perBankWrBursts::14 8045 # Per bank write bursts +system.physmem.perBankWrBursts::15 7623 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 14 # Number of times write queue was full causing retry -system.physmem.totGap 2804326433500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2804324017000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175100 # Read request sizes (log2) +system.physmem.readPktSize::6 175082 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 131755 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8506 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1503 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131723 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 104376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1509 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -176,135 +164,130 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 98 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7535 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8757 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7217 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 303.665033 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.572173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.227913 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24436 37.67% 37.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15780 24.33% 62.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6593 10.16% 72.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3751 5.78% 77.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2794 4.31% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1520 2.34% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1090 1.68% 86.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1132 1.75% 88.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7770 11.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6698 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.205584 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 477.627003 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6695 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2577 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 267 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64783 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 303.989874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.723316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 327.460023 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24407 37.68% 37.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15776 24.35% 62.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6538 10.09% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3738 5.77% 77.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2814 4.34% 82.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1507 2.33% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1107 1.71% 86.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1104 1.70% 87.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7792 12.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64783 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.165350 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 477.307058 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6698 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6698 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.743804 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.225845 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.527754 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 13 0.19% 0.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 9 0.13% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 4 0.06% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 9 0.13% 0.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5778 86.26% 86.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 106 1.58% 88.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.64% 89.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 223 3.33% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 204 3.05% 95.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.25% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.33% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.22% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 32 0.48% 96.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.15% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.12% 96.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 5 0.07% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 143 2.13% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.09% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 6 0.09% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.15% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 5 0.07% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 4 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.04% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6698 # Writes before turning the bus around for reads -system.physmem.totQLat 2733630250 # Total ticks spent queuing -system.physmem.totMemAccLat 6024836500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877655000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15573.49 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.712092 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.230918 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.181787 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.10% 0.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 4 0.06% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 9 0.13% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5755 85.81% 86.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 109 1.63% 87.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 46 0.69% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 238 3.55% 92.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 224 3.34% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 22 0.33% 95.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 23 0.34% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.10% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 31 0.46% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.03% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 8 0.12% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 152 2.27% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 5 0.07% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 12 0.18% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 13 0.19% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.06% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads +system.physmem.totQLat 2727699250 # Total ticks spent queuing +system.physmem.totMemAccLat 6018343000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 877505000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15542.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 34323.49 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 34292.36 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s @@ -314,710 +297,64 @@ system.physmem.busUtil 0.05 # Da system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.73 # Average write queue length when enqueuing -system.physmem.readRowHits 145110 # Number of row buffer hits during reads -system.physmem.writeRowHits 97798 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.94 # Row buffer hit rate for writes -system.physmem.avgGap 8994250.74 # Average gap between requests -system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2678438745750 # Time in different power states +system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing +system.physmem.readRowHits 145124 # Number of row buffer hits during reads +system.physmem.writeRowHits 97802 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.69 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes +system.physmem.avgGap 8995685.58 # Average gap between requests +system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2678459999250 # Time in different power states system.physmem.memoryStateTime::REF 93642380000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 32245482750 # Time in different power states +system.physmem.memoryStateTime::ACT 32221812750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 259141680 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 231245280 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 141396750 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 126175500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 715486200 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 653647800 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 447269040 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 409672080 # Energy for write commands per rank (pJ) +system.physmem.actEnergy::0 259096320 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 230663160 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 141372000 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 125857875 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 715533000 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 653367000 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 447210720 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 409503600 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 77839312860 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 76923425745 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1614311544000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1615114953750 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1876878645810 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1876623615435 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.281339 # Core power per rank (mW) -system.physmem.averagePower::1 669.190397 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 68041 # Transaction distribution -system.membus.trans_dist::ReadResp 68040 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 95531 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4632 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4658 # Transaction distribution -system.membus.trans_dist::ReadExReq 138441 # Transaction distribution -system.membus.trans_dist::ReadExResp 138441 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464888 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572528 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 645240 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17339160 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17503137 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19822433 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 234 # Total snoops (count) -system.membus.snoop_fanout::samples 311110 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 311110 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 311110 # Request fanout histogram -system.membus.reqLayer0.occupancy 81518499 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1434327498 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1730433594 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38513958 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 104268 # number of replacements -system.l2c.tags.tagsinuse 65131.307742 # Cycle average of tags in use -system.l2c.tags.total_refs 3106944 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169509 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.329080 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48616.163532 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.311212 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5571.967356 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2874.440506 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.347195 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4984.192297 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2991.885408 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.085021 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.076053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045653 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 63 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 332 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3243 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8995 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52594 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000961 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994537 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 29221748 # Number of tag accesses -system.l2c.tags.data_accesses 29221748 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 36519 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 8855 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 959908 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 271615 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36602 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7424 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 964068 # 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number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 18 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 26 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 74760 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 65571 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140331 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 68 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 10921 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 81838 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 69 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9951 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 73476 # 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number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2427344000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5414949500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2228650000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1873529499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4102179499 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 35706500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5180549000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4300873499 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9517128999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025390 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028494 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013894 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.972305 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.960719 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.966173 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.275862 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.360000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.329114 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.490043 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.454348 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.472691 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061065 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001859 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000113 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011249 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.189737 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001882 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010216 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.174221 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061065 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67978.735801 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69671.409614 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 65496.450282 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10002.153965 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10047.084546 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10025.799052 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64313.786664 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65477.355813 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64857.475462 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66955.882353 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63391.081403 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64630.760564 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62714.827656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65928.577917 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64987.909326 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actBackEnergy::0 77871628440 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 76866307470 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1614283197000 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1615165057500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1876882532760 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1876615251885 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.282725 # Core power per rank (mW) +system.physmem.averagePower::1 669.187414 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 640 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2655325 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2655239 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 703423 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36238 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2838 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 79 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2917 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296877 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296877 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891298 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533043 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42437 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6635850 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124513216 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99808865 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65120 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 293032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224680233 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 69343 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3662983 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009961 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099307 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3626496 99.00% 99.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36487 1.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3662983 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4670881246 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8762800197 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3909656420 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26229350 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96621860 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30210 # Transaction distribution -system.iobus.trans_dist::ReadResp 30210 # Transaction distribution -system.iobus.trans_dist::WriteReq 59030 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 8 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326627644 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36841042 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 27349422 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14250256 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 549515 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 17066610 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12886962 # Number of BTB hits +system.cpu0.branchPred.lookups 27347795 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14227638 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 549324 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 17049849 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12874628 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.509794 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6758521 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30298 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.511683 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6769747 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 30174 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1041,25 +378,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14278108 # DTB read hits -system.cpu0.dtb.read_misses 49273 # DTB read misses -system.cpu0.dtb.write_hits 10337716 # DTB write hits -system.cpu0.dtb.write_misses 7471 # DTB write misses +system.cpu0.dtb.read_hits 14276180 # DTB read hits +system.cpu0.dtb.read_misses 49315 # DTB read misses +system.cpu0.dtb.write_hits 10339289 # DTB write hits +system.cpu0.dtb.write_misses 7532 # DTB write misses system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3414 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 948 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3434 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1022 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1284 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 559 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14327381 # DTB read accesses -system.cpu0.dtb.write_accesses 10345187 # DTB write accesses +system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14325495 # DTB read accesses +system.cpu0.dtb.write_accesses 10346821 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24615824 # DTB hits -system.cpu0.dtb.misses 56744 # DTB misses -system.cpu0.dtb.accesses 24672568 # DTB accesses +system.cpu0.dtb.hits 24615469 # DTB hits +system.cpu0.dtb.misses 56847 # DTB misses +system.cpu0.dtb.accesses 24672316 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1081,158 +418,158 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 20514368 # ITB inst hits -system.cpu0.itb.inst_misses 8789 # ITB inst misses +system.cpu0.itb.inst_hits 20541420 # ITB inst hits +system.cpu0.itb.inst_misses 9178 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2304 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2315 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1446 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20523157 # ITB inst accesses -system.cpu0.itb.hits 20514368 # DTB hits -system.cpu0.itb.misses 8789 # DTB misses -system.cpu0.itb.accesses 20523157 # DTB accesses -system.cpu0.numCycles 107867607 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20550598 # ITB inst accesses +system.cpu0.itb.hits 20541420 # DTB hits +system.cpu0.itb.misses 9178 # DTB misses +system.cpu0.itb.accesses 20550598 # DTB accesses +system.cpu0.numCycles 107861472 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40554205 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 105662539 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 27349422 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19645483 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 61985766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3245353 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 132544 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 7121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 440 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 622961 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 144030 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 269 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20513111 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 376873 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3476 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105069976 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.208080 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.305286 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 40570754 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 105629295 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 27347795 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19644375 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61853082 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3245677 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 138610 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 7043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 456 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 740654 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 142990 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20540168 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 376427 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3608 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 105076575 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.207830 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.305137 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 75961238 72.30% 72.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3886755 3.70% 76.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2398368 2.28% 78.28% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8188948 7.79% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1668369 1.59% 87.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1057044 1.01% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6240721 5.94% 94.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1068642 1.02% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4599891 4.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75967097 72.30% 72.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3896975 3.71% 76.01% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2393426 2.28% 78.28% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8192788 7.80% 86.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1656267 1.58% 87.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1057275 1.01% 88.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6246218 5.94% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1068490 1.02% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4598039 4.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105069976 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 105076575 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.979558 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28001193 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58307153 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15793340 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1494905 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1473111 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1905219 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 151604 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 87425197 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 489487 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1473111 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 28862922 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7852670 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44540857 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16413726 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5926414 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 83594857 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2128 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1233256 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 243031 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3726809 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86235184 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 384969647 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93192750 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5702 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72438827 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13796341 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1547496 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1453336 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8912532 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15029778 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11466004 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1956224 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2714292 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80433839 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1054374 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77107853 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91926 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10053145 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 24795847 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 115089 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105069976 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.733871 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.427930 # Number of insts issued each cycle +system.cpu0.fetch.rate 0.979305 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27994294 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 58319975 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15794569 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1493949 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1473513 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1905038 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 151409 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 87407414 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 488746 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1473513 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28854924 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 7818064 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 44554229 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16415102 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 5960455 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 83576128 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2157 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1234281 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 240945 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3763501 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 86207701 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 384903383 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 93172990 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5580 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 72433922 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13773763 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1548068 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1453832 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8905153 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 15025647 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11465948 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1963626 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2709003 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 80419048 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1054429 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 77104069 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 91403 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10038631 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24749704 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 115176 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 105076575 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.733789 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.427784 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74334112 70.75% 70.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10187384 9.70% 80.44% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7871575 7.49% 87.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6574512 6.26% 94.19% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2321319 2.21% 96.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1487177 1.42% 97.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1563743 1.49% 99.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 491068 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 239086 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 74341292 70.75% 70.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10185363 9.69% 80.44% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7872852 7.49% 87.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6575632 6.26% 94.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2323435 2.21% 96.40% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1484934 1.41% 97.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1562160 1.49% 99.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 492520 0.47% 99.77% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 238387 0.23% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105069976 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 105076575 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 112390 9.87% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 534190 46.93% 56.80% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 491756 43.20% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112989 9.93% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 531745 46.73% 56.66% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 493078 43.34% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51438430 66.71% 66.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57761 0.07% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 51434902 66.71% 66.71% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57707 0.07% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued @@ -1256,101 +593,101 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4468 0.01% 66.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4464 0.01% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14680887 19.04% 85.83% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10924099 14.17% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14679264 19.04% 85.83% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10925524 14.17% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77107853 # Type of FU issued -system.cpu0.iq.rate 0.714838 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1138339 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014763 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 260503389 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 91586031 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 74660496 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12558 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6677 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78237256 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6737 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 345558 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 77104069 # Type of FU issued +system.cpu0.iq.rate 0.714843 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1137816 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014757 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 260501553 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 91556805 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 74656153 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12379 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6497 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5408 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 78233021 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6665 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 345101 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2209259 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2417 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 52309 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1126312 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2206473 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 52158 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1126677 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 207644 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 205299 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 207379 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 207346 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1473111 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5378277 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2195764 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 81614966 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 130944 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15029778 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11466004 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 550994 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44204 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2139047 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 52309 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 254090 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 219689 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 473779 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76503781 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14445333 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 547436 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1473513 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5378839 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2159961 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 81600157 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 131532 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 15025647 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11465948 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 550941 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 44144 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2103435 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 52158 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 253800 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 219690 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 473490 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 76500063 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14443562 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 547275 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126753 # number of nop insts executed -system.cpu0.iew.exec_refs 25264055 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14430009 # Number of branches executed -system.cpu0.iew.exec_stores 10818722 # Number of stores executed -system.cpu0.iew.exec_rate 0.709238 # Inst execution rate -system.cpu0.iew.wb_sent 75844960 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 74665993 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 39001048 # num instructions producing a value -system.cpu0.iew.wb_consumers 67639279 # num instructions consuming a value +system.cpu0.iew.exec_nop 126680 # number of nop insts executed +system.cpu0.iew.exec_refs 25263883 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14430618 # Number of branches executed +system.cpu0.iew.exec_stores 10820321 # Number of stores executed +system.cpu0.iew.exec_rate 0.709244 # Inst execution rate +system.cpu0.iew.wb_sent 75840899 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 74661561 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38996929 # num instructions producing a value +system.cpu0.iew.wb_consumers 67640251 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.692200 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.576604 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.692199 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.576534 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11323076 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 939285 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 399913 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102514186 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.684864 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.574695 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11313930 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 939253 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 399962 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102521377 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.684763 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.574745 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75189561 73.35% 73.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12242134 11.94% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6265138 6.11% 91.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2642512 2.58% 93.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1297372 1.27% 95.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 836423 0.82% 96.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1889134 1.84% 97.90% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 413413 0.40% 98.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1738499 1.70% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 75202228 73.35% 73.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12236708 11.94% 85.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6265954 6.11% 91.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2644751 2.58% 93.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1294412 1.26% 95.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 834681 0.81% 96.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1890114 1.84% 97.90% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 411979 0.40% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1740550 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102514186 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 57883100 # Number of instructions committed -system.cpu0.commit.committedOps 70208236 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102521377 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 57875239 # Number of instructions committed +system.cpu0.commit.committedOps 70202859 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23160211 # Number of memory references committed -system.cpu0.commit.loads 12820519 # Number of loads committed -system.cpu0.commit.membars 372556 # Number of memory barriers committed -system.cpu0.commit.branches 13646736 # Number of branches committed -system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61470931 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2656843 # Number of function calls committed. +system.cpu0.commit.refs 23158445 # Number of memory references committed +system.cpu0.commit.loads 12819174 # Number of loads committed +system.cpu0.commit.membars 372518 # Number of memory barriers committed +system.cpu0.commit.branches 13646130 # Number of branches committed +system.cpu0.commit.fp_insts 5383 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 61467682 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2657552 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 46987548 66.93% 66.93% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 56009 0.08% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 46983958 66.93% 66.93% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55992 0.08% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction @@ -1374,427 +711,292 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4468 0.01% 67.01% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4464 0.01% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12820519 18.26% 85.27% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10339692 14.73% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12819174 18.26% 85.27% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10339271 14.73% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70208236 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1738499 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 70202859 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1740550 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 169645518 # The number of ROB reads -system.cpu0.rob.rob_writes 165622521 # The number of ROB writes -system.cpu0.timesIdled 399235 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2797631 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2442097834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 57811199 # Number of Instructions Simulated -system.cpu0.committedOps 70136335 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.865860 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.865860 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.535946 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.535946 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83226933 # number of integer regfile reads -system.cpu0.int_regfile_writes 47573974 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16207 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13000 # number of floating regfile writes -system.cpu0.cc_regfile_reads 270444340 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28203341 # number of cc regfile writes -system.cpu0.misc_regfile_reads 191459430 # number of misc regfile reads -system.cpu0.misc_regfile_writes 720407 # number of misc regfile writes -system.cpu0.icache.tags.replacements 1944509 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.580286 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39079293 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1945021 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.091965 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.092053 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.488233 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541195 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.457985 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43109447 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43109447 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19472177 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19607116 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39079293 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19472177 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19607116 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39079293 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19472177 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19607116 # number of overall hits -system.cpu0.icache.overall_hits::total 39079293 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1040272 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1044765 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2085037 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1040272 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1044765 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2085037 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1040272 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1044765 # number of overall misses -system.cpu0.icache.overall_misses::total 2085037 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14234369484 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14196293397 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28430662881 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14234369484 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14196293397 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28430662881 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14234369484 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14196293397 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28430662881 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 20512449 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20651881 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41164330 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 20512449 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20651881 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41164330 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20512449 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20651881 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41164330 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050714 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050589 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050652 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050714 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050589 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050652 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050714 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050589 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050652 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13683.315021 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13588.025438 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13635.567561 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13635.567561 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13635.567561 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8976 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 503 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.844930 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69341 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70578 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 139919 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 69341 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 70578 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 139919 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 69341 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 70578 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 139919 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970931 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974187 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1945118 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 970931 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 974187 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1945118 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 970931 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 974187 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1945118 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11624310724 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11588912543 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 23213223267 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11624310724 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11588912543 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 23213223267 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11624310724 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11588912543 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 23213223267 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49455500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49455500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047253 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047334 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047172 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047253 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11934.095138 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11972.334516 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11895.983567 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11934.095138 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 852532 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984435 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42510984 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853044 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.834456 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 169629703 # The number of ROB reads +system.cpu0.rob.rob_writes 165592947 # The number of ROB writes +system.cpu0.timesIdled 399199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2784897 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2442098527 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 57803575 # Number of Instructions Simulated +system.cpu0.committedOps 70131195 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.866000 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.866000 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.535906 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.535906 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 83223669 # number of integer regfile reads +system.cpu0.int_regfile_writes 47570918 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16180 # number of floating regfile reads +system.cpu0.fp_regfile_writes 12936 # number of floating regfile writes +system.cpu0.cc_regfile_reads 270428616 # number of cc regfile reads +system.cpu0.cc_regfile_writes 28197078 # number of cc regfile writes +system.cpu0.misc_regfile_reads 191501099 # number of misc regfile reads +system.cpu0.misc_regfile_writes 720417 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 852560 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.984422 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42511963 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 853072 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.833968 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.580964 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.403471 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641760 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358210 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 328.271130 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 183.713292 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.641155 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.358815 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189858417 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189858417 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12600621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12736293 # 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number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84951 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 181875 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13440 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14180 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27620 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 29 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 50 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 79 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2338284 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2195631 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4533915 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2435208 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26167287 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9644451 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9961517 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19605968 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 277862 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 266378 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 544240 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 221325 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 253024 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474349 # 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number of overall hits +system.cpu0.dcache.overall_hits::total 41602692 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 422442 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 405866 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 828308 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1913785 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1789558 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3703343 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 96940 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84905 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 181845 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13431 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14182 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27613 # 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number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 81474507999 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 173126878114 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 91652370115 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 81474507999 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 173126878114 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13021272 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13144717 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26165989 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9643992 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9961999 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19605991 # 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miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.348821 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318911 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.334182 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060725 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 22665264 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23106716 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45771980 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22943113 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23373075 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46316188 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032442 # 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miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000136 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000204 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000172 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.103151 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.095030 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.099052 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106125 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097582 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.101814 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16547.597759 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16417.728515 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16483.974149 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44231.715085 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41795.422208 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 43054.974959 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13622.358110 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14768.617419 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14210.843157 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16569.241379 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17600.360000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17221.848101 # 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miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16586.734300 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16333.464414 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 16462.633560 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44229.334488 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41823.349749 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43066.695965 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13625.734867 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14773.462347 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14215.206171 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 16696.714286 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 17694.244898 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17331.506494 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39230.935228 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37111.058273 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 38203.930116 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37667.932417 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 35729.277661 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36730.036074 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1114371 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 157529 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 70035 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610547002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784492003 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430732877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005306500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436039377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604677878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615853502 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220531380 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016244 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 768982 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1180474 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9648547200 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9090744839 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 18739292039 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10628456705 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9989890346 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 20618347051 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3173952500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2610543001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784495501 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2430739877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005307000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436046877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5604692377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4615850001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220542378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016262 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015948 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014643 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227771 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.219087 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223521 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017716 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020520 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019212 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000136 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000204 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000172 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016121 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015568 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.015842 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018684 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017888 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018282 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13498.833162 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13689.935191 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13594.905432 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44118.620594 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42275.061097 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43221.693957 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15403.782774 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15501.829301 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15450.819703 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11959.576894 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15349.191641 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13890.760891 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14568.689655 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15599.640000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15221.189873 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26391.904416 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25276.856624 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25838.808321 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24769.875092 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23912.260930 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24346.480321 # average overall mshr miss latency +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228304 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.218521 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223516 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017780 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020470 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019215 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000131 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000199 # 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average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1805,15 +1007,150 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27353552 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14236577 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 553412 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17312116 # 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Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 43134734 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43134734 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19500172 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19604543 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39104715 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19500172 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19604543 # 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number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14213949952 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14204519409 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28418469361 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14213949952 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14204519409 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28418469361 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14213949952 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14204519409 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28418469361 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20539505 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20650160 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41189665 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20539505 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20650160 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41189665 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20539505 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20650160 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41189665 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050602 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050635 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050618 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050602 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050635 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050618 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050602 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050635 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050618 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13676.030639 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13584.820646 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13630.288190 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13676.030639 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13584.820646 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13630.288190 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13676.030639 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13584.820646 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13630.288190 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9244 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 502 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.414343 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69295 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70585 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 139880 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 69295 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 70585 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 139880 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 69295 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 70585 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 139880 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970038 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 975032 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1945070 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 970038 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 975032 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1945070 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 970038 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 975032 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1945070 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11608622245 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11596487286 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23205109531 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11608622245 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11596487286 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23205109531 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11608622245 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11596487286 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23205109531 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49455500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49455500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 49455500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047222 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047222 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047228 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047217 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047222 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11930.218209 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11930.218209 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11930.218209 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.branchPred.lookups 27351704 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14236490 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 554287 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17308437 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 12845549 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.188464 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6764103 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29805 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.215534 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6761805 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 29778 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1837,25 +1174,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14379922 # DTB read hits -system.cpu1.dtb.read_misses 49648 # DTB read misses -system.cpu1.dtb.write_hits 10687800 # DTB write hits -system.cpu1.dtb.write_misses 9435 # DTB write misses +system.cpu1.dtb.read_hits 14383095 # DTB read hits +system.cpu1.dtb.read_misses 49639 # DTB read misses +system.cpu1.dtb.write_hits 10688826 # DTB write hits +system.cpu1.dtb.write_misses 9570 # DTB write misses system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 765 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1285 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3468 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 807 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1316 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14429570 # DTB read accesses -system.cpu1.dtb.write_accesses 10697235 # DTB write accesses +system.cpu1.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14432734 # DTB read accesses +system.cpu1.dtb.write_accesses 10698396 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25067722 # DTB hits -system.cpu1.dtb.misses 59083 # DTB misses -system.cpu1.dtb.accesses 25126805 # DTB accesses +system.cpu1.dtb.hits 25071921 # DTB hits +system.cpu1.dtb.misses 59209 # DTB misses +system.cpu1.dtb.accesses 25131130 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1877,124 +1214,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 20653653 # ITB inst hits -system.cpu1.itb.inst_misses 7569 # ITB inst misses +system.cpu1.itb.inst_hits 20651947 # ITB inst hits +system.cpu1.itb.inst_misses 7444 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2278 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2253 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1323 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1346 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20661222 # ITB inst accesses -system.cpu1.itb.hits 20653653 # DTB hits -system.cpu1.itb.misses 7569 # DTB misses -system.cpu1.itb.accesses 20661222 # DTB accesses -system.cpu1.numCycles 107242523 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20659391 # ITB inst accesses +system.cpu1.itb.hits 20651947 # DTB hits +system.cpu1.itb.misses 7444 # DTB misses +system.cpu1.itb.accesses 20659391 # DTB accesses +system.cpu1.numCycles 107242437 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40712684 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106782026 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27353552 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19607696 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61803081 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3231443 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 109598 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 4239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 431 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 249521 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 135474 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20651884 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 381778 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3230 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104630887 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.228118 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.325936 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40725111 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 106781914 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27351704 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19607354 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 61789362 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3232365 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 107163 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 4234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 251985 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137059 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20650163 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 382444 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3144 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 104631724 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.228100 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.325979 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75276432 71.94% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3916697 3.74% 75.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2503204 2.39% 78.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8106458 7.75% 85.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1592842 1.52% 87.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1179592 1.13% 88.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6154126 5.88% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1149786 1.10% 95.46% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4751750 4.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 75276621 71.94% 71.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3919456 3.75% 75.69% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2502030 2.39% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8106690 7.75% 85.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1591855 1.52% 87.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1179587 1.13% 88.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6153020 5.88% 94.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1148569 1.10% 95.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4753896 4.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104630887 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.255063 # Number of branch fetches per cycle +system.cpu1.fetch.rateDist::total 104631724 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.255046 # Number of branch fetches per cycle system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27864157 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57830739 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15747454 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1722658 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1465635 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1976909 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 152146 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 89229365 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 493204 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1465635 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28812184 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6716141 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45339545 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16513270 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5783839 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 85351560 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2174 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1570337 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 239520 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3169707 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 88205068 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 393510505 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 95333289 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6152 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 74299663 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13905405 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1590806 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1489461 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10064978 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15196570 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11856807 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2179914 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2787279 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 82067057 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1161463 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78685046 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94868 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10122036 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25487135 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106552 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104630887 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.752025 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.430826 # Number of insts issued each cycle +system.cpu1.decode.IdleCycles 27872686 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 57819434 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 15751164 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1722324 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1465861 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1979467 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 152392 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 89250616 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 494405 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1465861 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28821025 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 6714609 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 45327507 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16516394 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 5786062 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 85371989 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2599 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1571177 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 234219 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 3175787 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 88221695 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 393591898 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 95352384 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6204 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 74304877 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13916818 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1590220 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1488950 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10060689 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15200897 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11860337 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2181365 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2795831 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 82084086 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1161665 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 78697860 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94798 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10134538 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25514104 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 106722 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 104631724 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.752141 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.431263 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72948465 69.72% 69.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10708543 10.23% 79.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8057357 7.70% 87.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6681907 6.39% 94.04% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2500436 2.39% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1544614 1.48% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1464658 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 495950 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 228957 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72948361 69.72% 69.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10716718 10.24% 79.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8047314 7.69% 87.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6681191 6.39% 94.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2496863 2.39% 96.42% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1548306 1.48% 97.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1467102 1.40% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 495605 0.47% 99.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 230264 0.22% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104630887 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 104631724 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 103296 8.95% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 5 0.00% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 103418 8.95% 8.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 4 0.00% 8.95% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available @@ -2022,131 +1359,131 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.95% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 535211 46.35% 55.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 516097 44.70% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 534479 46.25% 55.20% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 517677 44.80% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52538123 66.77% 66.77% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 58820 0.07% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4114 0.01% 66.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 52546114 66.77% 66.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 58878 0.07% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4118 0.01% 66.85% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14784683 18.79% 85.64% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11299162 14.36% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14788040 18.79% 85.64% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11300566 14.36% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78685046 # Type of FU issued -system.cpu1.iq.rate 0.733711 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1154609 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014674 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 263236691 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 93395575 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 76291766 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 13765 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7276 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6039 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79832108 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7409 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 367192 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 78697860 # Type of FU issued +system.cpu1.iq.rate 0.733831 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1155578 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014684 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 263263981 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 93425233 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 76303202 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 13839 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7410 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6119 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 79845879 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7421 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 368633 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2204039 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2671 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 53511 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1150974 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2206977 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2711 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 53558 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1154048 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 193750 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 155367 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 194646 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 154093 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1465635 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4317272 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2160865 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 83369977 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 136369 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15196570 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11856807 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 585220 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 46964 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2101356 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 53511 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 256264 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 221755 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 478019 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 78073190 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14542904 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 552934 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1465861 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4319089 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 2154851 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 83386940 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 137036 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15200897 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11860337 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585271 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 47319 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2094987 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 53558 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 256552 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 222245 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 478797 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 78084459 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14546039 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 554355 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 141457 # number of nop insts executed -system.cpu1.iew.exec_refs 25733696 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14521478 # Number of branches executed -system.cpu1.iew.exec_stores 11190792 # Number of stores executed -system.cpu1.iew.exec_rate 0.728006 # Inst execution rate -system.cpu1.iew.wb_sent 77444186 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 76297805 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39935797 # num instructions producing a value -system.cpu1.iew.wb_consumers 69997959 # num instructions consuming a value +system.cpu1.iew.exec_nop 141189 # number of nop insts executed +system.cpu1.iew.exec_refs 25737628 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14524352 # Number of branches executed +system.cpu1.iew.exec_stores 11191589 # Number of stores executed +system.cpu1.iew.exec_rate 0.728112 # Inst execution rate +system.cpu1.iew.wb_sent 77455792 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 76309321 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 39942887 # num instructions producing a value +system.cpu1.iew.wb_consumers 70003346 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.711451 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570528 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.711559 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570585 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11451015 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1054911 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 403289 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 102066180 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.704508 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.588054 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11462178 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1054943 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 403929 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 102065282 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.704569 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.588134 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73979517 72.48% 72.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12597540 12.34% 84.82% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6450417 6.32% 91.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2677104 2.62% 93.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1410201 1.38% 95.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 931945 0.91% 96.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1826334 1.79% 97.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 426802 0.42% 98.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1766320 1.73% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 73979562 72.48% 72.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12596710 12.34% 84.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6446210 6.32% 91.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2677597 2.62% 93.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1413220 1.38% 95.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 933927 0.92% 96.06% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1825426 1.79% 97.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 426013 0.42% 98.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1766617 1.73% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 102066180 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 59233366 # Number of instructions committed -system.cpu1.commit.committedOps 71906393 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 102065282 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 59241455 # Number of instructions committed +system.cpu1.commit.committedOps 71912019 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23698364 # Number of memory references committed -system.cpu1.commit.loads 12992531 # Number of loads committed -system.cpu1.commit.membars 441834 # Number of memory barriers committed -system.cpu1.commit.branches 13745002 # Number of branches committed -system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 63017798 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2684230 # Number of function calls committed. +system.cpu1.commit.refs 23700209 # Number of memory references committed +system.cpu1.commit.loads 12993920 # Number of loads committed +system.cpu1.commit.membars 441872 # Number of memory barriers committed +system.cpu1.commit.branches 13745651 # Number of branches committed +system.cpu1.commit.fp_insts 6045 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 63021281 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2683532 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 48146836 66.96% 66.96% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57080 0.08% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 48150599 66.96% 66.96% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57094 0.08% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction @@ -2170,88 +1507,186 @@ system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.04% # system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4113 0.01% 67.04% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4117 0.01% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12992531 18.07% 85.11% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10705833 14.89% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 12993920 18.07% 85.11% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10706289 14.89% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71906393 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1766320 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 71912019 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1766617 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171177235 # The number of ROB reads -system.cpu1.rob.rob_writes 169283950 # The number of ROB writes -system.cpu1.timesIdled 392418 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2611636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951410112 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 59150362 # Number of Instructions Simulated -system.cpu1.committedOps 71823389 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.813049 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.813049 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.551557 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.551557 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84951910 # number of integer regfile reads -system.cpu1.int_regfile_writes 48574213 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16611 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13102 # number of floating regfile writes -system.cpu1.cc_regfile_reads 275725718 # number of cc regfile reads -system.cpu1.cc_regfile_writes 28996859 # number of cc regfile writes -system.cpu1.misc_regfile_reads 192674093 # number of misc regfile reads -system.cpu1.misc_regfile_writes 799402 # number of misc regfile writes +system.cpu1.rob.rob_reads 171199210 # The number of ROB reads +system.cpu1.rob.rob_writes 169319306 # The number of ROB writes +system.cpu1.timesIdled 392561 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2610713 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2951410695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 59158214 # Number of Instructions Simulated +system.cpu1.committedOps 71828778 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.812807 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.812807 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.551631 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.551631 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 84962024 # number of integer regfile reads +system.cpu1.int_regfile_writes 48578648 # number of integer regfile writes +system.cpu1.fp_regfile_reads 16598 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13166 # number of floating regfile writes +system.cpu1.cc_regfile_reads 275767015 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29005141 # number of cc regfile writes +system.cpu1.misc_regfile_reads 192510337 # number of misc regfile reads +system.cpu1.misc_regfile_writes 799392 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30210 # Transaction distribution +system.iobus.trans_dist::ReadResp 30210 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326614949 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36834534 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 0.982061 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.982055 # Cycle average of tags in use system.iocache.tags.total_refs 16 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.982061 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.061379 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.061379 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.982055 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061378 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061378 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328305 # Number of tag accesses -system.iocache.tags.data_accesses 328305 # Number of data accesses +system.iocache.tags.tag_accesses 328241 # Number of tag accesses +system.iocache.tags.data_accesses 328241 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 8 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 8 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29662377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29662377 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29662377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29662377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29662377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29662377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29659377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36232 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36232 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000221 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000221 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68249.154993 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69566.014635 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 65322.906692 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10006.781804 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10044.162983 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.500546 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64274.914919 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65547.461649 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64869.592247 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64620.091520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65977.465861 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64962.074596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67026.119403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62939.311927 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64620.091520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65550.724638 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62482.734391 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65977.465861 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64962.074596 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 68015 # Transaction distribution +system.membus.trans_dist::ReadResp 68014 # Transaction distribution +system.membus.trans_dist::WriteReq 27608 # Transaction distribution +system.membus.trans_dist::WriteResp 27608 # Transaction distribution +system.membus.trans_dist::Writeback 95499 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4652 # Transaction distribution +system.membus.trans_dist::ReadExReq 138449 # Transaction distribution +system.membus.trans_dist::ReadExResp 138449 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464808 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572448 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 645160 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17335960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17499937 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19819233 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 234 # Total snoops (count) +system.membus.snoop_fanout::samples 311043 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 311043 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 311043 # Request fanout histogram +system.membus.reqLayer0.occupancy 81528999 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1699500 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1433996498 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 1730108850 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38499466 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 2655847 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2655761 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 703475 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2844 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 77 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2921 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296861 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296861 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891199 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533159 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43047 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169738 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6637143 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124509952 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99813985 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66376 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294776 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224685089 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69111 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3663534 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099284 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3627058 99.00% 99.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3663534 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4671361722 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 8762587438 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3909721674 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26515368 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 96849116 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index fd62dd2fe..0d43a2133 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -4,28 +4,15 @@ sim_seconds 2.904683 # Nu sim_ticks 2904682547500 # Number of ticks simulated final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 680974 # Simulator instruction rate (inst/s) -host_op_rate 821042 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17584626781 # Simulator tick rate (ticks/s) -host_mem_usage 555668 # Number of bytes of host memory used -host_seconds 165.18 # Real time elapsed on the host -sim_insts 112485367 # Number of instructions simulated -sim_ops 135622163 # Number of ops (including micro ops) simulated +host_inst_rate 744036 # Simulator instruction rate (inst/s) +host_op_rate 897074 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 19213049576 # Simulator tick rate (ticks/s) +host_mem_usage 562336 # Number of bytes of host memory used +host_seconds 151.18 # Real time elapsed on the host +sim_insts 112485415 # Number of instructions simulated +sim_ops 135622211 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory @@ -33,16 +20,16 @@ system.physmem.bytes_read::cpu0.data 4265248 # Nu system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory @@ -50,13 +37,13 @@ system.physmem.num_reads::cpu0.data 67163 # Nu system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s) @@ -64,17 +51,17 @@ system.physmem.bw_read::cpu0.data 1468404 # To system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s) @@ -82,6 +69,7 @@ system.physmem.bw_total::cpu0.data 1474434 # To system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 168816 # Number of read requests accepted system.physmem.writeReqs 123423 # Number of write requests accepted @@ -94,7 +82,7 @@ system.physmem.bytesReadSys 10229960 # To system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4512 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9768 # Per bank write bursts system.physmem.perBankRdBursts::1 9653 # Per bank write bursts system.physmem.perBankRdBursts::2 10324 # Per bank write bursts @@ -243,13 +231,13 @@ system.physmem.wrQLenPdf::63 7 # Wh system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.865343 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.865134 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5740 9.81% 71.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3179 5.43% 76.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2292 3.92% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1563 2.67% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5741 9.81% 71.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3177 5.43% 76.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2294 3.92% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1562 2.67% 83.37% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation @@ -295,12 +283,12 @@ system.physmem.wrPerTurnAround::124-127 2 0.03% 99.85% # Wr system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads -system.physmem.totQLat 1487003250 # Total ticks spent queuing -system.physmem.totMemAccLat 4649565750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 1486855250 # Total ticks spent queuing +system.physmem.totMemAccLat 4649417750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8816.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8815.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27566.05 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 27565.17 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s @@ -317,10 +305,10 @@ system.physmem.readRowHitRate 82.41 # Ro system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes system.physmem.avgGap 9939406.38 # Average gap between requests system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2756104234500 # Time in different power states +system.physmem.memoryStateTime::IDLE 2756105768250 # Time in different power states system.physmem.memoryStateTime::REF 96993520000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 51578640500 # Time in different power states +system.physmem.memoryStateTime::ACT 51577106750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ) system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ) @@ -332,651 +320,33 @@ system.physmem.writeEnergy::0 388618560 # En system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ) system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ) system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 86947691130 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 86007166335 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1666535924250 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1667360946000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1944635950455 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1944428294400 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.484547 # Core power per rank (mW) -system.physmem.averagePower::1 669.413056 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 70576 # Transaction distribution -system.membus.trans_dist::ReadResp 70576 # Transaction distribution -system.membus.trans_dist::WriteReq 27613 # Transaction distribution -system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 82818 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4510 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4512 # Transaction distribution -system.membus.trans_dist::ReadExReq 129059 # Transaction distribution -system.membus.trans_dist::ReadExResp 129059 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 618567 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 219 # Total snoops (count) -system.membus.snoop_fanout::samples 283020 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 283020 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 283020 # Request fanout histogram -system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1640331988 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 89435 # number of replacements -system.l2c.tags.tagsinuse 64928.071050 # Cycle average of tags in use -system.l2c.tags.total_refs 2766017 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.882651 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50556.019026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2064.899937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5760.330467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26291974 # Number of tag accesses -system.l2c.tags.data_accesses 26291974 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6206 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3383 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 836468 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 253614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5323 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2799 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 844176 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 261862 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2213831 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 686956 # number of Writeback hits -system.l2c.Writeback_hits::total 686956 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 86550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78519 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 165069 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6206 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3383 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 836468 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 340164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5323 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2799 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 844176 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 340381 # number of demand (read+write) hits -system.l2c.demand_hits::total 2378900 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6206 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3383 # number of overall hits -system.l2c.overall_hits::cpu0.inst 836468 # number of overall hits -system.l2c.overall_hits::cpu0.data 340164 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5323 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2799 # number of overall hits -system.l2c.overall_hits::cpu1.inst 844176 # number of overall hits -system.l2c.overall_hits::cpu1.data 340381 # number of overall hits -system.l2c.overall_hits::total 2378900 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5123 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9868 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7019 # number of ReadReq misses -system.l2c.ReadReq_misses::total 30170 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1297 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1431 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62337 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 68504 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130841 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8151 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 67460 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9868 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 75523 # 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number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 566500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 717694500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 529005500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2229966250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 232490 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 231490 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 463980 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 45998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 45998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4342132899 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4712323819 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9054456718 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 591637750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4733045399 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 566500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 717694500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5241329319 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11284422968 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 591637750 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.165496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.181588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063392 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63831.251220 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62881.393361 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61336.650646 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56855.945923 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55978.536742 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.563631 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actBackEnergy::0 86946648885 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 86006740545 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1666536838500 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1667361319500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1944635822460 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1944428242110 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.484503 # Core power per rank (mW) +system.physmem.averagePower::1 669.413038 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 2301460 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2301445 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5925126 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205689597 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53732 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104795 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3246673 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4418860748 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782893012 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 59038 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1000,25 +370,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12289558 # DTB read hits -system.cpu0.dtb.read_misses 5978 # DTB read misses -system.cpu0.dtb.write_hits 9834640 # DTB write hits -system.cpu0.dtb.write_misses 1046 # DTB write misses +system.cpu0.dtb.read_hits 12289553 # DTB read hits +system.cpu0.dtb.read_misses 5977 # DTB read misses +system.cpu0.dtb.write_hits 9834643 # DTB write hits +system.cpu0.dtb.write_misses 1047 # DTB write misses system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 865 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12295536 # DTB read accesses -system.cpu0.dtb.write_accesses 9835686 # DTB write accesses +system.cpu0.dtb.read_accesses 12295530 # DTB read accesses +system.cpu0.dtb.write_accesses 9835690 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22124198 # DTB hits +system.cpu0.dtb.hits 22124196 # DTB hits system.cpu0.dtb.misses 7024 # DTB misses -system.cpu0.dtb.accesses 22131222 # DTB accesses +system.cpu0.dtb.accesses 22131220 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1040,7 +410,7 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 58032783 # ITB inst hits +system.cpu0.itb.inst_hits 58032770 # ITB inst hits system.cpu0.itb.inst_misses 3465 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -1057,38 +427,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58036248 # ITB inst accesses -system.cpu0.itb.hits 58032783 # DTB hits +system.cpu0.itb.inst_accesses 58036235 # ITB inst accesses +system.cpu0.itb.hits 58032770 # DTB hits system.cpu0.itb.misses 3465 # DTB misses -system.cpu0.itb.accesses 58036248 # DTB accesses +system.cpu0.itb.accesses 58036235 # DTB accesses system.cpu0.numCycles 2905319694 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56513151 # Number of instructions committed -system.cpu0.committedOps 68067864 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60172055 # Number of integer alu accesses +system.cpu0.committedInsts 56513131 # Number of instructions committed +system.cpu0.committedOps 68067849 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60172046 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses -system.cpu0.num_func_calls 4924591 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7649382 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60172055 # number of integer instructions +system.cpu0.num_func_calls 4924583 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7649378 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60172046 # number of integer instructions system.cpu0.num_fp_insts 6287 # number of float instructions -system.cpu0.num_int_register_reads 109432777 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41532372 # number of times the integer registers were written +system.cpu0.num_int_register_reads 109432768 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41532346 # number of times the integer registers were written system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245794859 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26123489 # number of times the CC registers were written -system.cpu0.num_mem_refs 22763355 # number of memory refs -system.cpu0.num_load_insts 12450624 # Number of load instructions -system.cpu0.num_store_insts 10312731 # Number of store instructions +system.cpu0.num_cc_register_reads 245794871 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26123486 # number of times the CC registers were written +system.cpu0.num_mem_refs 22763364 # number of memory refs +system.cpu0.num_load_insts 12450622 # Number of load instructions +system.cpu0.num_store_insts 10312742 # Number of store instructions system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles -system.cpu0.Branches 12983474 # Number of branches fetched +system.cpu0.Branches 12983457 # Number of branches fetched system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46789639 67.21% 67.21% # Class of executed instruction -system.cpu0.op_class::IntMult 58624 0.08% 67.30% # Class of executed instruction +system.cpu0.op_class::IntAlu 46789630 67.21% 67.21% # Class of executed instruction +system.cpu0.op_class::IntMult 58620 0.08% 67.30% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction @@ -1116,147 +486,21 @@ system.cpu0.op_class::SimdFloatMisc 4273 0.01% 67.30% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction -system.cpu0.op_class::MemRead 12450624 17.88% 85.19% # Class of executed instruction -system.cpu0.op_class::MemWrite 10312731 14.81% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 12450622 17.88% 85.19% # Class of executed instruction +system.cpu0.op_class::MemWrite 10312742 14.81% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69618095 # Class of executed instruction +system.cpu0.op_class::total 69618091 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 1698167 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113885210 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.043397 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089770 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685078 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117282580 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117282580 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57188150 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56697060 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113885210 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57188150 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56697060 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113885210 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 57188150 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 56697060 # number of overall hits -system.cpu0.icache.overall_hits::total 113885210 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844633 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 854052 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1698685 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844633 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 854052 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1698685 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844633 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 854052 # number of overall misses -system.cpu0.icache.overall_misses::total 1698685 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11522277749 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11755816000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23278093749 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11522277749 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11755816000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23278093749 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11522277749 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11755816000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23278093749 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 58032783 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 57551112 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115583895 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58032783 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57551112 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115583895 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58032783 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57551112 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115583895 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014554 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014840 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014554 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014840 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014554 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014840 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.756537 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.754371 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.596458 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.756537 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.754371 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13703.596458 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.756537 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.754371 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13703.596458 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844633 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854052 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 844633 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 854052 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1698685 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 844633 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 854052 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1698685 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9830070251 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10044101000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19874171251 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9830070251 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10044101000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19874171251 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830070251 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044101000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19874171251 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.273962 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.526291 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.739063 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.273962 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.526291 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.739063 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.273962 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.526291 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.739063 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 822985 # number of replacements +system.cpu0.dcache.tags.replacements 822992 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.850755 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43241496 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 823497 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.509597 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 43241503 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 823504 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.509160 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068900 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781856 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.068917 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.781838 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625135 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374574 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy @@ -1266,35 +510,35 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::1 369 system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177151472 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177151472 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11581595 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11533851 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23115446 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9437905 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9389787 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18827692 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199754 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192263 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392017 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227024 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216270 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 177151535 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177151535 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11581583 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11533865 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23115448 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9437909 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9389790 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18827699 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 199753 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 192262 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392015 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227025 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 216269 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 443294 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235238 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225056 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235239 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 225055 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460294 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21019500 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20923638 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41943138 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21219254 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21115901 # number of overall hits -system.cpu0.dcache.overall_hits::total 42335155 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197290 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 205524 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402814 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 150195 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 21019492 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20923655 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41943147 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 21219245 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21115917 # number of overall hits +system.cpu0.dcache.overall_hits::total 42335162 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197297 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 205526 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 402823 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 150193 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::cpu1.data 148466 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298661 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298659 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 58530 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::cpu1.data 60464 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 118994 # number of SoftPFReq misses @@ -1303,59 +547,59 @@ system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11645 system.cpu0.dcache.LoadLockedReq_misses::total 22772 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 347485 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 353990 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 701475 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 406015 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 414454 # number of overall misses -system.cpu0.dcache.overall_misses::total 820469 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2867929500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066278250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5934207750 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744490374 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031803093 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11776293467 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 347490 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 353992 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 701482 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 406020 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 414456 # number of overall misses +system.cpu0.dcache.overall_misses::total 820476 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2868020500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3066163250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5934183750 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5744459123 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6031837843 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11776296966 # number of WriteReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 135157750 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 145057500 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 280215250 # number of LoadLockedReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 52002 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 52002 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8612419874 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 9098081343 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17710501217 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8612419874 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 9098081343 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17710501217 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778885 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739375 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23518260 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9588100 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9538253 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19126353 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258284 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 252727 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511011 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238151 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227915 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 8612479623 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9098001093 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 17710480716 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8612479623 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9098001093 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 17710480716 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11778880 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11739391 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23518271 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9588102 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9538256 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19126358 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 258283 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 252726 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511009 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238152 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227914 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 466066 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235240 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 225056 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235241 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 225055 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460296 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21366985 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21277628 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42644613 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21625269 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21530355 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43155624 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016749 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 21366982 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21277647 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42644629 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21625265 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21530373 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43155638 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016750 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017507 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.017128 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015665 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015565 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.015615 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226611 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.239246 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232860 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226612 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.239247 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232861 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046722 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051094 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048860 # miss rate for LoadLockedReq accesses @@ -1367,23 +611,23 @@ system.cpu0.dcache.demand_miss_rate::total 0.016449 # system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018775 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019250 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.019012 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.618683 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14919.319642 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.880595 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38246.881547 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.504567 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.302139 # average WriteReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14536.564165 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14918.614920 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.491871 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38247.182778 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40627.738627 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39430.577903 # average WriteReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12146.827537 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12456.633748 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12305.254260 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26001 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26001 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24785.011940 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.520786 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25247.515901 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21212.073135 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.968959 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21585.826176 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24784.827255 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25701.148876 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25247.234734 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21211.959073 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21951.669400 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21585.617027 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -1392,8 +636,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686956 # number of writebacks -system.cpu0.dcache.writebacks::total 686956 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 686960 # number of writebacks +system.cpu0.dcache.writebacks::total 686960 # number of writebacks system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 328 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits @@ -1406,12 +650,12 @@ system.cpu0.dcache.demand_mshr_hits::total 615 # system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::cpu1.data 328 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 615 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 197003 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205196 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 402199 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 150195 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 197010 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 205198 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 402208 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 150193 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 148466 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298661 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298659 # number of WriteReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 57639 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 59222 # number of SoftPFReq MSHR misses system.cpu0.dcache.SoftPFReq_mshr_misses::total 116861 # number of SoftPFReq MSHR misses @@ -1420,18 +664,18 @@ system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4463 system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8558 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 347198 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 353662 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 700860 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 404837 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 412884 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817721 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467791750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647821500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115613250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416619578 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704545869 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121165447 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_misses::cpu0.data 347203 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 353664 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 700867 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 404842 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 412886 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 817728 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2467868750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2647702500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5115571250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5416592829 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5704580119 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11121172948 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 696038250 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 742244000 # number of SoftPFReq MSHR miss cycles system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1438282250 # number of SoftPFReq MSHR miss cycles @@ -1440,47 +684,47 @@ system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52699750 system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100974500 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 47998 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 47998 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884411328 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352367369 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16236778697 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580449578 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094611369 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17675060947 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688394500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884461579 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8352282619 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 16236744198 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8580499829 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9094526619 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17675026448 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2688395000 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3103027500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791422500 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2165315000 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429802500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853709500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4853710000 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5367515000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221224500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016725 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221225000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016726 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017479 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017102 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015665 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015565 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015615 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223161 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234332 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228686 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223162 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.234333 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228687 # mshr miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017195 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018362 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000009 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016250 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016621 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.016435 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018721 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019177 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.018948 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.670914 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.865085 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12719.109819 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36063.914098 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.247538 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37236.751524 # average WriteReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12526.616669 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12903.159388 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12718.720786 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36064.216235 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38423.478231 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37237.026000 # average WriteReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12075.821059 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12533.247780 # average SoftPFReq mshr miss latency system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency @@ -1489,12 +733,12 @@ system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11808.144746 system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11798.843188 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23999 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23999 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.688783 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.807486 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.935903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.825517 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22027.037543 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21615.026332 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22708.506490 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23616.434296 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23166.655297 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21194.687876 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22026.725583 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21614.799112 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1505,6 +749,132 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1698167 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113885267 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.043430 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089773 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685075 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 117282637 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117282637 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57188138 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56697129 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113885267 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57188138 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56697129 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113885267 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57188138 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56697129 # number of overall hits +system.cpu0.icache.overall_hits::total 113885267 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844632 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 854053 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 57551182 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115583952 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014554 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014840 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014554 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014840 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014554 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014840 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.719410 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.732400 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.567023 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13703.567023 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13703.567023 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844632 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854053 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 844632 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 854053 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1698685 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 844632 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 854053 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1698685 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9830027251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10044094000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19874121251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9830027251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10044094000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19874121251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830027251 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044094000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19874121251 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.709629 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1528,9 +898,9 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12236378 # DTB read hits +system.cpu1.dtb.read_hits 12236392 # DTB read hits system.cpu1.dtb.read_misses 5657 # DTB read misses -system.cpu1.dtb.write_hits 9775690 # DTB write hits +system.cpu1.dtb.write_hits 9775692 # DTB write hits system.cpu1.dtb.write_misses 790 # DTB write misses system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA @@ -1538,15 +908,15 @@ system.cpu1.dtb.flush_tlb_mva_asid 0 # Nu system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12242035 # DTB read accesses -system.cpu1.dtb.write_accesses 9776480 # DTB write accesses +system.cpu1.dtb.read_accesses 12242049 # DTB read accesses +system.cpu1.dtb.write_accesses 9776482 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22012068 # DTB hits +system.cpu1.dtb.hits 22012084 # DTB hits system.cpu1.dtb.misses 6447 # DTB misses -system.cpu1.dtb.accesses 22018515 # DTB accesses +system.cpu1.dtb.accesses 22018531 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1568,7 +938,7 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 57551112 # ITB inst hits +system.cpu1.itb.inst_hits 57551182 # ITB inst hits system.cpu1.itb.inst_misses 3277 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1585,38 +955,38 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57554389 # ITB inst accesses -system.cpu1.itb.hits 57551112 # DTB hits +system.cpu1.itb.inst_accesses 57554459 # ITB inst accesses +system.cpu1.itb.hits 57551182 # DTB hits system.cpu1.itb.misses 3277 # DTB misses -system.cpu1.itb.accesses 57554389 # DTB accesses +system.cpu1.itb.accesses 57554459 # DTB accesses system.cpu1.numCycles 2904045401 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55972216 # Number of instructions committed -system.cpu1.committedOps 67554299 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59752061 # Number of integer alu accesses +system.cpu1.committedInsts 55972284 # Number of instructions committed +system.cpu1.committedOps 67554362 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59752131 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses -system.cpu1.num_func_calls 4972349 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7584517 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59752061 # number of integer instructions +system.cpu1.num_func_calls 4972365 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7584533 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59752131 # number of integer instructions system.cpu1.num_fp_insts 5003 # number of float instructions -system.cpu1.num_int_register_reads 108688873 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41135339 # number of times the integer registers were written +system.cpu1.num_int_register_reads 108688988 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41135378 # number of times the integer registers were written system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 244070995 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25783519 # number of times the CC registers were written -system.cpu1.num_mem_refs 22653694 # number of memory refs -system.cpu1.num_load_insts 12397895 # Number of load instructions -system.cpu1.num_store_insts 10255799 # Number of store instructions +system.cpu1.num_cc_register_reads 244071190 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25783552 # number of times the CC registers were written +system.cpu1.num_mem_refs 22653716 # number of memory refs +system.cpu1.num_load_insts 12397911 # Number of load instructions +system.cpu1.num_store_insts 10255805 # Number of store instructions system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles -system.cpu1.Branches 12941354 # Number of branches fetched +system.cpu1.Branches 12941389 # Number of branches fetched system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46411426 67.14% 67.14% # Class of executed instruction -system.cpu1.op_class::IntMult 56056 0.08% 67.22% # Class of executed instruction +system.cpu1.op_class::IntAlu 46411475 67.14% 67.14% # Class of executed instruction +system.cpu1.op_class::IntMult 56055 0.08% 67.22% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction @@ -1644,13 +1014,115 @@ system.cpu1.op_class::SimdFloatMisc 4164 0.01% 67.23% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction -system.cpu1.op_class::MemRead 12397895 17.94% 85.16% # Class of executed instruction -system.cpu1.op_class::MemWrite 10255799 14.84% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12397911 17.94% 85.16% # Class of executed instruction +system.cpu1.op_class::MemWrite 10255805 14.84% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69125473 # Class of executed instruction +system.cpu1.op_class::total 69125543 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.iobus.trans_dist::ReadReq 30195 # Transaction distribution +system.iobus.trans_dist::ReadResp 30195 # Transaction distribution +system.iobus.trans_dist::WriteReq 59038 # Transaction distribution +system.iobus.trans_dist::WriteResp 59038 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements system.iocache.tags.tagsinuse 1.083103 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1736,5 +1208,533 @@ system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 89435 # number of replacements +system.l2c.tags.tagsinuse 64928.071220 # Cycle average of tags in use +system.l2c.tags.total_refs 2766032 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.882748 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 50556.019197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2064.899938 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5760.330465 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.771424 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.031508 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.087896 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.040455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990724 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65236 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026104 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013445 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991590 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991684 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991639 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418686 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465941 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.442164 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59942.185008 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57386.469559 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60084.515606 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56618.658303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57321.604441 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 70576 # Transaction distribution +system.membus.trans_dist::ReadResp 70576 # Transaction distribution +system.membus.trans_dist::WriteReq 27613 # Transaction distribution +system.membus.trans_dist::WriteResp 27613 # Transaction distribution +system.membus.trans_dist::Writeback 82818 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4509 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4511 # Transaction distribution +system.membus.trans_dist::ReadExReq 129059 # Transaction distribution +system.membus.trans_dist::ReadExResp 129059 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438204 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 545868 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 618565 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 219 # Total snoops (count) +system.membus.snoop_fanout::samples 283019 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 283019 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 283019 # Request fanout histogram +system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1736000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1336695000 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1640329489 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 2301469 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2301454 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 686960 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295908 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295908 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457281 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34351 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5925146 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868901 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46156 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205690309 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 53730 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3283144 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104794 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 3246684 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3283144 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4418882248 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 3782924511 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 385ae9f2d..560862ac3 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -4,40 +4,40 @@ sim_seconds 5.125902 # Nu sim_ticks 5125902116500 # Number of ticks simulated final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 134346 # Simulator instruction rate (inst/s) -host_op_rate 265563 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1687822207 # Simulator tick rate (ticks/s) -host_mem_usage 793660 # Number of bytes of host memory used -host_seconds 3036.99 # Real time elapsed on the host +host_inst_rate 182847 # Simulator instruction rate (inst/s) +host_op_rate 361437 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2297162464 # Simulator tick rate (ticks/s) +host_mem_usage 805240 # Number of bytes of host memory used +host_seconds 2231.41 # Real time elapsed on the host sim_insts 408006726 # Number of instructions simulated sim_ops 806511598 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory +system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s) @@ -45,11 +45,11 @@ system.physmem.bw_write::writebacks 1288465 # Wr system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 185800 # Number of read requests accepted system.physmem.writeReqs 149916 # Number of write requests accepted @@ -307,265 +307,6 @@ system.physmem.totalEnergy::0 3427824613320 # T system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ) system.physmem.averagePower::0 668.726542 # Core power per rank (mW) system.physmem.averagePower::1 668.742609 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 662592 # Transaction distribution -system.membus.trans_dist::ReadResp 662582 # Transaction distribution -system.membus.trans_dist::WriteReq 13889 # Transaction distribution -system.membus.trans_dist::WriteResp 13889 # Transaction distribution -system.membus.trans_dist::Writeback 103196 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution -system.membus.trans_dist::ReadExReq 133104 # Transaction distribution -system.membus.trans_dist::ReadExResp 133101 # Transaction distribution -system.membus.trans_dist::MessageReq 1644 # Transaction distribution -system.membus.trans_dist::MessageResp 1644 # Transaction distribution -system.membus.trans_dist::BadAddressError 10 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 949 # Total snoops (count) -system.membus.snoop_fanout::samples 338415 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 338415 # Request fanout histogram -system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks) -system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47575 # number of replacements -system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy -system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id -system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428670 # Number of tag accesses -system.iocache.tags.data_accesses 428670 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses -system.iocache.ReadReq_misses::total 910 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses -system.iocache.demand_misses::total 910 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses -system.iocache.overall_misses::total 910 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles -system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses -system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses -system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 46720 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. -system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. -system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 225681 # Transaction distribution -system.iobus.trans_dist::ReadResp 225681 # Transaction distribution -system.iobus.trans_dist::WriteReq 57721 # Transaction distribution -system.iobus.trans_dist::WriteResp 57721 # Transaction distribution -system.iobus.trans_dist::MessageReq 1644 # Transaction distribution -system.iobus.trans_dist::MessageResp 1644 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) -system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.branchPred.lookups 86911006 # Number of BP lookups system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect @@ -575,6 +316,7 @@ system.cpu.branchPred.BTBCorrect 0 # Nu system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.numCycles 449563158 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -769,8 +511,8 @@ system.cpu.iew.iewIQFullEvents 416093 # Nu system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute +system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute @@ -873,53 +615,236 @@ system.cpu.cc_regfile_reads 416306470 # nu system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads system.cpu.misc_regfile_writes 402647 # number of misc regfile writes -system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 58568 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) -system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu.dcache.tags.replacements 1657683 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits +system.cpu.dcache.overall_hits::total 19128334 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses +system.cpu.dcache.overall_misses::total 2535648 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks +system.cpu.dcache.writebacks::total 1559289 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency +system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed +system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed +system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # 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number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency +system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 994393 # number of replacements system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks. @@ -1102,236 +1027,6 @@ system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency -system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed -system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency -system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1657683 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1658195 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.537253 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996297 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88314142 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88314142 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10979297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10979297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8084679 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8084679 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64358 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64358 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19063976 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19063976 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19128334 # number of overall hits -system.cpu.dcache.overall_hits::total 19128334 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1796007 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1796007 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333248 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333248 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406393 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406393 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2129255 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2129255 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2535648 # number of overall misses -system.cpu.dcache.overall_misses::total 2535648 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26565336178 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26565336178 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12842853467 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12842853467 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39408189645 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39408189645 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39408189645 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39408189645 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12775304 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12775304 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8417927 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8417927 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 470751 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 470751 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21193231 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21193231 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21663982 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21663982 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140584 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140584 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039588 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039588 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863287 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.863287 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100469 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100469 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117044 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117044 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14791.332204 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14791.332204 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38538.426238 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38538.426238 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18507.970931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18507.970931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15541.664160 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15541.664160 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378856 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39922 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.489905 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1559289 # number of writebacks -system.cpu.dcache.writebacks::total 1559289 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 827651 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 827651 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44088 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44088 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 871739 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 871739 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 871739 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 871739 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968356 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968356 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289160 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289160 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402927 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402927 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1257516 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1257516 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1660443 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1660443 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12252685521 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12252685521 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11181268784 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11181268784 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5616168251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5616168251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23433954305 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23433954305 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29050122556 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29050122556 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97390324000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97390324000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2564320000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2564320000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99954644000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99954644000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075799 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075799 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034350 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855924 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855924 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059336 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059336 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076645 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076645 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12653.079571 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12653.079571 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38668.103417 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38668.103417 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13938.426194 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13938.426194 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18635.114229 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18635.114229 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17495.404874 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17495.404874 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 113085 # number of replacements system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks. @@ -1584,6 +1279,311 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 58568 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 225681 # Transaction distribution +system.iobus.trans_dist::ReadResp 225681 # Transaction distribution +system.iobus.trans_dist::WriteReq 57721 # Transaction distribution +system.iobus.trans_dist::WriteResp 57721 # Transaction distribution +system.iobus.trans_dist::MessageReq 1644 # Transaction distribution +system.iobus.trans_dist::MessageResp 1644 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks) +system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks) +system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) +system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) +system.iocache.tags.replacements 47575 # number of replacements +system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 428670 # Number of tag accesses +system.iocache.tags.data_accesses 428670 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses +system.iocache.ReadReq_misses::total 910 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses +system.iocache.demand_misses::total 910 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses +system.iocache.overall_misses::total 910 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles +system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 46720 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 662592 # Transaction distribution +system.membus.trans_dist::ReadResp 662582 # Transaction distribution +system.membus.trans_dist::WriteReq 13889 # Transaction distribution +system.membus.trans_dist::WriteResp 13889 # Transaction distribution +system.membus.trans_dist::Writeback 103196 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution +system.membus.trans_dist::ReadExReq 133104 # Transaction distribution +system.membus.trans_dist::ReadExResp 133101 # Transaction distribution +system.membus.trans_dist::MessageReq 1644 # Transaction distribution +system.membus.trans_dist::MessageResp 1644 # Transaction distribution +system.membus.trans_dist::BadAddressError 10 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 949 # Total snoops (count) +system.membus.snoop_fanout::samples 338415 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 338415 # Request fanout histogram +system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks) +system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks) +system.membus.respLayer4.utilization 0.0 # Layer utilization (%) +system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. +system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. +system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed |