diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs')
22 files changed, 37169 insertions, 37481 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index e432f371b..421497f85 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884236 # Number of seconds simulated -sim_ticks 1884235597000 # Number of ticks simulated -final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887184 # Number of seconds simulated +sim_ticks 1887184463000 # Number of ticks simulated +final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167027 # Simulator instruction rate (inst/s) -host_op_rate 167027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5607682389 # Simulator tick rate (ticks/s) -host_mem_usage 359752 # Number of bytes of host memory used -host_seconds 336.01 # Real time elapsed on the host -sim_insts 56122640 # Number of instructions simulated -sim_ops 56122640 # Number of ops (including micro ops) simulated +host_inst_rate 275099 # Simulator instruction rate (inst/s) +host_op_rate 275099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9249537203 # Simulator tick rate (ticks/s) +host_mem_usage 373576 # Number of bytes of host memory used +host_seconds 204.03 # Real time elapsed on the host +sim_insts 56128524 # Number of instructions simulated +sim_ops 56128524 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1053184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24861632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388463 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 558945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13194545 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 558945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13194545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404934 # Number of read requests accepted -system.physmem.writeReqs 159706 # Number of write requests accepted -system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue -system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25481 # Per bank write bursts -system.physmem.perBankRdBursts::1 25742 # Per bank write bursts -system.physmem.perBankRdBursts::2 25839 # Per bank write bursts -system.physmem.perBankRdBursts::3 25784 # Per bank write bursts -system.physmem.perBankRdBursts::4 25228 # Per bank write bursts -system.physmem.perBankRdBursts::5 24953 # Per bank write bursts -system.physmem.perBankRdBursts::6 24817 # Per bank write bursts -system.physmem.perBankRdBursts::7 24560 # Per bank write bursts -system.physmem.perBankRdBursts::8 25102 # Per bank write bursts -system.physmem.perBankRdBursts::9 25274 # Per bank write bursts -system.physmem.perBankRdBursts::10 25530 # Per bank write bursts -system.physmem.perBankRdBursts::11 24856 # Per bank write bursts -system.physmem.perBankRdBursts::12 24523 # Per bank write bursts -system.physmem.perBankRdBursts::13 25574 # Per bank write bursts -system.physmem.perBankRdBursts::14 25845 # Per bank write bursts +system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404899 # Number of read requests accepted +system.physmem.writeReqs 159652 # Number of write requests accepted +system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25492 # Per bank write bursts +system.physmem.perBankRdBursts::1 25732 # Per bank write bursts +system.physmem.perBankRdBursts::2 25844 # Per bank write bursts +system.physmem.perBankRdBursts::3 25788 # Per bank write bursts +system.physmem.perBankRdBursts::4 25096 # Per bank write bursts +system.physmem.perBankRdBursts::5 25019 # Per bank write bursts +system.physmem.perBankRdBursts::6 24724 # Per bank write bursts +system.physmem.perBankRdBursts::7 24556 # Per bank write bursts +system.physmem.perBankRdBursts::8 25196 # Per bank write bursts +system.physmem.perBankRdBursts::9 25300 # Per bank write bursts +system.physmem.perBankRdBursts::10 25394 # Per bank write bursts +system.physmem.perBankRdBursts::11 24993 # Per bank write bursts +system.physmem.perBankRdBursts::12 24525 # Per bank write bursts +system.physmem.perBankRdBursts::13 25570 # Per bank write bursts +system.physmem.perBankRdBursts::14 25834 # Per bank write bursts system.physmem.perBankRdBursts::15 25739 # Per bank write bursts -system.physmem.perBankWrBursts::0 10323 # Per bank write bursts -system.physmem.perBankWrBursts::1 10094 # Per bank write bursts -system.physmem.perBankWrBursts::2 10597 # Per bank write bursts -system.physmem.perBankWrBursts::3 9998 # Per bank write bursts -system.physmem.perBankWrBursts::4 9794 # Per bank write bursts -system.physmem.perBankWrBursts::5 9430 # Per bank write bursts -system.physmem.perBankWrBursts::6 9122 # Per bank write bursts -system.physmem.perBankWrBursts::7 8746 # Per bank write bursts -system.physmem.perBankWrBursts::8 9866 # Per bank write bursts -system.physmem.perBankWrBursts::9 8965 # Per bank write bursts -system.physmem.perBankWrBursts::10 9841 # Per bank write bursts -system.physmem.perBankWrBursts::11 9391 # Per bank write bursts -system.physmem.perBankWrBursts::12 9895 # Per bank write bursts -system.physmem.perBankWrBursts::13 10602 # Per bank write bursts -system.physmem.perBankWrBursts::14 10396 # Per bank write bursts -system.physmem.perBankWrBursts::15 10461 # Per bank write bursts +system.physmem.perBankWrBursts::0 8904 # Per bank write bursts +system.physmem.perBankWrBursts::1 8550 # Per bank write bursts +system.physmem.perBankWrBursts::2 9125 # Per bank write bursts +system.physmem.perBankWrBursts::3 8822 # Per bank write bursts +system.physmem.perBankWrBursts::4 8179 # Per bank write bursts +system.physmem.perBankWrBursts::5 8016 # Per bank write bursts +system.physmem.perBankWrBursts::6 7555 # Per bank write bursts +system.physmem.perBankWrBursts::7 7379 # Per bank write bursts +system.physmem.perBankWrBursts::8 8271 # Per bank write bursts +system.physmem.perBankWrBursts::9 7751 # Per bank write bursts +system.physmem.perBankWrBursts::10 8147 # Per bank write bursts +system.physmem.perBankWrBursts::11 7873 # Per bank write bursts +system.physmem.perBankWrBursts::12 8188 # Per bank write bursts +system.physmem.perBankWrBursts::13 9058 # Per bank write bursts +system.physmem.perBankWrBursts::14 9003 # Per bank write bursts +system.physmem.perBankWrBursts::15 8879 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1884226862500 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times write queue was full causing retry +system.physmem.totGap 1887175688500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404934 # Read request sizes (log2) +system.physmem.readPktSize::6 404899 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159706 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159652 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,193 +148,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads -system.physmem.totQLat 2143675250 # Total ticks spent queuing -system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads +system.physmem.totQLat 2145870750 # Total ticks spent queuing +system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing -system.physmem.readRowHits 364210 # Number of row buffer hits during reads -system.physmem.writeRowHits 132411 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes -system.physmem.avgGap 3337041.06 # Average gap between requests -system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.517914 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing +system.physmem.readRowHits 363622 # Number of row buffer hits during reads +system.physmem.writeRowHits 110090 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes +system.physmem.avgGap 3342790.44 # Average gap between requests +system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517315 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states +system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.585024 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.597050 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states +system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15006303 # Number of BP lookups -system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits +system.cpu.branchPred.lookups 15007831 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241313 # DTB read hits -system.cpu.dtb.read_misses 17796 # DTB read misses +system.cpu.dtb.read_hits 9242509 # DTB read hits +system.cpu.dtb.read_misses 17824 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766310 # DTB read accesses -system.cpu.dtb.write_hits 6385986 # DTB write hits -system.cpu.dtb.write_misses 2327 # DTB write misses -system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298447 # DTB write accesses -system.cpu.dtb.data_hits 15627299 # DTB hits -system.cpu.dtb.data_misses 20123 # DTB misses -system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064757 # DTB accesses -system.cpu.itb.fetch_hits 4016976 # ITB hits -system.cpu.itb.fetch_misses 6883 # ITB misses -system.cpu.itb.fetch_acv 674 # ITB acv -system.cpu.itb.fetch_accesses 4023859 # ITB accesses +system.cpu.dtb.read_accesses 766347 # DTB read accesses +system.cpu.dtb.write_hits 6385998 # DTB write hits +system.cpu.dtb.write_misses 2322 # DTB write misses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298454 # DTB write accesses +system.cpu.dtb.data_hits 15628507 # DTB hits +system.cpu.dtb.data_misses 20146 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1064801 # DTB accesses +system.cpu.itb.fetch_hits 4019475 # ITB hits +system.cpu.itb.fetch_misses 6849 # ITB misses +system.cpu.itb.fetch_acv 693 # ITB acv +system.cpu.itb.fetch_accesses 4026324 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,39 +336,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 175257245 # number of cpu cycles simulated +system.cpu.numCycles 180833283 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56122640 # Number of instructions committed -system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.122755 # CPI: cycles per instruction -system.cpu.ipc 0.320230 # IPC: instructions per cycle +system.cpu.committedInsts 56128524 # Number of instructions committed +system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.221772 # CPI: cycles per instruction +system.cpu.ipc 0.310388 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -415,115 +404,115 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192413 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192427 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 167 +system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395383 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36591764000 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4171 # number of times the context was actually changed +system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked +system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395325 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182732 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198999 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13390675 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13390675 # number of overall hits -system.cpu.dcache.overall_hits::total 13390675 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573763 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17288 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775403 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775403 # number of overall misses -system.cpu.dcache.overall_misses::total 1775403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51714049793 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15166078 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15166078 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117064 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117064 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25826.915091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36041.702834 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815437 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13392432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392432 # number of overall hits +system.cpu.dcache.overall_hits::total 13392432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1774788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1774788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1774788 # number of overall misses +system.cpu.dcache.overall_misses::total 1774788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999838250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32999838250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55461434302 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55461434302 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55461434302 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55461434302 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.641805 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.641805 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39182.965957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39182.965957 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31249.610828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31249.610828 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,64 +521,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks -system.cpu.dcache.writebacks::total 838265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127268 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269487 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838171 # 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number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086416 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # 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number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018255500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085964 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085964 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 # 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number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17111152616 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17111152616 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17111152616 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071489 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071489 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071489 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3221270000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60215.531385 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52608.159389 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 76588 # number of writebacks +system.cpu.l2cache.writebacks::total 76588 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16444 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405312 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116961750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343103250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460065000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500878889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500878889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116961750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843982139 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24960943889 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116961750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843982139 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24960943889 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893208000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893208000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67925.185478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.585100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.867828 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.024045 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.024045 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -861,42 +850,42 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41944 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6582654 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030876 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236451932 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41987 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3735584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011181 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41766 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3735584 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698164499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193277658 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -969,23 +958,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242093194 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -999,14 +988,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1023,19 +1012,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.305278 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1049,14 +1038,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1065,61 +1054,61 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295774 # Transaction distribution -system.membus.trans_dist::ReadResp 295758 # Transaction distribution +system.membus.trans_dist::ReadReq 295757 # Transaction distribution +system.membus.trans_dist::ReadResp 295741 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118154 # Transaction distribution +system.membus.trans_dist::Writeback 118100 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 116537 # Transaction distribution -system.membus.trans_dist::ReadExResp 116537 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116519 # Transaction distribution +system.membus.trans_dist::ReadExResp 116519 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886945 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565243 # Request fanout histogram +system.membus.snoop_fanout::samples 565206 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565243 # Request fanout histogram -system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 565206 # Request fanout histogram +system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 38c6e11f9..24a65d69d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901175 # Number of seconds simulated -sim_ticks 1901175003500 # Number of ticks simulated -final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904438 # Number of seconds simulated +sim_ticks 1904437574000 # Number of ticks simulated +final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154934 # Simulator instruction rate (inst/s) -host_op_rate 154934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5197600055 # Simulator tick rate (ticks/s) -host_mem_usage 378544 # Number of bytes of host memory used -host_seconds 365.78 # Real time elapsed on the host -sim_insts 56671579 # Number of instructions simulated -sim_ops 56671579 # Number of ops (including micro ops) simulated +host_inst_rate 150033 # Simulator instruction rate (inst/s) +host_op_rate 150033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5049661741 # Simulator tick rate (ticks/s) +host_mem_usage 379720 # Number of bytes of host memory used +host_seconds 377.14 # Real time elapsed on the host +sim_insts 56583768 # Number of instructions simulated +sim_ops 56583768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory +system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410534 # Number of read requests accepted -system.physmem.writeReqs 164756 # Number of write requests accepted -system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue -system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25742 # Per bank write bursts -system.physmem.perBankRdBursts::1 25822 # Per bank write bursts -system.physmem.perBankRdBursts::2 25939 # Per bank write bursts -system.physmem.perBankRdBursts::3 25643 # Per bank write bursts -system.physmem.perBankRdBursts::4 25873 # Per bank write bursts -system.physmem.perBankRdBursts::5 25657 # Per bank write bursts -system.physmem.perBankRdBursts::6 25709 # Per bank write bursts -system.physmem.perBankRdBursts::7 25201 # Per bank write bursts -system.physmem.perBankRdBursts::8 25222 # Per bank write bursts -system.physmem.perBankRdBursts::9 26115 # Per bank write bursts -system.physmem.perBankRdBursts::10 25677 # Per bank write bursts -system.physmem.perBankRdBursts::11 25575 # Per bank write bursts -system.physmem.perBankRdBursts::12 25800 # Per bank write bursts -system.physmem.perBankRdBursts::13 26085 # Per bank write bursts -system.physmem.perBankRdBursts::14 25301 # Per bank write bursts -system.physmem.perBankRdBursts::15 25075 # Per bank write bursts -system.physmem.perBankWrBursts::0 10194 # Per bank write bursts -system.physmem.perBankWrBursts::1 10103 # Per bank write bursts -system.physmem.perBankWrBursts::2 10030 # Per bank write bursts -system.physmem.perBankWrBursts::3 9736 # Per bank write bursts -system.physmem.perBankWrBursts::4 9490 # Per bank write bursts -system.physmem.perBankWrBursts::5 10167 # Per bank write bursts -system.physmem.perBankWrBursts::6 10200 # Per bank write bursts -system.physmem.perBankWrBursts::7 9338 # Per bank write bursts -system.physmem.perBankWrBursts::8 9741 # Per bank write bursts -system.physmem.perBankWrBursts::9 10459 # Per bank write bursts -system.physmem.perBankWrBursts::10 10157 # Per bank write bursts -system.physmem.perBankWrBursts::11 10688 # Per bank write bursts -system.physmem.perBankWrBursts::12 11170 # Per bank write bursts -system.physmem.perBankWrBursts::13 11200 # Per bank write bursts -system.physmem.perBankWrBursts::14 10147 # Per bank write bursts -system.physmem.perBankWrBursts::15 9577 # Per bank write bursts +system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412410 # Number of read requests accepted +system.physmem.writeReqs 166296 # Number of write requests accepted +system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25681 # Per bank write bursts +system.physmem.perBankRdBursts::1 26031 # Per bank write bursts +system.physmem.perBankRdBursts::2 26262 # Per bank write bursts +system.physmem.perBankRdBursts::3 25929 # Per bank write bursts +system.physmem.perBankRdBursts::4 25778 # Per bank write bursts +system.physmem.perBankRdBursts::5 25597 # Per bank write bursts +system.physmem.perBankRdBursts::6 26273 # Per bank write bursts +system.physmem.perBankRdBursts::7 25295 # Per bank write bursts +system.physmem.perBankRdBursts::8 25970 # Per bank write bursts +system.physmem.perBankRdBursts::9 26150 # Per bank write bursts +system.physmem.perBankRdBursts::10 25721 # Per bank write bursts +system.physmem.perBankRdBursts::11 25208 # Per bank write bursts +system.physmem.perBankRdBursts::12 25640 # Per bank write bursts +system.physmem.perBankRdBursts::13 25768 # Per bank write bursts +system.physmem.perBankRdBursts::14 25547 # Per bank write bursts +system.physmem.perBankRdBursts::15 25457 # Per bank write bursts +system.physmem.perBankWrBursts::0 9358 # Per bank write bursts +system.physmem.perBankWrBursts::1 9077 # Per bank write bursts +system.physmem.perBankWrBursts::2 9200 # Per bank write bursts +system.physmem.perBankWrBursts::3 8756 # Per bank write bursts +system.physmem.perBankWrBursts::4 8419 # Per bank write bursts +system.physmem.perBankWrBursts::5 8251 # Per bank write bursts +system.physmem.perBankWrBursts::6 9072 # Per bank write bursts +system.physmem.perBankWrBursts::7 8046 # Per bank write bursts +system.physmem.perBankWrBursts::8 8692 # Per bank write bursts +system.physmem.perBankWrBursts::9 8978 # Per bank write bursts +system.physmem.perBankWrBursts::10 8574 # Per bank write bursts +system.physmem.perBankWrBursts::11 8968 # Per bank write bursts +system.physmem.perBankWrBursts::12 8555 # Per bank write bursts +system.physmem.perBankWrBursts::13 9260 # Per bank write bursts +system.physmem.perBankWrBursts::14 8896 # Per bank write bursts +system.physmem.perBankWrBursts::15 8762 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1901170614000 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 1904433039500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410534 # Read request sizes (log2) +system.physmem.readPktSize::6 412410 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164756 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 166296 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,193 +158,200 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads -system.physmem.totQLat 3885054500 # Total ticks spent queuing -system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads +system.physmem.totQLat 4111304500 # Total ticks spent queuing +system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing -system.physmem.readRowHits 370181 # Number of row buffer hits during reads -system.physmem.writeRowHits 135448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes -system.physmem.avgGap 3304716.95 # Average gap between requests -system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.322456 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 371693 # Number of row buffer hits during reads +system.physmem.writeRowHits 115102 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes +system.physmem.avgGap 3290847.23 # Average gap between requests +system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.325620 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states +system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.329412 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states -system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.317995 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states +system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16131633 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits +system.cpu0.branchPred.lookups 16050181 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9231009 # DTB read hits -system.cpu0.dtb.read_misses 34580 # DTB read misses -system.cpu0.dtb.read_acv 535 # DTB read access violations -system.cpu0.dtb.read_accesses 687791 # DTB read accesses -system.cpu0.dtb.write_hits 5940395 # DTB write hits -system.cpu0.dtb.write_misses 7538 # DTB write misses -system.cpu0.dtb.write_acv 382 # DTB write access violations -system.cpu0.dtb.write_accesses 237219 # DTB write accesses -system.cpu0.dtb.data_hits 15171404 # DTB hits -system.cpu0.dtb.data_misses 42118 # DTB misses -system.cpu0.dtb.data_acv 917 # DTB access violations -system.cpu0.dtb.data_accesses 925010 # DTB accesses -system.cpu0.itb.fetch_hits 1435355 # ITB hits -system.cpu0.itb.fetch_misses 29386 # ITB misses -system.cpu0.itb.fetch_acv 625 # ITB acv -system.cpu0.itb.fetch_accesses 1464741 # ITB accesses +system.cpu0.dtb.read_hits 9185685 # DTB read hits +system.cpu0.dtb.read_misses 31794 # DTB read misses +system.cpu0.dtb.read_acv 464 # DTB read access violations +system.cpu0.dtb.read_accesses 674724 # DTB read accesses +system.cpu0.dtb.write_hits 5856177 # DTB write hits +system.cpu0.dtb.write_misses 6642 # DTB write misses +system.cpu0.dtb.write_acv 308 # DTB write access violations +system.cpu0.dtb.write_accesses 220970 # DTB write accesses +system.cpu0.dtb.data_hits 15041862 # DTB hits +system.cpu0.dtb.data_misses 38436 # DTB misses +system.cpu0.dtb.data_acv 772 # DTB access violations +system.cpu0.dtb.data_accesses 895694 # DTB accesses +system.cpu0.itb.fetch_hits 1413849 # ITB hits +system.cpu0.itb.fetch_misses 27924 # ITB misses +system.cpu0.itb.fetch_acv 522 # ITB acv +system.cpu0.itb.fetch_accesses 1441773 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -357,466 +364,465 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112944275 # number of cpu cycles simulated +system.cpu0.numCycles 115311619 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued -system.cpu0.iq.rate 0.465714 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued +system.cpu0.iq.rate 0.453068 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3408998 # number of nop insts executed -system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8273174 # Number of branches executed -system.cpu0.iew.exec_stores 5961648 # Number of stores executed -system.cpu0.iew.exec_rate 0.461213 # Inst execution rate -system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26436063 # num instructions producing a value -system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value +system.cpu0.iew.exec_nop 3391780 # number of nop insts executed +system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8225133 # Number of branches executed +system.cpu0.iew.exec_stores 5876205 # Number of stores executed +system.cpu0.iew.exec_rate 0.448685 # Inst execution rate +system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26435135 # num instructions producing a value +system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51697359 # Number of instructions committed -system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51332073 # Number of instructions committed +system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13959169 # Number of memory references committed -system.cpu0.commit.loads 8256071 # Number of loads committed -system.cpu0.commit.membars 200989 # Number of memory barriers committed -system.cpu0.commit.branches 7816314 # Number of branches committed -system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions. -system.cpu0.commit.function_calls 663768 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13832347 # Number of memory references committed +system.cpu0.commit.loads 8208434 # Number of loads committed +system.cpu0.commit.membars 200823 # Number of memory barriers committed +system.cpu0.commit.branches 7767218 # Number of branches committed +system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. +system.cpu0.commit.function_calls 660195 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 163161097 # The number of ROB reads -system.cpu0.rob.rob_writes 118660594 # The number of ROB writes -system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48729536 # Number of Instructions Simulated -system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads -system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes -system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads -system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads -system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1291740 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits -system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses -system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked +system.cpu0.rob.rob_reads 165216916 # The number of ROB reads +system.cpu0.rob.rob_writes 117798939 # The number of ROB writes +system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48375955 # Number of Instructions Simulated +system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads +system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes +system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads +system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads +system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1283357 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits +system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses +system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks -system.cpu0.dcache.writebacks::total 762456 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2106130 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1021422 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1021422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 267761 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 267761 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16114 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16114 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2626 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2626 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1289183 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1289183 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1289183 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1289183 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27591103326 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27591103326 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11693886534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11693886534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178834256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178834256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14183619 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14183619 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39284989860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094326 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5401.225819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5401.225819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks +system.cpu0.dcache.writebacks::total 752753 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # 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average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 911417 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # 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miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 197 # 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average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3410499 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits +system.cpu1.branchPred.lookups 3445639 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1800297 # DTB read hits -system.cpu1.dtb.read_misses 9623 # DTB read misses -system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 290908 # DTB read accesses -system.cpu1.dtb.write_hits 1120103 # DTB write hits -system.cpu1.dtb.write_misses 2035 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 109629 # DTB write accesses -system.cpu1.dtb.data_hits 2920400 # DTB hits -system.cpu1.dtb.data_misses 11658 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 400537 # DTB accesses -system.cpu1.itb.fetch_hits 513208 # ITB hits -system.cpu1.itb.fetch_misses 5417 # ITB misses -system.cpu1.itb.fetch_acv 59 # ITB acv -system.cpu1.itb.fetch_accesses 518625 # ITB accesses +system.cpu1.dtb.read_hits 1858276 # DTB read hits +system.cpu1.dtb.read_misses 10905 # DTB read misses +system.cpu1.dtb.read_acv 64 # DTB read access violations +system.cpu1.dtb.read_accesses 300263 # DTB read accesses +system.cpu1.dtb.write_hits 1193771 # DTB write hits +system.cpu1.dtb.write_misses 2902 # DTB write misses +system.cpu1.dtb.write_acv 104 # DTB write access violations +system.cpu1.dtb.write_accesses 125157 # DTB write accesses +system.cpu1.dtb.data_hits 3052047 # DTB hits +system.cpu1.dtb.data_misses 13807 # DTB misses +system.cpu1.dtb.data_acv 168 # DTB access violations +system.cpu1.dtb.data_accesses 425420 # DTB accesses +system.cpu1.itb.fetch_hits 529068 # ITB hits +system.cpu1.itb.fetch_misses 7485 # ITB misses +system.cpu1.itb.fetch_acv 158 # ITB acv +system.cpu1.itb.fetch_accesses 536553 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -956,463 +960,467 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 13834996 # number of cpu cycles simulated +system.cpu1.numCycles 14296923 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued -system.cpu1.iq.rate 0.630763 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued +system.cpu1.iq.rate 0.633233 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 494140 # number of nop insts executed -system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1279494 # Number of branches executed -system.cpu1.iew.exec_stores 1127581 # Number of stores executed -system.cpu1.iew.exec_rate 0.622051 # Inst execution rate -system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4051784 # num instructions producing a value -system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value +system.cpu1.iew.exec_nop 503606 # number of nop insts executed +system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1318456 # Number of branches executed +system.cpu1.iew.exec_stores 1202277 # Number of stores executed +system.cpu1.iew.exec_rate 0.624860 # Inst execution rate +system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4148200 # num instructions producing a value +system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8342954 # Number of instructions committed -system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8615735 # Number of instructions committed +system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2660112 # Number of memory references committed -system.cpu1.commit.loads 1593766 # Number of loads committed -system.cpu1.commit.membars 39768 # Number of memory barriers committed -system.cpu1.commit.branches 1189273 # Number of branches committed -system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions. -system.cpu1.commit.function_calls 132492 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2763276 # Number of memory references committed +system.cpu1.commit.loads 1626761 # Number of loads committed +system.cpu1.commit.membars 39485 # Number of memory barriers committed +system.cpu1.commit.branches 1225974 # Number of branches committed +system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. +system.cpu1.commit.function_calls 135018 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction -system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction +system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22401053 # The number of ROB reads -system.cpu1.rob.rob_writes 19972727 # The number of ROB writes -system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7942043 # Number of Instructions Simulated -system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads -system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes -system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads -system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes -system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads -system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 93396 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits -system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses -system.cpu1.dcache.overall_misses::total 362184 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 23176968 # The number of ROB reads +system.cpu1.rob.rob_writes 20704388 # The number of ROB writes +system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8207813 # Number of Instructions Simulated +system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads +system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes +system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes +system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads +system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 102439 # number of replacements +system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits +system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses +system.cpu1.dcache.overall_misses::total 425658 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks -system.cpu1.dcache.writebacks::total 60059 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks +system.cpu1.dcache.writebacks::total 70134 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1420,95 +1428,97 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 205003 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits -system.cpu1.icache.overall_hits::total 1269898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses -system.cpu1.icache.overall_misses::total 212310 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 211356 # number of replacements +system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits +system.cpu1.icache.overall_hits::total 1331062 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses +system.cpu1.icache.overall_misses::total 219986 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1522,58 +1532,58 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 54536 # Transaction distribution -system.iobus.trans_dist::WriteResp 12984 # Transaction distribution +system.iobus.trans_dist::ReadReq 7375 # Transaction distribution +system.iobus.trans_dist::ReadResp 7375 # Transaction distribution +system.iobus.trans_dist::WriteReq 54477 # Transaction distribution +system.iobus.trans_dist::WriteResp 12925 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1581,52 +1591,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41701 # number of replacements -system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375597 # Number of tag accesses -system.iocache.tags.data_accesses 375597 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses -system.iocache.ReadReq_misses::total 181 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses -system.iocache.demand_misses::total 181 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 181 # number of overall misses -system.iocache.overall_misses::total 181 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses +system.iocache.demand_misses::total 178 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 178 # number of overall misses +system.iocache.overall_misses::total 178 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1635,40 +1645,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1677,189 +1687,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345072 # number of replacements -system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use -system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53609.898857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5305.766317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6049.152476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 209.737010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 62.641613 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818022 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080960 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.092303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5798 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5210 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51300 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993744 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27343076 # Number of tag accesses -system.l2c.tags.data_accesses 27343076 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 901250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 743094 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 204045 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 62863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1911252 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822515 # number of Writeback hits -system.l2c.Writeback_hits::total 822515 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 236 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 410 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 50 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 157590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 21227 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178817 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 901250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 900684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 204045 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1997,101 +2007,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296649 # Transaction distribution -system.membus.trans_dist::ReadResp 296568 # Transaction distribution -system.membus.trans_dist::WriteReq 12984 # Transaction distribution -system.membus.trans_dist::WriteResp 12984 # Transaction distribution -system.membus.trans_dist::Writeback 123204 # Transaction distribution +system.membus.trans_dist::ReadReq 296650 # Transaction distribution +system.membus.trans_dist::ReadResp 296572 # Transaction distribution +system.membus.trans_dist::WriteReq 12925 # Transaction distribution +system.membus.trans_dist::WriteResp 12925 # Transaction distribution +system.membus.trans_dist::Writeback 124744 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution -system.membus.trans_dist::ReadExReq 121989 # Transaction distribution -system.membus.trans_dist::ReadExResp 121610 # Transaction distribution -system.membus.trans_dist::BadAddressError 81 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution +system.membus.trans_dist::ReadExReq 123808 # Transaction distribution +system.membus.trans_dist::ReadExResp 123481 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10884 # Total snoops (count) -system.membus.snoop_fanout::samples 591178 # Request fanout histogram +system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10437 # Total snoops (count) +system.membus.snoop_fanout::samples 594010 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 591178 # Request fanout histogram -system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 594010 # Request fanout histogram +system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 73699 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 72565 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2125,161 +2135,171 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 232 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed +system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed -system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170980 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches +system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed +system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed +system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170714 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1354 -system.cpu0.kern.mode_good::user 1355 +system.cpu0.kern.mode_good::kernel 1181 +system.cpu0.kern.mode_good::user 1181 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3574 # number of times the context was actually changed +system.cpu0.kern.swap_context 3503 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed -system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed -system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 94 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed +system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed +system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed +system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 111 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed +system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed +system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed +system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46833 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches -system.cpu1.kern.mode_switch::user 384 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 574 -system.cpu1.kern.mode_good::user 384 -system.cpu1.kern.mode_good::idle 190 -system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 46904 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches +system.cpu1.kern.mode_switch::user 554 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 733 +system.cpu1.kern.mode_good::user 554 +system.cpu1.kern.mode_good::idle 179 +system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 990 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1024 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index aba3b9944..12a10aeec 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859045 # Number of seconds simulated -sim_ticks 1859045389000 # Number of ticks simulated -final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.861006 # Number of seconds simulated +sim_ticks 1861005569500 # Number of ticks simulated +final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155751 # Simulator instruction rate (inst/s) -host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5470499619 # Simulator tick rate (ticks/s) -host_mem_usage 374716 # Number of bytes of host memory used -host_seconds 339.83 # Real time elapsed on the host -sim_insts 52929026 # Number of instructions simulated -sim_ops 52929026 # Number of ops (including micro ops) simulated +host_inst_rate 153218 # Simulator instruction rate (inst/s) +host_op_rate 153218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5386630373 # Simulator tick rate (ticks/s) +host_mem_usage 376136 # Number of bytes of host memory used +host_seconds 345.49 # Real time elapsed on the host +sim_insts 52934565 # Number of instructions simulated +sim_ops 52934565 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403836 # Number of read requests accepted -system.physmem.writeReqs 159002 # Number of write requests accepted -system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25744 # Per bank write bursts -system.physmem.perBankRdBursts::1 25557 # Per bank write bursts -system.physmem.perBankRdBursts::2 25510 # Per bank write bursts -system.physmem.perBankRdBursts::3 25348 # Per bank write bursts -system.physmem.perBankRdBursts::4 25387 # Per bank write bursts -system.physmem.perBankRdBursts::5 24799 # Per bank write bursts +system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403841 # Number of read requests accepted +system.physmem.writeReqs 159009 # Number of write requests accepted +system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue +system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25748 # Per bank write bursts +system.physmem.perBankRdBursts::1 25559 # Per bank write bursts +system.physmem.perBankRdBursts::2 25508 # Per bank write bursts +system.physmem.perBankRdBursts::3 25346 # Per bank write bursts +system.physmem.perBankRdBursts::4 25393 # Per bank write bursts +system.physmem.perBankRdBursts::5 24806 # Per bank write bursts system.physmem.perBankRdBursts::6 25027 # Per bank write bursts -system.physmem.perBankRdBursts::7 25129 # Per bank write bursts -system.physmem.perBankRdBursts::8 24928 # Per bank write bursts -system.physmem.perBankRdBursts::9 25032 # Per bank write bursts +system.physmem.perBankRdBursts::7 25127 # Per bank write bursts +system.physmem.perBankRdBursts::8 24925 # Per bank write bursts +system.physmem.perBankRdBursts::9 25034 # Per bank write bursts system.physmem.perBankRdBursts::10 25436 # Per bank write bursts -system.physmem.perBankRdBursts::11 24784 # Per bank write bursts +system.physmem.perBankRdBursts::11 24774 # Per bank write bursts system.physmem.perBankRdBursts::12 24551 # Per bank write bursts -system.physmem.perBankRdBursts::13 25235 # Per bank write bursts -system.physmem.perBankRdBursts::14 25659 # Per bank write bursts -system.physmem.perBankRdBursts::15 25606 # Per bank write bursts -system.physmem.perBankWrBursts::0 10485 # Per bank write bursts -system.physmem.perBankWrBursts::1 10108 # Per bank write bursts -system.physmem.perBankWrBursts::2 10574 # Per bank write bursts -system.physmem.perBankWrBursts::3 9632 # Per bank write bursts -system.physmem.perBankWrBursts::4 9668 # Per bank write bursts -system.physmem.perBankWrBursts::5 9137 # Per bank write bursts -system.physmem.perBankWrBursts::6 9064 # Per bank write bursts -system.physmem.perBankWrBursts::7 8900 # Per bank write bursts -system.physmem.perBankWrBursts::8 9821 # Per bank write bursts -system.physmem.perBankWrBursts::9 8750 # Per bank write bursts -system.physmem.perBankWrBursts::10 9677 # Per bank write bursts -system.physmem.perBankWrBursts::11 9460 # Per bank write bursts -system.physmem.perBankWrBursts::12 10019 # Per bank write bursts -system.physmem.perBankWrBursts::13 10709 # Per bank write bursts -system.physmem.perBankWrBursts::14 10502 # Per bank write bursts -system.physmem.perBankWrBursts::15 10405 # Per bank write bursts +system.physmem.perBankRdBursts::13 25233 # Per bank write bursts +system.physmem.perBankRdBursts::14 25663 # Per bank write bursts +system.physmem.perBankRdBursts::15 25612 # Per bank write bursts +system.physmem.perBankWrBursts::0 9148 # Per bank write bursts +system.physmem.perBankWrBursts::1 8514 # Per bank write bursts +system.physmem.perBankWrBursts::2 8998 # Per bank write bursts +system.physmem.perBankWrBursts::3 8298 # Per bank write bursts +system.physmem.perBankWrBursts::4 8214 # Per bank write bursts +system.physmem.perBankWrBursts::5 7705 # Per bank write bursts +system.physmem.perBankWrBursts::6 7696 # Per bank write bursts +system.physmem.perBankWrBursts::7 7707 # Per bank write bursts +system.physmem.perBankWrBursts::8 8055 # Per bank write bursts +system.physmem.perBankWrBursts::9 7602 # Per bank write bursts +system.physmem.perBankWrBursts::10 8149 # Per bank write bursts +system.physmem.perBankWrBursts::11 7799 # Per bank write bursts +system.physmem.perBankWrBursts::12 8377 # Per bank write bursts +system.physmem.perBankWrBursts::13 9062 # Per bank write bursts +system.physmem.perBankWrBursts::14 8903 # Per bank write bursts +system.physmem.perBankWrBursts::15 8889 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1859040142000 # Total gap between requests +system.physmem.numWrRetry 85 # Number of times write queue was full causing retry +system.physmem.totGap 1861000236500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403836 # Read request sizes (log2) +system.physmem.readPktSize::6 403841 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159002 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159009 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -148,193 +148,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads -system.physmem.totQLat 3621320000 # Total ticks spent queuing -system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads +system.physmem.totQLat 3741903500 # Total ticks spent queuing +system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364717 # Number of row buffer hits during reads -system.physmem.writeRowHits 132230 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes -system.physmem.avgGap 3302975.53 # Average gap between requests -system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.311493 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states -system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing +system.physmem.readRowHits 364326 # Number of row buffer hits during reads +system.physmem.writeRowHits 109846 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes +system.physmem.avgGap 3306387.56 # Average gap between requests +system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.297807 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states +system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.308507 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states -system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.286901 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states +system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17755011 # Number of BP lookups -system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits +system.cpu.branchPred.lookups 17721924 # Number of BP lookups +system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10297861 # DTB read hits -system.cpu.dtb.read_misses 41459 # DTB read misses -system.cpu.dtb.read_acv 502 # DTB read access violations -system.cpu.dtb.read_accesses 968382 # DTB read accesses -system.cpu.dtb.write_hits 6648165 # DTB write hits -system.cpu.dtb.write_misses 9537 # DTB write misses -system.cpu.dtb.write_acv 407 # DTB write access violations -system.cpu.dtb.write_accesses 342637 # DTB write accesses -system.cpu.dtb.data_hits 16946026 # DTB hits -system.cpu.dtb.data_misses 50996 # DTB misses +system.cpu.dtb.read_hits 10269214 # DTB read hits +system.cpu.dtb.read_misses 41261 # DTB read misses +system.cpu.dtb.read_acv 507 # DTB read access violations +system.cpu.dtb.read_accesses 967301 # DTB read accesses +system.cpu.dtb.write_hits 6648637 # DTB write hits +system.cpu.dtb.write_misses 9303 # DTB write misses +system.cpu.dtb.write_acv 402 # DTB write access violations +system.cpu.dtb.write_accesses 342644 # DTB write accesses +system.cpu.dtb.data_hits 16917851 # DTB hits +system.cpu.dtb.data_misses 50564 # DTB misses system.cpu.dtb.data_acv 909 # DTB access violations -system.cpu.dtb.data_accesses 1311019 # DTB accesses -system.cpu.itb.fetch_hits 1769037 # ITB hits -system.cpu.itb.fetch_misses 35976 # ITB misses -system.cpu.itb.fetch_acv 675 # ITB acv -system.cpu.itb.fetch_accesses 1805013 # ITB accesses +system.cpu.dtb.data_accesses 1309945 # DTB accesses +system.cpu.itb.fetch_hits 1769158 # ITB hits +system.cpu.itb.fetch_misses 36068 # ITB misses +system.cpu.itb.fetch_acv 660 # ITB acv +system.cpu.itb.fetch_accesses 1805226 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,254 +353,253 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118253854 # number of cpu cycles simulated +system.cpu.numCycles 122572361 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7497440 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued -system.cpu.iq.rate 0.486545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued +system.cpu.iq.rate 0.469435 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67941522 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334790 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3696550 # number of nop insts executed -system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed -system.cpu.iew.exec_branches 8972525 # Number of branches executed -system.cpu.iew.exec_stores 6672811 # Number of stores executed -system.cpu.iew.exec_rate 0.481583 # Inst execution rate -system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28889312 # num instructions producing a value -system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value +system.cpu.iew.exec_nop 3706829 # number of nop insts executed +system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed +system.cpu.iew.exec_branches 8976912 # Number of branches executed +system.cpu.iew.exec_stores 6673045 # Number of stores executed +system.cpu.iew.exec_rate 0.464599 # Inst execution rate +system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28792537 # num instructions producing a value +system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56117715 # Number of instructions committed -system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56123349 # Number of instructions committed +system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458158 # Number of memory references committed -system.cpu.commit.loads 9084456 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8434758 # Number of branches committed +system.cpu.commit.refs 15459994 # Number of memory references committed +system.cpu.commit.loads 9085408 # Number of loads committed +system.cpu.commit.membars 226308 # Number of memory barriers committed +system.cpu.commit.branches 8435685 # Number of branches committed system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. -system.cpu.commit.function_calls 739915 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction +system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. +system.cpu.commit.function_calls 740049 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction @@ -622,192 +627,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction -system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction +system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173330307 # The number of ROB reads -system.cpu.rob.rob_writes 129976168 # The number of ROB writes -system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52929026 # Number of Instructions Simulated -system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74582639 # number of integer regfile reads -system.cpu.int_regfile_writes 40531859 # number of integer regfile writes -system.cpu.fp_regfile_reads 167323 # number of floating regfile reads -system.cpu.fp_regfile_writes 167888 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads -system.cpu.misc_regfile_writes 939419 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404198 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 177593269 # The number of ROB reads +system.cpu.rob.rob_writes 130137832 # The number of ROB writes +system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52934565 # Number of Instructions Simulated +system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads +system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74599299 # number of integer regfile reads +system.cpu.int_regfile_writes 40560409 # number of integer regfile writes +system.cpu.fp_regfile_reads 167171 # number of floating regfile reads +system.cpu.fp_regfile_writes 167579 # number of floating regfile writes +system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads +system.cpu.misc_regfile_writes 939349 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1403663 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits -system.cpu.dcache.overall_hits::total 11473712 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses -system.cpu.dcache.overall_misses::total 3729145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits +system.cpu.dcache.overall_hits::total 11456366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses +system.cpu.dcache.overall_misses::total 3751566 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks -system.cpu.dcache.writebacks::total 842396 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # 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number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # 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average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,80 +1035,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks -system.cpu.l2cache.writebacks::total 75938 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks +system.cpu.l2cache.writebacks::total 75945 # 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number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # 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average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1111,43 +1116,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42071 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42097 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1220,23 +1225,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1250,14 +1255,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1274,19 +1279,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1300,14 +1305,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1316,62 +1321,62 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296054 # Transaction distribution -system.membus.trans_dist::ReadResp 295968 # Transaction distribution +system.membus.trans_dist::ReadReq 296160 # Transaction distribution +system.membus.trans_dist::ReadResp 296066 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117450 # Transaction distribution +system.membus.trans_dist::Writeback 117457 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 203 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 211 # Transaction distribution -system.membus.trans_dist::ReadExReq 115230 # Transaction distribution -system.membus.trans_dist::ReadExResp 115230 # Transaction distribution -system.membus.trans_dist::BadAddressError 86 # Transaction distribution +system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 190 # Transaction distribution +system.membus.trans_dist::ReadExReq 115137 # Transaction distribution +system.membus.trans_dist::ReadExResp 115137 # Transaction distribution +system.membus.trans_dist::BadAddressError 94 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563568 # Request fanout histogram +system.membus.snoop_fanout::samples 563651 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563568 # Request fanout histogram -system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 563651 # Request fanout histogram +system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1405,28 +1410,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1465,7 +1470,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1474,20 +1479,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191962 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 191942 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index b0cdac391..43a4f79aa 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842591955000 # Number of ticks simulated -final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841539 # Number of seconds simulated +sim_ticks 1841538755500 # Number of ticks simulated +final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212167 # Simulator instruction rate (inst/s) -host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5858461865 # Simulator tick rate (ticks/s) -host_mem_usage 373744 # Number of bytes of host memory used -host_seconds 314.52 # Real time elapsed on the host -sim_insts 66730424 # Number of instructions simulated -sim_ops 66730424 # Number of ops (including micro ops) simulated +host_inst_rate 221552 # Simulator instruction rate (inst/s) +host_op_rate 221552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5785089232 # Simulator tick rate (ticks/s) +host_mem_usage 374344 # Number of bytes of host memory used +host_seconds 318.33 # Real time elapsed on the host +sim_insts 70525499 # Number of instructions simulated +sim_ops 70525499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 467648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20091072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2148032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 308096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2634304 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25797120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 467648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 308096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 922752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41161 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403080 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 253944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1166433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 167304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1430491 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14008459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 253944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 167304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 501077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4062828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 253944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1166433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 167304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1430491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81945 # Number of read requests accepted -system.physmem.writeReqs 62218 # Number of write requests accepted -system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue -system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5216 # Per bank write bursts -system.physmem.perBankRdBursts::1 4952 # Per bank write bursts -system.physmem.perBankRdBursts::2 4966 # Per bank write bursts -system.physmem.perBankRdBursts::3 5032 # Per bank write bursts -system.physmem.perBankRdBursts::4 5011 # Per bank write bursts -system.physmem.perBankRdBursts::5 5077 # Per bank write bursts -system.physmem.perBankRdBursts::6 5139 # Per bank write bursts -system.physmem.perBankRdBursts::7 5153 # Per bank write bursts -system.physmem.perBankRdBursts::8 5336 # Per bank write bursts -system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5284 # Per bank write bursts -system.physmem.perBankRdBursts::11 5137 # Per bank write bursts -system.physmem.perBankRdBursts::12 4814 # Per bank write bursts -system.physmem.perBankRdBursts::13 5083 # Per bank write bursts -system.physmem.perBankRdBursts::14 5582 # Per bank write bursts -system.physmem.perBankRdBursts::15 5130 # Per bank write bursts -system.physmem.perBankWrBursts::0 3820 # Per bank write bursts -system.physmem.perBankWrBursts::1 3672 # Per bank write bursts -system.physmem.perBankWrBursts::2 3762 # Per bank write bursts -system.physmem.perBankWrBursts::3 4075 # Per bank write bursts -system.physmem.perBankWrBursts::4 3759 # Per bank write bursts -system.physmem.perBankWrBursts::5 3520 # Per bank write bursts -system.physmem.perBankWrBursts::6 4123 # Per bank write bursts -system.physmem.perBankWrBursts::7 3706 # Per bank write bursts -system.physmem.perBankWrBursts::8 4379 # Per bank write bursts -system.physmem.perBankWrBursts::9 3471 # Per bank write bursts -system.physmem.perBankWrBursts::10 3889 # Per bank write bursts -system.physmem.perBankWrBursts::11 3981 # Per bank write bursts -system.physmem.perBankWrBursts::12 3541 # Per bank write bursts -system.physmem.perBankWrBursts::13 3879 # Per bank write bursts -system.physmem.perBankWrBursts::14 4169 # Per bank write bursts -system.physmem.perBankWrBursts::15 3676 # Per bank write bursts +system.physmem.bw_total::total 18071287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81850 # Number of read requests accepted +system.physmem.writeReqs 64472 # Number of write requests accepted +system.physmem.readBursts 81850 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 64472 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5236928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1472 # Total number of bytes read from write queue +system.physmem.bytesWritten 3416192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5238400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4126208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 23 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11076 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4878 # Per bank write bursts +system.physmem.perBankRdBursts::1 4919 # Per bank write bursts +system.physmem.perBankRdBursts::2 4947 # Per bank write bursts +system.physmem.perBankRdBursts::3 4947 # Per bank write bursts +system.physmem.perBankRdBursts::4 5010 # Per bank write bursts +system.physmem.perBankRdBursts::5 5136 # Per bank write bursts +system.physmem.perBankRdBursts::6 5318 # Per bank write bursts +system.physmem.perBankRdBursts::7 5111 # Per bank write bursts +system.physmem.perBankRdBursts::8 5349 # Per bank write bursts +system.physmem.perBankRdBursts::9 4830 # Per bank write bursts +system.physmem.perBankRdBursts::10 5530 # Per bank write bursts +system.physmem.perBankRdBursts::11 5119 # Per bank write bursts +system.physmem.perBankRdBursts::12 4880 # Per bank write bursts +system.physmem.perBankRdBursts::13 5044 # Per bank write bursts +system.physmem.perBankRdBursts::14 5637 # Per bank write bursts +system.physmem.perBankRdBursts::15 5172 # Per bank write bursts +system.physmem.perBankWrBursts::0 3097 # Per bank write bursts +system.physmem.perBankWrBursts::1 3264 # Per bank write bursts +system.physmem.perBankWrBursts::2 3389 # Per bank write bursts +system.physmem.perBankWrBursts::3 3378 # Per bank write bursts +system.physmem.perBankWrBursts::4 3165 # Per bank write bursts +system.physmem.perBankWrBursts::5 3060 # Per bank write bursts +system.physmem.perBankWrBursts::6 3647 # Per bank write bursts +system.physmem.perBankWrBursts::7 3165 # Per bank write bursts +system.physmem.perBankWrBursts::8 3847 # Per bank write bursts +system.physmem.perBankWrBursts::9 3079 # Per bank write bursts +system.physmem.perBankWrBursts::10 3680 # Per bank write bursts +system.physmem.perBankWrBursts::11 3339 # Per bank write bursts +system.physmem.perBankWrBursts::12 2997 # Per bank write bursts +system.physmem.perBankWrBursts::13 3248 # Per bank write bursts +system.physmem.perBankWrBursts::14 3739 # Per bank write bursts +system.physmem.perBankWrBursts::15 3284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579678500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1840526879500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81945 # Read request sizes (log2) +system.physmem.readPktSize::6 81850 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62218 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64472 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -153,216 +153,196 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 38 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.924780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 222.627349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 384.024543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7145 32.28% 32.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4994 22.56% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1972 8.91% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1000 4.52% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 834 3.77% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 471 2.13% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 534 2.41% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 337 1.52% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4848 21.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22135 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 42.863279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1017.016663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1907 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads -system.physmem.totQLat 814366500 # Total ticks spent queuing -system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.961236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.965205 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.780578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 2.36% 2.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 1768 92.61% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 14 0.73% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 2 0.10% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 2 0.10% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 1 0.05% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 1 0.05% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 2 0.10% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.58% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.63% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 5 0.26% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 8 0.42% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 1 0.05% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.05% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.10% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.10% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.31% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 2 0.10% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.10% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.05% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.16% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 4 0.21% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1909 # Writes before turning the bus around for reads +system.physmem.totQLat 884680000 # Total ticks spent queuing +system.physmem.totMemAccLat 2418936250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10811.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29561.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70260 # Number of row buffer hits during reads -system.physmem.writeRowHits 50807 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes -system.physmem.avgGap 12774287.98 # Average gap between requests -system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.726630 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.99 # Average write queue length when enqueuing +system.physmem.readRowHits 70087 # Number of row buffer hits during reads +system.physmem.writeRowHits 42983 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes +system.physmem.avgGap 12578606.63 # Average gap between requests +system.physmem.pageHitRate 83.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81814320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44558250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314074800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 169549200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35647575705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 798651060750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923964608865 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.989912 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309028017250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9101184500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.972279 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states -system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.actEnergy 85526280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46513500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324175800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 176340240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35475772860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801505403250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926669707770 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.770193 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309231204000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8903896000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4841130 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3448228 # DTB write hits -system.cpu0.dtb.write_misses 688 # DTB write misses -system.cpu0.dtb.write_acv 85 # DTB write access violations -system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8289358 # DTB hits -system.cpu0.dtb.data_misses 6850 # DTB misses -system.cpu0.dtb.data_acv 211 # DTB access violations -system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2744473 # ITB hits -system.cpu0.itb.fetch_misses 3071 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2747544 # ITB accesses +system.cpu0.dtb.read_hits 4781172 # DTB read hits +system.cpu0.dtb.read_misses 6058 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 428328 # DTB read accesses +system.cpu0.dtb.write_hits 3391530 # DTB write hits +system.cpu0.dtb.write_misses 675 # DTB write misses +system.cpu0.dtb.write_acv 82 # DTB write access violations +system.cpu0.dtb.write_accesses 163639 # DTB write accesses +system.cpu0.dtb.data_hits 8172702 # DTB hits +system.cpu0.dtb.data_misses 6733 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 591967 # DTB accesses +system.cpu0.itb.fetch_hits 2720050 # ITB hits +system.cpu0.itb.fetch_misses 3046 # ITB misses +system.cpu0.itb.fetch_acv 99 # ITB acv +system.cpu0.itb.fetch_accesses 2723096 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -375,87 +355,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929111283 # number of cpu cycles simulated +system.cpu0.numCycles 930048733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30392058 # Number of instructions committed -system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses -system.cpu0.num_func_calls 800920 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28296981 # number of integer instructions -system.cpu0.num_fp_insts 165313 # number of float instructions -system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319320 # number of memory refs -system.cpu0.num_load_insts 4862427 # Number of load instructions -system.cpu0.num_store_insts 3456893 # Number of store instructions -system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles -system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles -system.cpu0.Branches 4712544 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction -system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction -system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction -system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31504183 # Number of instructions committed +system.cpu0.committedOps 31504183 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29439494 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162688 # Number of float alu accesses +system.cpu0.num_func_calls 792913 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4107229 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29439494 # number of integer instructions +system.cpu0.num_fp_insts 162688 # number of float instructions +system.cpu0.num_int_register_reads 41004383 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21582488 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84172 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85625 # number of times the floating registers were written +system.cpu0.num_mem_refs 8202083 # number of memory refs +system.cpu0.num_load_insts 4802046 # Number of load instructions +system.cpu0.num_store_insts 3400037 # Number of store instructions +system.cpu0.num_idle_cycles 907048310.649553 # Number of idle cycles +system.cpu0.num_busy_cycles 23000422.350447 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024730 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975270 # Percentage of idle cycles +system.cpu0.Branches 5154717 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1560474 4.95% 4.95% # Class of executed instruction +system.cpu0.op_class::IntAlu 21056937 66.82% 71.78% # Class of executed instruction +system.cpu0.op_class::IntMult 31354 0.10% 71.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12843 0.04% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1601 0.01% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::MemRead 4932088 15.65% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 3403118 10.80% 98.37% # Class of executed instruction +system.cpu0.op_class::IprAccess 512701 1.63% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30399119 # Class of executed instruction +system.cpu0.op_class::total 31511116 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211361 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182558 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818811073000 98.77% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38572000 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 355311500 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22333065000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841538021500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694801 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815834 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -491,278 +471,276 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175301 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192228 # number of callpals executed +system.cpu0.kern.callpal::total 192212 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1910 -system.cpu0.kern.mode_good::user 1740 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393017 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29730845000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2571229000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809235945500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1393219 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13266024 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393731 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.518353 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 178.252416 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.663502 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.081899 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.348149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.321608 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.330238 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63366474 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4014509 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1053432 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2506621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7574562 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3156846 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 808200 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357961 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5323007 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114880 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50813 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184484 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123743 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20765 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54820 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199328 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7171355 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1861632 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3864582 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12897569 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7171355 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1861632 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3864582 # number of overall hits -system.cpu0.dcache.overall_hits::total 12897569 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 713110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 94552 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 558128 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1365790 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166356 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43595 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 617033 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 826984 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9412 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2104 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7556 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19072 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 879466 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138147 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1175161 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2192774 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 879466 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138147 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1175161 # number of overall misses -system.cpu0.dcache.overall_misses::total 2192774 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193347250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9664547340 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11857894590 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1652894510 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19391335975 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21044230485 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27729500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125483249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 153212749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 91000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3846241760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 29055883315 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32902125075 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3846241760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 29055883315 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32902125075 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727619 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147984 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3064749 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8940352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3323202 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 851795 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124292 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20895 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203556 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123745 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20765 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54827 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199337 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8050821 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1999779 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5039743 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15090343 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8050821 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1999779 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5039743 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15090343 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150839 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082364 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182112 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050059 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051180 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312423 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.134469 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075725 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100694 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.129452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093694 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000128 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109239 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069081 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233179 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145310 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109239 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069081 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233179 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145310 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8682.077472 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 63377040 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63377040 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3961674 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1077685 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2542197 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7581556 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3105087 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 828848 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1366589 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5300524 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113741 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19662 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51148 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184551 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122328 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21764 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55225 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7066761 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1906533 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3908786 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12882080 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7066761 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1906533 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3908786 # number of overall hits +system.cpu0.dcache.overall_hits::total 12882080 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 706841 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 96965 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 557653 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1361459 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 162721 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 642629 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11086168542 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3795432990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7290735552 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11086168542 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 222473500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 331326000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 553799500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 293979000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 446199000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740178000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 516452500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 777525000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1293977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082548 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087131 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050408 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047670 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022729 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102034 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040445 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033581 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033581 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21811.633063 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15810.589349 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17395.873429 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38194.190418 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31534.830267 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33631.000823 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11726.355894 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11998.625916 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11924.863388 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15318 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15318 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # 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average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6716.906439 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2709 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43227698 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43227698 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31004099 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7794052 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2481801 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41279952 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31004099 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7794052 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2481801 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41279952 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31004099 # 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number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42262186 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016090 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016263 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122471 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023241 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016090 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016263 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122471 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023241 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016090 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016263 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122471 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023241 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14274.651139 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13970.038652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6798.836701 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6798.836701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6798.836701 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4002 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.705882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.786667 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16232 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16232 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16232 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16232 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16232 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16232 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124188 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326610 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 450798 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16722 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16722 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16722 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16722 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128848 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329647 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 458495 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128848 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 329647 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 458495 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128848 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 329647 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 458495 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1645092750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4148478396 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5793571146 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1645092750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4148478396 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5793571146 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1645092750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4148478396 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5793571146 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010849 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010849 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010849 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12636.061780 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166781 # DTB read hits -system.cpu1.dtb.read_misses 1314 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 872888 # DTB write hits -system.cpu1.dtb.write_misses 168 # DTB write misses +system.cpu1.dtb.read_hits 1194215 # DTB read hits +system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 141030 # DTB read accesses +system.cpu1.dtb.write_hits 894755 # DTB write hits +system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2039669 # DTB hits -system.cpu1.dtb.data_misses 1482 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 848090 # ITB hits -system.cpu1.itb.fetch_misses 662 # ITB misses -system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848752 # ITB accesses +system.cpu1.dtb.write_accesses 57515 # DTB write accesses +system.cpu1.dtb.data_hits 2088970 # DTB hits +system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 198545 # DTB accesses +system.cpu1.itb.fetch_hits 856400 # ITB hits +system.cpu1.itb.fetch_misses 653 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 857053 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -942,64 +920,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953408444 # number of cpu cycles simulated +system.cpu1.numCycles 953255662 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7454598 # Number of instructions committed -system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses -system.cpu1.num_func_calls 203515 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6929268 # number of integer instructions -system.cpu1.num_fp_insts 43953 # number of float instructions -system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written -system.cpu1.num_mem_refs 2046592 # number of memory refs -system.cpu1.num_load_insts 1171450 # Number of load instructions -system.cpu1.num_store_insts 875142 # Number of store instructions -system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles -system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles -system.cpu1.Branches 1171881 # Number of branches fetched -system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction -system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7921357 # Number of instructions committed +system.cpu1.committedOps 7921357 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7380748 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45896 # Number of float alu accesses +system.cpu1.num_func_calls 207012 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1022630 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7380748 # number of integer instructions +system.cpu1.num_fp_insts 45896 # number of float instructions +system.cpu1.num_int_register_reads 10351742 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5363285 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24726 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written +system.cpu1.num_mem_refs 2096070 # number of memory refs +system.cpu1.num_load_insts 1198996 # Number of load instructions +system.cpu1.num_store_insts 897074 # Number of store instructions +system.cpu1.num_idle_cycles 923177922.874727 # Number of idle cycles +system.cpu1.num_busy_cycles 30077739.125273 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031553 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968447 # Percentage of idle cycles +system.cpu1.Branches 1296149 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410448 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5236817 66.10% 71.28% # Class of executed instruction +system.cpu1.op_class::IntMult 8727 0.11% 71.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.39% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5162 0.07% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::MemRead 1228055 15.50% 86.96% # Class of executed instruction +system.cpu1.op_class::MemWrite 898300 11.34% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134580 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7456136 # Class of executed instruction +system.cpu1.op_class::total 7922899 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1017,35 +995,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9673449 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits +system.cpu2.branchPred.lookups 10412478 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9668294 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 126557 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8251745 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6275895 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 76.055368 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 302998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7851 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3461968 # DTB read hits -system.cpu2.dtb.read_misses 12174 # DTB read misses -system.cpu2.dtb.read_acv 114 # DTB read access violations -system.cpu2.dtb.read_accesses 224881 # DTB read accesses -system.cpu2.dtb.write_hits 2122047 # DTB write hits -system.cpu2.dtb.write_misses 2563 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 83942 # DTB write accesses -system.cpu2.dtb.data_hits 5584015 # DTB hits -system.cpu2.dtb.data_misses 14737 # DTB misses -system.cpu2.dtb.data_acv 220 # DTB access violations -system.cpu2.dtb.data_accesses 308823 # DTB accesses -system.cpu2.itb.fetch_hits 534012 # ITB hits -system.cpu2.itb.fetch_misses 5788 # ITB misses -system.cpu2.itb.fetch_acv 158 # ITB acv -system.cpu2.itb.fetch_accesses 539800 # ITB accesses +system.cpu2.dtb.read_hits 3529660 # DTB read hits +system.cpu2.dtb.read_misses 12347 # DTB read misses +system.cpu2.dtb.read_acv 141 # DTB read access violations +system.cpu2.dtb.read_accesses 225697 # DTB read accesses +system.cpu2.dtb.write_hits 2155841 # DTB write hits +system.cpu2.dtb.write_misses 2820 # DTB write misses +system.cpu2.dtb.write_acv 143 # DTB write access violations +system.cpu2.dtb.write_accesses 84900 # DTB write accesses +system.cpu2.dtb.data_hits 5685501 # DTB hits +system.cpu2.dtb.data_misses 15167 # DTB misses +system.cpu2.dtb.data_acv 284 # DTB access violations +system.cpu2.dtb.data_accesses 310597 # DTB accesses +system.cpu2.itb.fetch_hits 538073 # ITB hits +system.cpu2.itb.fetch_misses 5955 # ITB misses +system.cpu2.itb.fetch_acv 169 # ITB acv +system.cpu2.itb.fetch_accesses 544028 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1058,305 +1036,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30013580 # number of cpu cycles simulated +system.cpu2.numCycles 30702821 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9319148 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 39738878 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10412478 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6578893 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 19243837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 412304 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 656 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 233877 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 108804 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2828172 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93139 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.364460 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.368556 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20002999 68.68% 68.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 306830 1.05% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 477568 1.64% 71.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4658363 15.99% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 855343 2.94% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 200502 0.69% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 234860 0.81% 91.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433547 1.49% 93.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1954244 6.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.339138 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.294307 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7666487 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12991565 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7744961 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 527663 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 193001 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 177358 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13514 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36364188 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 193001 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7942048 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4601261 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6305683 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7969678 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2112012 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35538074 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 62867 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 396006 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 59218 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1045972 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23773076 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44310063 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44249815 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56335 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21846032 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1927044 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 532665 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63556 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3796199 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3529311 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2248768 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 470664 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 333419 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32987424 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2457717 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.121642 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.623821 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17381860 59.68% 59.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2746661 9.43% 69.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1371662 4.71% 73.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5386342 18.49% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1029310 3.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 605779 2.08% 97.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 390861 1.34% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 167562 0.58% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44219 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 29124256 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85214 22.02% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179569 46.41% 68.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 122132 31.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26477502 81.05% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21078 0.06% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20355 0.06% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1225 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3659635 11.20% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2180799 6.68% 99.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 303954 0.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued -system.cpu2.iq.rate 1.012645 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32666998 # Type of FU issued +system.cpu2.iq.rate 1.063974 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36013478 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119374 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205891 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 443704 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1465 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6049 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 180746 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5094 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 200289 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 193001 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3976817 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 219021 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35063617 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 53776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3529311 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2248768 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606766 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12977 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 164349 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6049 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63932 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135830 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 199762 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32464526 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3550760 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1379854 # number of nop insts executed -system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6643679 # Number of branches executed -system.cpu2.iew.exec_stores 2129239 # Number of stores executed -system.cpu2.iew.exec_rate 1.006060 # Inst execution rate -system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17254819 # num instructions producing a value -system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value +system.cpu2.iew.exec_nop 1394387 # number of nop insts executed +system.cpu2.iew.exec_refs 5714159 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7350868 # Number of branches executed +system.cpu2.iew.exec_stores 2163399 # Number of stores executed +system.cpu2.iew.exec_rate 1.057379 # Inst execution rate +system.cpu2.iew.wb_sent 32215343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32171488 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18756374 # num instructions producing a value +system.cpu2.iew.wb_consumers 22505351 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.047835 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.833418 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2693673 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194212 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181849 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28653786 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.128143 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.870801 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18143596 63.32% 63.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2243135 7.83% 71.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1187950 4.15% 75.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5112990 17.84% 93.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 566123 1.98% 95.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201198 0.70% 95.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164794 0.58% 96.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 163684 0.57% 96.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 870316 3.04% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30096794 # Number of instructions committed -system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28653786 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32325567 # Number of instructions committed +system.cpu2.commit.committedOps 32325567 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5086249 # Number of memory references committed -system.cpu2.commit.loads 3053005 # Number of loads committed -system.cpu2.commit.membars 67981 # Number of memory barriers committed -system.cpu2.commit.branches 6474041 # Number of branches committed -system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239427 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5153629 # Number of memory references committed +system.cpu2.commit.loads 3085607 # Number of loads committed +system.cpu2.commit.membars 68228 # Number of memory barriers committed +system.cpu2.commit.branches 7176692 # Number of branches committed +system.cpu2.commit.fp_insts 115672 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30802580 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241655 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228058 3.80% 3.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25528107 78.97% 82.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20647 0.06% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20076 0.06% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1225 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3153835 9.76% 92.66% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2069665 6.40% 99.06% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction +system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 59838509 # The number of ROB reads -system.cpu2.rob.rob_writes 65974697 # The number of ROB writes -system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 28883768 # Number of Instructions Simulated -system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads -system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes +system.cpu2.rob.rob_reads 62726939 # The number of ROB reads +system.cpu2.rob.rob_writes 70507401 # The number of ROB writes +system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1578565 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745106872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31099959 # Number of Instructions Simulated +system.cpu2.committedOps 31099959 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.987230 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.987230 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.012935 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.012935 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42640475 # number of integer regfile reads +system.cpu2.int_regfile_writes 22658201 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70901 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71243 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5010785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273099 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1371,10 +1349,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51363 # Transaction distribution -system.iobus.trans_dist::WriteResp 9811 # Transaction distribution +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 9810 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1386,11 +1364,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1402,37 +1380,41 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5364000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 100878274 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8843000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17495500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254165 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892917000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078385 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078385 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1446,14 +1428,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9444962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9444962 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9444962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9444962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9444962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9444962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1470,19 +1452,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54595.156069 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4243 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308037 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1490,234 +1472,237 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75392 # number of writebacks +system.l2c.writebacks::total 75392 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 15641 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4814 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 16829 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418496000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 694509000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 483058500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 727940000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1210998500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.157678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.061015 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019247 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.578947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.354839 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408460 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.254337 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034749 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034749 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61949.204015 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62185.646800 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63528.132185 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63351.177453 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75924.889630 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70595.341502 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1827,92 +1820,92 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 294932 # Transaction distribution -system.membus.trans_dist::ReadResp 294926 # Transaction distribution -system.membus.trans_dist::WriteReq 9811 # Transaction distribution -system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::Writeback 116905 # Transaction distribution +system.membus.trans_dist::ReadReq 295002 # Transaction distribution +system.membus.trans_dist::ReadResp 294996 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::Writeback 116904 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeReq 145 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 165 # Transaction distribution -system.membus.trans_dist::ReadExReq 115724 # Transaction distribution -system.membus.trans_dist::ReadExResp 115724 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 115657 # Transaction distribution +system.membus.trans_dist::ReadExResp 115657 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882256 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1041083 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30677824 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562134 # Request fanout histogram +system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 157 # Total snoops (count) +system.membus.snoop_fanout::samples 562136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562134 # Request fanout histogram -system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562136 # Request fanout histogram +system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 438835201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17657500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063715 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063694 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835707 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 42 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302749 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302749 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930984 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657230 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5588214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61790208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 689338845 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 790311532 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index f1c3d0229..57022429e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.845843 # Number of seconds simulated -sim_ticks 2845842660500 # Number of ticks simulated -final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846001 # Number of seconds simulated +sim_ticks 2846001096000 # Number of ticks simulated +final_tick 2846001096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92448 # Simulator instruction rate (inst/s) -host_op_rate 111941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2101025547 # Simulator tick rate (ticks/s) -host_mem_usage 635156 # Number of bytes of host memory used -host_seconds 1354.50 # Real time elapsed on the host -sim_insts 125221621 # Number of instructions simulated -sim_ops 151624712 # Number of ops (including micro ops) simulated +host_inst_rate 163513 # Simulator instruction rate (inst/s) +host_op_rate 197998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3697981305 # Simulator tick rate (ticks/s) +host_mem_usage 648920 # Number of bytes of host memory used +host_seconds 769.61 # Real time elapsed on the host +sim_insts 125841424 # Number of instructions simulated +sim_ops 152380857 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1722304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1285116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 621216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1676864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1253436 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 601248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 396864 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1722304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory +system.physmem.bytes_read::total 12760092 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1676864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8825856 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8843600 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9730 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6201 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199925 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137904 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142340 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3396 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 605200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 451577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 218289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 589200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 440420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3022526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 139446 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 605200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4483516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 589200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3101143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3107378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3101143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 605200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 457798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 218303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 589200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 446641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3022526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 139446 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 202521 # Number of read requests accepted -system.physmem.writeReqs 180931 # Number of write requests accepted -system.physmem.readBursts 202521 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 180931 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12951936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 11206784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12926236 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11313424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5797 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13571 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12806 # Per bank write bursts -system.physmem.perBankRdBursts::1 12696 # Per bank write bursts -system.physmem.perBankRdBursts::2 13455 # Per bank write bursts -system.physmem.perBankRdBursts::3 13223 # Per bank write bursts -system.physmem.perBankRdBursts::4 15141 # Per bank write bursts -system.physmem.perBankRdBursts::5 12251 # Per bank write bursts -system.physmem.perBankRdBursts::6 12720 # Per bank write bursts -system.physmem.perBankRdBursts::7 12666 # Per bank write bursts -system.physmem.perBankRdBursts::8 12396 # Per bank write bursts -system.physmem.perBankRdBursts::9 12410 # Per bank write bursts -system.physmem.perBankRdBursts::10 12030 # Per bank write bursts -system.physmem.perBankRdBursts::11 11077 # Per bank write bursts -system.physmem.perBankRdBursts::12 12224 # Per bank write bursts -system.physmem.perBankRdBursts::13 12978 # Per bank write bursts -system.physmem.perBankRdBursts::14 12239 # Per bank write bursts -system.physmem.perBankRdBursts::15 12062 # Per bank write bursts -system.physmem.perBankWrBursts::0 11243 # Per bank write bursts -system.physmem.perBankWrBursts::1 11520 # Per bank write bursts -system.physmem.perBankWrBursts::2 11868 # Per bank write bursts -system.physmem.perBankWrBursts::3 11342 # Per bank write bursts -system.physmem.perBankWrBursts::4 10753 # Per bank write bursts -system.physmem.perBankWrBursts::5 10659 # Per bank write bursts -system.physmem.perBankWrBursts::6 11197 # Per bank write bursts -system.physmem.perBankWrBursts::7 10854 # Per bank write bursts -system.physmem.perBankWrBursts::8 10720 # Per bank write bursts -system.physmem.perBankWrBursts::9 10780 # Per bank write bursts -system.physmem.perBankWrBursts::10 10917 # Per bank write bursts -system.physmem.perBankWrBursts::11 10553 # Per bank write bursts -system.physmem.perBankWrBursts::12 10892 # Per bank write bursts -system.physmem.perBankWrBursts::13 10850 # Per bank write bursts -system.physmem.perBankWrBursts::14 10512 # Per bank write bursts -system.physmem.perBankWrBursts::15 10446 # Per bank write bursts +system.physmem.bw_total::total 7590894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199925 # Number of read requests accepted +system.physmem.writeReqs 178564 # Number of write requests accepted +system.physmem.readBursts 199925 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178564 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12787648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 9914112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12760092 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11161936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23627 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14395 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11804 # Per bank write bursts +system.physmem.perBankRdBursts::1 12403 # Per bank write bursts +system.physmem.perBankRdBursts::2 13173 # Per bank write bursts +system.physmem.perBankRdBursts::3 12915 # Per bank write bursts +system.physmem.perBankRdBursts::4 15440 # Per bank write bursts +system.physmem.perBankRdBursts::5 12419 # Per bank write bursts +system.physmem.perBankRdBursts::6 12541 # Per bank write bursts +system.physmem.perBankRdBursts::7 12439 # Per bank write bursts +system.physmem.perBankRdBursts::8 12804 # Per bank write bursts +system.physmem.perBankRdBursts::9 13107 # Per bank write bursts +system.physmem.perBankRdBursts::10 11847 # Per bank write bursts +system.physmem.perBankRdBursts::11 11130 # Per bank write bursts +system.physmem.perBankRdBursts::12 12155 # Per bank write bursts +system.physmem.perBankRdBursts::13 12699 # Per bank write bursts +system.physmem.perBankRdBursts::14 11526 # Per bank write bursts +system.physmem.perBankRdBursts::15 11405 # Per bank write bursts +system.physmem.perBankWrBursts::0 9464 # Per bank write bursts +system.physmem.perBankWrBursts::1 9978 # Per bank write bursts +system.physmem.perBankWrBursts::2 10476 # Per bank write bursts +system.physmem.perBankWrBursts::3 10111 # Per bank write bursts +system.physmem.perBankWrBursts::4 9384 # Per bank write bursts +system.physmem.perBankWrBursts::5 9602 # Per bank write bursts +system.physmem.perBankWrBursts::6 9874 # Per bank write bursts +system.physmem.perBankWrBursts::7 9552 # Per bank write bursts +system.physmem.perBankWrBursts::8 9896 # Per bank write bursts +system.physmem.perBankWrBursts::9 10357 # Per bank write bursts +system.physmem.perBankWrBursts::10 9473 # Per bank write bursts +system.physmem.perBankWrBursts::11 9143 # Per bank write bursts +system.physmem.perBankWrBursts::12 9886 # Per bank write bursts +system.physmem.perBankWrBursts::13 9717 # Per bank write bursts +system.physmem.perBankWrBursts::14 9232 # Per bank write bursts +system.physmem.perBankWrBursts::15 8763 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2845842079500 # Total gap between requests +system.physmem.numWrRetry 62 # Number of times write queue was full causing retry +system.physmem.totGap 2846000520000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 201934 # Read request sizes (log2) +system.physmem.readPktSize::6 199338 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 176495 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9843 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174128 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 99213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -184,158 +184,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 256.627498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.457232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 317.924062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48795 51.83% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18347 19.49% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6488 6.89% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3770 4.00% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2738 2.91% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1619 1.72% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 964 1.02% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1076 1.14% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10342 10.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94139 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7479 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.058430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 520.327968 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7478 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7479 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7479 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.413023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.870843 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.578889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 6390 85.44% 85.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 248 3.32% 88.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 198 2.65% 91.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 77 1.03% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 144 1.93% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 30 0.40% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 35 0.47% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 33 0.44% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 72 0.96% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 21 0.28% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 96 1.28% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 18 0.24% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 22 0.29% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 12 0.16% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 35 0.47% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.16% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.05% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 8 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7479 # Writes before turning the bus around for reads -system.physmem.totQLat 5783977250 # Total ticks spent queuing -system.physmem.totMemAccLat 9578489750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1011870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28580.63 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 117 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.620056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.134877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.994619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47499 52.23% 52.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17879 19.66% 71.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6335 6.97% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3699 4.07% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2819 3.10% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1518 1.67% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 969 1.07% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1044 1.15% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9183 10.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90945 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6522 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.635388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.912572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6520 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6522 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.751610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.656400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.548658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6178 94.73% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.32% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 19 0.29% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 33 0.51% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 33 0.51% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 29 0.44% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.20% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 13 0.20% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.06% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.34% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.28% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 8 0.12% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.09% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.14% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6522 # Writes before turning the bus around for reads +system.physmem.totQLat 5658505376 # Total ticks spent queuing +system.physmem.totMemAccLat 9404886626 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 999035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28319.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47330.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47069.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 168404 # Number of row buffer hits during reads -system.physmem.writeRowHits 114936 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.63 # Row buffer hit rate for writes -system.physmem.avgGap 7421638.38 # Average gap between requests -system.physmem.pageHitRate 75.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 372813840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 203420250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 818672400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 579545280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83421293220 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634324841000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905596723190 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.608836 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2718714861000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing +system.physmem.readRowHits 166469 # Number of row buffer hits during reads +system.physmem.writeRowHits 97300 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.80 # Row buffer hit rate for writes +system.physmem.avgGap 7519374.46 # Average gap between requests +system.physmem.pageHitRate 74.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 351842400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 191977500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 804437400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 508297680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83070715860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634730471750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905544559550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.552036 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719396100671 # Time in different power states +system.physmem_0.memoryStateTime::REF 95034160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32092142750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31570722329 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 338877000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 184903125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 759837000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 555141600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82372109895 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635245177250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905332183070 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.515879 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720254769500 # Time in different power states -system.physmem_1.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem_1.actEnergy 335701800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 183170625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 754049400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 495506160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82302536835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635404313000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905362094780 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.487923 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720522847414 # Time in different power states +system.physmem_1.memoryStateTime::REF 95034160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30559102000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30442207586 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -361,15 +365,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 35059389 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17250705 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1579435 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20094508 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14609065 # Number of BTB hits +system.cpu0.branchPred.lookups 20635824 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13602989 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1045571 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13187813 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9323038 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.701780 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10810171 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 733013 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.694345 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3366354 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 208367 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -400,58 +404,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 67889 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67889 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44852 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23037 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67889 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67889 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67889 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6673 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8598.195564 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7320.525431 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6106.619536 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6491 97.27% 97.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 168 2.52% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6673 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 287368000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 287368000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 287368000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5164 77.39% 77.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1509 22.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6673 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 68383 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 68383 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45560 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22823 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 68383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 68383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 68383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6747 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9430.747147 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8234.841596 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6251.099816 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6572 97.41% 97.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 158 2.34% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6747 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5180 76.77% 76.77% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1567 23.23% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6747 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68383 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67889 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6673 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68383 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6747 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6673 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74562 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6747 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 75130 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23969568 # DTB read hits -system.cpu0.dtb.read_misses 61820 # DTB read misses -system.cpu0.dtb.write_hits 17946825 # DTB write hits -system.cpu0.dtb.write_misses 6069 # DTB write misses +system.cpu0.dtb.read_hits 17310932 # DTB read hits +system.cpu0.dtb.read_misses 62315 # DTB read misses +system.cpu0.dtb.write_hits 14537397 # DTB write hits +system.cpu0.dtb.write_misses 6068 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1251 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2004 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24031388 # DTB read accesses -system.cpu0.dtb.write_accesses 17952894 # DTB write accesses +system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17373247 # DTB read accesses +system.cpu0.dtb.write_accesses 14543465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41916393 # DTB hits -system.cpu0.dtb.misses 67889 # DTB misses -system.cpu0.dtb.accesses 41984282 # DTB accesses +system.cpu0.dtb.hits 31848329 # DTB hits +system.cpu0.dtb.misses 68383 # DTB misses +system.cpu0.dtb.accesses 31916712 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,38 +486,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3825 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3825 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3518 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3825 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3825 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3825 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 8874.535345 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7628.532351 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4888.994435 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1491 61.64% 61.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 888 36.71% 98.35% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 286941000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 286941000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 286941000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3838 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3838 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3532 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3838 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3838 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3838 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9817.861169 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8667.312532 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5173.169908 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 854 35.39% 35.39% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1509 62.54% 97.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.12% 98.05% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 46 1.91% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2114 87.61% 87.61% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.39% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2413 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3825 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3825 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3838 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3838 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 70462798 # ITB inst hits -system.cpu0.itb.inst_misses 3825 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2413 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2413 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6251 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38726658 # ITB inst hits +system.cpu0.itb.inst_misses 3838 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -521,123 +526,123 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7291 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7377 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70466623 # ITB inst accesses -system.cpu0.itb.hits 70462798 # DTB hits -system.cpu0.itb.misses 3825 # DTB misses -system.cpu0.itb.accesses 70466623 # DTB accesses -system.cpu0.numCycles 234985394 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38730496 # ITB inst accesses +system.cpu0.itb.hits 38726658 # DTB hits +system.cpu0.itb.misses 3838 # DTB misses +system.cpu0.itb.accesses 38730496 # DTB accesses +system.cpu0.numCycles 164623207 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 109265327 # Number of instructions committed -system.cpu0.committedOps 132114239 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8364757 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1821 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5456715361 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.150594 # CPI: cycles per instruction -system.cpu0.ipc 0.464988 # IPC: instructions per cycle +system.cpu0.committedInsts 79533802 # Number of instructions committed +system.cpu0.committedOps 95718607 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5045973 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1856 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527394503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.069852 # CPI: cycles per instruction +system.cpu0.ipc 0.483126 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1824 # number of quiesce instructions executed -system.cpu0.tickCycles 195318282 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 39667112 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 718541 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.305697 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40476936 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.305697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965441 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed +system.cpu0.tickCycles 128554371 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36068836 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 714653 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.517650 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30439123 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715165 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.562378 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.517650 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977574 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22808347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16863099 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 381264 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362825 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 39671446 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 39671446 # number of overall hits -system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 540080 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 532227 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6489 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19898 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1072307 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1072307 # number of overall misses -system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 14968306916 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026318 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026318 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22019.443411 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63710880 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63710880 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 16167111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 16167111 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13468154 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13468154 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 380067 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 380067 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361342 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361342 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29635265 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29635265 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29635265 # number of overall hits +system.cpu0.dcache.overall_hits::total 29635265 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 537159 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 537159 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 529716 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 529716 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6447 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6447 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20264 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20264 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1066875 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1066875 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1066875 # number of overall misses +system.cpu0.dcache.overall_misses::total 1066875 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6690812322 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6690812322 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8678584493 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8678584493 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104630740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 104630740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454305285 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 454305285 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 153000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 153000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15369396815 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15369396815 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15369396815 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15369396815 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16704270 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16704270 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13997870 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13997870 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386514 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386514 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381606 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381606 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30702140 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30702140 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30702140 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30702140 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032157 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032157 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037843 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016680 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016680 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053102 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053102 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034749 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034749 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034749 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.034749 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12455.925195 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12455.925195 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16383.466788 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16383.466788 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16229.368699 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16229.368699 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22419.329106 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22419.329106 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14405.995843 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14405.995843 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,74 +651,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks -system.cpu0.dcache.writebacks::total 523102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 273091 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6489 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19898 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 799216 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 799216 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149793898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4423706193 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91926250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 397751115 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 291000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9573500091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4804555500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10995546249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016735 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051991 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10352.967697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14658.032277 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14166.474033 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19989.502211 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 516062 # number of writebacks +system.cpu0.dcache.writebacks::total 516062 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42087 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42087 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 229086 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 229086 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 271173 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 271173 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 271173 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 271173 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 495072 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 495072 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 300630 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 300630 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20264 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20264 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 795702 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 795702 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 795702 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 795702 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5420342985 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5420342985 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4742244244 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4742244244 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94933760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94933760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423201715 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423201715 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 147000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 147000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10162587229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10162587229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10162587229 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10162587229 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276747000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276747000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261903001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261903001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538650001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538650001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029637 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029637 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021477 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021477 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053102 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053102 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025917 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025917 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10948.595326 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10948.595326 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15774.354669 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15774.354669 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14725.261362 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14725.261362 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20884.411518 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.411518 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +726,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1982441 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.792915 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 68472197 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1982953 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.530419 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6378447750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.792915 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999596 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999596 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1970130 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.783768 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36748265 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1970642 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.647865 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6452193250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783768 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 142893294 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 142893294 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 68472197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 68472197 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 68472197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 68472197 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 68472197 # number of overall hits -system.cpu0.icache.overall_hits::total 68472197 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1982967 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1982967 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1982967 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1982967 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1982967 # number of overall misses -system.cpu0.icache.overall_misses::total 1982967 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18641895952 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18641895952 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18641895952 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18641895952 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18641895952 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18641895952 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70455164 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70455164 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70455164 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70455164 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70455164 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70455164 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028145 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028145 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028145 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028145 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028145 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028145 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9401.011692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9401.011692 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9401.011692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9401.011692 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79408512 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79408512 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36748265 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36748265 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36748265 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36748265 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36748265 # number of overall hits +system.cpu0.icache.overall_hits::total 36748265 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1970661 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1970661 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1970661 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1970661 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1970661 # number of overall misses +system.cpu0.icache.overall_misses::total 1970661 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18596838762 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18596838762 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18596838762 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18596838762 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18596838762 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18596838762 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38718926 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38718926 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38718926 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38718926 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38718926 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38718926 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050897 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050897 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050897 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050897 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050897 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050897 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9436.853300 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9436.853300 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9436.853300 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9436.853300 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,224 +786,225 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1982967 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1982967 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1982967 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1982967 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1982967 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1982967 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15657207046 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 15657207046 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15657207046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 15657207046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15657207046 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 15657207046 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 278031000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 278031000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 278031000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 278031000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028145 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028145 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028145 # 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average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8432.101330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2969035 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 319611 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.289527 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5929.101601 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1862.423160 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361884 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.113673 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 509 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 923 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 288151 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 300423 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16135.818285 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2948802 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 316647 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.312585 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2825975663500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6474.830142 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.840728 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090495 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5820.472159 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1850.674004 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1932.910757 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.395192 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003469 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355253 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.112956 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.117976 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984852 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1935 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14276 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 526 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 949 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 452 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4022 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7455 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2494 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.118469 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871582 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 55347065 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 55347065 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80493 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4332 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1910084 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 434260 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2429169 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 523100 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 523100 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4781 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 4781 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1890 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1890 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226532 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 226532 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80493 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4332 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1910084 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 660792 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2655701 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80493 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4332 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1910084 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 660792 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2655701 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 854 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 72883 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 69644 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 143494 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26406 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26406 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18006 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18006 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44082 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44082 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 854 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 72883 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 113726 # 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number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7515138500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.139055 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055325 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.846699 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905006 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.851603 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.851603 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.910132 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.910132 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150831 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.156281 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.156281 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064926 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23156.467008 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 35947.135948 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.164053 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24533.565603 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32091.248642 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53498.080753 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20212.609271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20212.609271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14702.299751 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14702.299751 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 116499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 116499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38767.974866 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38767.974866 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33619.682585 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45630.907306 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1144,67 +1147,65 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2669763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 523100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 388140 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 64720 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42432 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 88655 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286773 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3972081 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2399294 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11788 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172273 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6555436 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127106560 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 87442327 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17780 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325388 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 214892055 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 732010 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4046250 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.152317 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.359328 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2704309 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2644372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 516061 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 357573 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 65952 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 89535 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284517 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3948091 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2342949 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11777 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172611 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6475428 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126338880 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86633336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17628 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325620 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 213315464 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 705686 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3997625 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.147566 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.354669 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3429939 84.77% 84.77% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 616311 15.23% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 3407711 85.24% 85.24% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 589914 14.76% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4046250 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2284841999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3997625 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2250942493 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117254000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117029497 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2984852953 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2966538511 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1241569539 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1219549045 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7347491 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7373994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90940738 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 91216246 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4088735 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2366310 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 253216 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2663045 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1651600 # Number of BTB hits +system.cpu1.branchPred.lookups 18670420 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6078179 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 807720 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9612678 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 6998038 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 62.019230 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 809555 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 58673 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.800088 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8300224 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 592338 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1234,58 +1235,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 25571 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 25571 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18521 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7050 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 25571 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 25571 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 25571 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 8701.256278 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7631.681902 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5745.938863 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2093 77.29% 77.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 481 17.76% 95.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 26198 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26198 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19047 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7151 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26198 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26198 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26198 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2710 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9322.699631 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8294.308784 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5681.860876 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1066 39.34% 39.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1510 55.72% 95.06% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 9 0.33% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.15% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1108722264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1108722264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1108722264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.74% 73.74% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 711 26.26% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 25571 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.14% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.22% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 3 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2710 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1205143764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1205143764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1205143764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2001 73.84% 73.84% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 709 26.16% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2710 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26198 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 25571 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26198 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2710 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28279 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2710 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28908 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4075725 # DTB read hits -system.cpu1.dtb.read_misses 23546 # DTB read misses -system.cpu1.dtb.write_hits 3346999 # DTB write hits -system.cpu1.dtb.write_misses 2025 # DTB write misses +system.cpu1.dtb.read_hits 10899944 # DTB read hits +system.cpu1.dtb.read_misses 24664 # DTB read misses +system.cpu1.dtb.write_hits 6857896 # DTB write hits +system.cpu1.dtb.write_misses 1534 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2069 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 121 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 325 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 340 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4099271 # DTB read accesses -system.cpu1.dtb.write_accesses 3349024 # DTB write accesses +system.cpu1.dtb.read_accesses 10924608 # DTB read accesses +system.cpu1.dtb.write_accesses 6859430 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7422724 # DTB hits -system.cpu1.dtb.misses 25571 # DTB misses -system.cpu1.dtb.accesses 7448295 # DTB accesses +system.cpu1.dtb.hits 17757840 # DTB hits +system.cpu1.dtb.misses 26198 # DTB misses +system.cpu1.dtb.accesses 17784038 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1315,42 +1317,41 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2243 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2243 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2062 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2243 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2243 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2243 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 8831.106061 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7825.020839 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4777.823788 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 160 14.26% 14.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 676 60.25% 74.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 3 0.27% 74.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 248 22.10% 96.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 98.13% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.69% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1108154264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1108154264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1108154264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 954 85.03% 85.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 14.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2253 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2253 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2076 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2253 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9627.345845 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8644.762201 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4978.900312 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.44% 16.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.39% 30.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 501 44.77% 75.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 236 21.09% 96.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 97.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.88% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1204569264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1204569264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1204569264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 955 85.34% 85.34% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 164 14.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2243 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2243 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2253 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2253 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3365 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 7772051 # ITB inst hits -system.cpu1.itb.inst_misses 2243 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3372 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39818327 # ITB inst hits +system.cpu1.itb.inst_misses 2253 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1359,122 +1360,122 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1845 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7774294 # ITB inst accesses -system.cpu1.itb.hits 7772051 # DTB hits -system.cpu1.itb.misses 2243 # DTB misses -system.cpu1.itb.accesses 7774294 # DTB accesses -system.cpu1.numCycles 42246986 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39820580 # ITB inst accesses +system.cpu1.itb.hits 39818327 # DTB hits +system.cpu1.itb.misses 2253 # DTB misses +system.cpu1.itb.accesses 39820580 # DTB accesses +system.cpu1.numCycles 115094455 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15956294 # Number of instructions committed -system.cpu1.committedOps 19510473 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1491389 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2792 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5648821854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.647669 # CPI: cycles per instruction -system.cpu1.ipc 0.377691 # IPC: instructions per cycle +system.cpu1.committedInsts 46307622 # Number of instructions committed +system.cpu1.committedOps 56662250 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4905736 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2805 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576292649 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.485432 # CPI: cycles per instruction +system.cpu1.ipc 0.402345 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2795 # number of quiesce instructions executed -system.cpu1.tickCycles 30354295 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 11892691 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 187758 # number of replacements -system.cpu1.dcache.tags.tagsinuse 478.493571 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7034054 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.493571 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934558 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3762812 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3070723 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 89288 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69262 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6833535 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6833535 # number of overall hits -system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181434 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139542 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5058 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23425 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320976 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320976 # number of overall misses -system.cpu1.dcache.overall_misses::total 320976 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6371545718 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.252732 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # 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Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 35540406 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 35540406 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10562839 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10562839 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6561699 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6561699 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 92378 # 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average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20052.123480 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20052.123480 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,74 +1484,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks -system.cpu1.dcache.writebacks::total 113901 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 64931 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 64931 # 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number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053611 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # 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average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 255012 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 255045 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 26 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 263000 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 263018 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 67427 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 54264 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15327.785502 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1131516 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 69292 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.329677 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 69926 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 55260 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15340.181807 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1180273 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 70026 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.854783 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3126.745417 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2197.034801 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 7920.573124 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.864575 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.107624 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4396.054830 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2144.688544 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 841.893110 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.483433 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002250 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.190841 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.134096 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12927 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 84 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 880 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1092 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.268314 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130901 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051385 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.936290 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2047 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12670 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 77 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 853 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1117 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 271 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6900 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.125488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.789001 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21629208 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21629208 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28145 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2626 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 889570 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 104349 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1024690 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 113900 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 113900 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1602 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1602 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 24979 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 889570 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 129328 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28145 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2626 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 889570 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 129328 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1049669 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 614 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18958 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 67006 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 86797 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28133 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28133 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22540 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22540 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35034 # 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number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4335498 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 588499240 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1440160422 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2046112410 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 524558345 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 524558345 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 440871540 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440871540 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 173000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 173000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1316941950 # 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number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3363054360 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28759 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2845 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 908528 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171355 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1111487 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 113900 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 113900 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29735 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29735 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23425 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23425 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60013 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 60013 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28759 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2845 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 908528 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 231368 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1171500 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28759 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2845 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 908528 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 231368 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1171500 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076977 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020867 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.391036 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.078091 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946124 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946124 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962220 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962220 # 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miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.103996 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31042.263952 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21493.006925 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18645.659723 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19559.518190 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5605 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.124939 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.773315 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 22538505 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 22538505 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28252 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2535 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2178958034 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2789665792 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2975000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 596579765 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2178958034 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 967597598 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3757263390 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9248000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205503500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214751500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754476501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754476501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9248000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959980001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969228001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.382714 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077373 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946124 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962220 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.579041 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949225 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949225 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960241 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.960241 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559621 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559621 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102090 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14482.907170 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13602.785492 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124466 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15397.298227 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18475.608133 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35413.300077 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15957.484300 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15957.484300 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15100.211457 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15100.211457 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30008.051108 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32362.948722 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32362.948722 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22377.297493 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24720.789733 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1964,64 +1965,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1157222 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2126 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2126 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 113900 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 36842 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74786 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41424 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 82199 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 64364 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1817284 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 767101 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7150 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 61380 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2652915 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58153088 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24793955 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11380 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115036 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 83073459 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 610470 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1874725 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.283158 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.450533 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1549513 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1217389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120163 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 34752 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76638 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42182 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86369 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85047 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67036 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1899176 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835933 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7082 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62248 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2804439 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60773632 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25876936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11012 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115596 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86777176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 610005 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1929839 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.274006 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.446012 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1343882 71.68% 71.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 530843 28.32% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 1401052 72.60% 72.60% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 528787 27.40% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1874725 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 789561722 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1929839 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 840003478 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79017500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80148998 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1364909988 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381206023 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1425055438 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 412471555 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4307495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4329500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 32623745 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33365476 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31012 # Transaction distribution -system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59440 # Transaction distribution -system.iobus.trans_dist::WriteResp 23216 # Transaction distribution +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2042,11 +2041,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2067,11 +2066,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2111,52 +2110,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347036169 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 199065929 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36822569 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36796533 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36417 # number of replacements -system.iocache.tags.tagsinuse 0.997930 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.480362 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 269849823000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.997930 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062371 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062371 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270133806000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.480362 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.905023 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.905023 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30354377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30354377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9625347223 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9625347223 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30354377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30354377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30354377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30354377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32660377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32660377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6669320019 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6669320019 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32660377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32660377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32660377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32660377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2165,40 +2164,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124915.131687 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124915.131687 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124915.131687 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56938 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128079.909804 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128079.909804 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184113.295578 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 184113.295578 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128079.909804 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128079.909804 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23275 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7266 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.836224 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.476071 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36174 # number of writebacks -system.iocache.writebacks::total 36174 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17717377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17717377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7741561361 # 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mshr miss rate for WriteInvalidateReq accesses @@ -2207,304 +2206,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72911.016461 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28977 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.485153 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.497330 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5313847 # Number of tag accesses -system.l2c.tags.data_accesses 5313847 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 48963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21691 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533180000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4296799000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205849250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478408750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6630000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453209500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10144097500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.121079 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.496925 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.749800 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.760340 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.808187 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.891365 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.860323 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737215 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.832110 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774809 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.435658 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.507959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.515497 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.435658 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.507959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.515497 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74516.538416 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73944.513196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87588.427365 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17836.287759 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.012109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17818.385732 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17922.124457 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.561719 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17828.243024 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80203.430324 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69785.069598 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75770.793429 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2707,57 +2706,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 217279 # Transaction distribution -system.membus.trans_dist::ReadResp 217279 # Transaction distribution -system.membus.trans_dist::WriteReq 30939 # Transaction distribution -system.membus.trans_dist::WriteResp 30939 # Transaction distribution -system.membus.trans_dist::Writeback 140271 # Transaction distribution +system.membus.trans_dist::ReadReq 215369 # Transaction distribution +system.membus.trans_dist::ReadResp 215369 # Transaction distribution +system.membus.trans_dist::WriteReq 31074 # Transaction distribution +system.membus.trans_dist::WriteResp 31074 # Transaction distribution +system.membus.trans_dist::Writeback 137904 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 75080 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40217 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13603 # Transaction distribution -system.membus.trans_dist::ReadExReq 40948 # Transaction distribution -system.membus.trans_dist::ReadExResp 20159 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77019 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40910 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14411 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 39992 # Transaction distribution +system.membus.trans_dist::ReadExResp 19617 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13590 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 668031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 789629 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 898509 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894551 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19605228 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19796474 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24430906 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123136 # Total snoops (count) -system.membus.snoop_fanout::samples 511969 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19286572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19478976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24114432 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124537 # Total snoops (count) +system.membus.snoop_fanout::samples 508980 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511969 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 508980 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511969 # Request fanout histogram -system.membus.reqLayer0.occupancy 88887000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 508980 # Request fanout histogram +system.membus.reqLayer0.occupancy 88720999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11855500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12492999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1869891749 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2005520473 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38480431 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1167594605 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1174957130 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37546467 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2790,44 +2790,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 516876 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 516861 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30939 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30939 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 234152 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 78584 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40535 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 119119 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51536 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51536 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1131248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290761 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1422009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34509719 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5415139 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39924858 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 285546 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 919868 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039644 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195121 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 518257 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 518242 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31074 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31074 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232242 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80802 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 122032 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51798 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51798 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1084621 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339731 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1424352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34113464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5575752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39689216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 290726 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 922102 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039605 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195030 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 883401 96.04% 96.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36467 3.96% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 885582 96.04% 96.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36520 3.96% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 919868 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1489301846 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 922102 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 794355306 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1891845782 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 645358377 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 683518313 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 260405210 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 6a8c865e1..6dd28da03 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852858 # Number of seconds simulated -sim_ticks 2852857543000 # Number of ticks simulated -final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.853442 # Number of seconds simulated +sim_ticks 2853442108500 # Number of ticks simulated +final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109881 # Simulator instruction rate (inst/s) -host_op_rate 132861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2793727953 # Simulator tick rate (ticks/s) -host_mem_usage 608784 # Number of bytes of host memory used -host_seconds 1021.17 # Real time elapsed on the host -sim_insts 112207125 # Number of instructions simulated -sim_ops 135672670 # Number of ops (including micro ops) simulated +host_inst_rate 171765 # Simulator instruction rate (inst/s) +host_op_rate 207684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4374009836 # Simulator tick rate (ticks/s) +host_mem_usage 619996 # Number of bytes of host memory used +host_seconds 652.36 # Real time elapsed on the host +sim_insts 112053421 # Number of instructions simulated +sim_ops 135485276 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory +system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170006 # Number of read requests accepted -system.physmem.writeReqs 165023 # Number of write requests accepted -system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10656 # Per bank write bursts -system.physmem.perBankRdBursts::1 10651 # Per bank write bursts -system.physmem.perBankRdBursts::2 10704 # Per bank write bursts -system.physmem.perBankRdBursts::3 10614 # Per bank write bursts -system.physmem.perBankRdBursts::4 13356 # Per bank write bursts -system.physmem.perBankRdBursts::5 10666 # Per bank write bursts -system.physmem.perBankRdBursts::6 11042 # Per bank write bursts -system.physmem.perBankRdBursts::7 10972 # Per bank write bursts -system.physmem.perBankRdBursts::8 10208 # Per bank write bursts -system.physmem.perBankRdBursts::9 10672 # Per bank write bursts -system.physmem.perBankRdBursts::10 10509 # Per bank write bursts -system.physmem.perBankRdBursts::11 9657 # Per bank write bursts -system.physmem.perBankRdBursts::12 10109 # Per bank write bursts -system.physmem.perBankRdBursts::13 10747 # Per bank write bursts -system.physmem.perBankRdBursts::14 9757 # Per bank write bursts -system.physmem.perBankRdBursts::15 9582 # Per bank write bursts -system.physmem.perBankWrBursts::0 10072 # Per bank write bursts -system.physmem.perBankWrBursts::1 10092 # Per bank write bursts -system.physmem.perBankWrBursts::2 10491 # Per bank write bursts -system.physmem.perBankWrBursts::3 10304 # Per bank write bursts -system.physmem.perBankWrBursts::4 9538 # Per bank write bursts -system.physmem.perBankWrBursts::5 9899 # Per bank write bursts -system.physmem.perBankWrBursts::6 10133 # Per bank write bursts -system.physmem.perBankWrBursts::7 10134 # Per bank write bursts -system.physmem.perBankWrBursts::8 10091 # Per bank write bursts -system.physmem.perBankWrBursts::9 10380 # Per bank write bursts -system.physmem.perBankWrBursts::10 10169 # Per bank write bursts -system.physmem.perBankWrBursts::11 9697 # Per bank write bursts -system.physmem.perBankWrBursts::12 9799 # Per bank write bursts -system.physmem.perBankWrBursts::13 10201 # Per bank write bursts -system.physmem.perBankWrBursts::14 9040 # Per bank write bursts -system.physmem.perBankWrBursts::15 8946 # Per bank write bursts +system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170041 # Number of read requests accepted +system.physmem.writeReqs 165183 # Number of write requests accepted +system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10431 # Per bank write bursts +system.physmem.perBankRdBursts::1 10779 # Per bank write bursts +system.physmem.perBankRdBursts::2 11040 # Per bank write bursts +system.physmem.perBankRdBursts::3 10735 # Per bank write bursts +system.physmem.perBankRdBursts::4 13061 # Per bank write bursts +system.physmem.perBankRdBursts::5 10390 # Per bank write bursts +system.physmem.perBankRdBursts::6 11080 # Per bank write bursts +system.physmem.perBankRdBursts::7 11267 # Per bank write bursts +system.physmem.perBankRdBursts::8 10153 # Per bank write bursts +system.physmem.perBankRdBursts::9 10232 # Per bank write bursts +system.physmem.perBankRdBursts::10 10264 # Per bank write bursts +system.physmem.perBankRdBursts::11 9394 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10799 # Per bank write bursts +system.physmem.perBankRdBursts::14 10090 # Per bank write bursts +system.physmem.perBankRdBursts::15 9930 # Per bank write bursts +system.physmem.perBankWrBursts::0 8676 # Per bank write bursts +system.physmem.perBankWrBursts::1 9067 # Per bank write bursts +system.physmem.perBankWrBursts::2 9547 # Per bank write bursts +system.physmem.perBankWrBursts::3 9319 # Per bank write bursts +system.physmem.perBankWrBursts::4 8434 # Per bank write bursts +system.physmem.perBankWrBursts::5 8678 # Per bank write bursts +system.physmem.perBankWrBursts::6 9214 # Per bank write bursts +system.physmem.perBankWrBursts::7 9423 # Per bank write bursts +system.physmem.perBankWrBursts::8 8918 # Per bank write bursts +system.physmem.perBankWrBursts::9 8886 # Per bank write bursts +system.physmem.perBankWrBursts::10 8752 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8824 # Per bank write bursts +system.physmem.perBankWrBursts::13 8894 # Per bank write bursts +system.physmem.perBankWrBursts::14 8297 # Per bank write bursts +system.physmem.perBankWrBursts::15 8373 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2852857119000 # Total gap between requests +system.physmem.numWrRetry 40 # Number of times write queue was full causing retry +system.physmem.totGap 2853441702500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169451 # Read request sizes (log2) +system.physmem.readPktSize::6 169486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160642 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160802 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,177 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads -system.physmem.totQLat 1659710000 # Total ticks spent queuing -system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads +system.physmem.totQLat 1685079736 # Total ticks spent queuing +system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing -system.physmem.readRowHits 140084 # Number of row buffer hits during reads -system.physmem.writeRowHits 125841 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes -system.physmem.avgGap 8515254.26 # Average gap between requests -system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.469106 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 140217 # Number of row buffer hits during reads +system.physmem.writeRowHits 109661 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes +system.physmem.avgGap 8512044.79 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.452112 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states +system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.371033 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.362464 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states +system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -349,15 +334,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31058702 # Number of BP lookups -system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits +system.cpu.branchPred.lookups 31053109 # Number of BP lookups +system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -388,57 +373,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66845 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 65844 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24793006 # DTB read hits -system.cpu.dtb.read_misses 59858 # DTB read misses -system.cpu.dtb.write_hits 19468400 # DTB write hits -system.cpu.dtb.write_misses 6987 # DTB write misses +system.cpu.dtb.read_hits 24757406 # DTB read hits +system.cpu.dtb.read_misses 59085 # DTB read misses +system.cpu.dtb.write_hits 19449348 # DTB write hits +system.cpu.dtb.write_misses 6759 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24852864 # DTB read accesses -system.cpu.dtb.write_accesses 19475387 # DTB write accesses +system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24816491 # DTB read accesses +system.cpu.dtb.write_accesses 19456107 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44261406 # DTB hits -system.cpu.dtb.misses 66845 # DTB misses -system.cpu.dtb.accesses 44328251 # DTB accesses +system.cpu.dtb.hits 44206754 # DTB hits +system.cpu.dtb.misses 65844 # DTB misses +system.cpu.dtb.accesses 44272598 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,37 +454,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5440 # Table walker walks requested -system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated +system.cpu.itb.walker.walks 5446 # Table walker walks requested +system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57692911 # ITB inst hits -system.cpu.itb.inst_misses 5440 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57726188 # ITB inst hits +system.cpu.itb.inst_misses 5446 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -507,119 +493,119 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57698351 # ITB inst accesses -system.cpu.itb.hits 57692911 # DTB hits -system.cpu.itb.misses 5440 # DTB misses -system.cpu.itb.accesses 57698351 # DTB accesses -system.cpu.numCycles 314937774 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57731634 # ITB inst accesses +system.cpu.itb.hits 57726188 # DTB hits +system.cpu.itb.misses 5446 # DTB misses +system.cpu.itb.accesses 57731634 # DTB accesses +system.cpu.numCycles 317415724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112207125 # Number of instructions committed -system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112053421 # Number of instructions committed +system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.806754 # CPI: cycles per instruction -system.cpu.ipc 0.356283 # IPC: instructions per cycle +system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.832718 # CPI: cycles per instruction +system.cpu.ipc 0.353018 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228221487 # Number of cycles that the object actually ticked -system.cpu.idleCycles 86716287 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 841983 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953279 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42762284 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked +system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842109 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits -system.cpu.dcache.overall_hits::total 41841174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits +system.cpu.dcache.overall_hits::total 41785966 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses -system.cpu.dcache.overall_misses::total 1125141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # 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Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60584835 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60584835 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54783568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54783568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54783568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54783568 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54783568 # number of overall hits -system.cpu.icache.overall_hits::total 54783568 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2900634 # 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number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57684202 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57684202 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57684202 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57684202 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57684202 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050285 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050285 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050285 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050285 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050285 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050285 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.615517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13503.615517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13503.615517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13503.615517 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60616478 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60616478 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54818221 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54818221 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54818221 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54818221 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33358375709 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33358375709 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33358375709 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33358375709 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222066250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222066250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222066250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 222066250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050285 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050285 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050285 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11500.373956 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11500.373956 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2899129 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2899129 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2899129 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2899129 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2899129 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2899129 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34950907125 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34950907125 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34950907125 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34950907125 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34950907125 # 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Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.489031 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5306.229599 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.724770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47373.506796 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.256900 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12244.945403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5373.703806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.722862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001026 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.080967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992905 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2285 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6934 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000565 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36621683 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # 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average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65033.561856 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65033.561856 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1069,61 +1055,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61311 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284832397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61029 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4577967 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1144,11 +1128,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1169,11 +1153,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1213,23 +1197,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1243,14 +1227,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1267,19 +1251,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1293,14 +1277,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,66 +1293,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71749 # Transaction distribution -system.membus.trans_dist::ReadResp 71749 # Transaction distribution -system.membus.trans_dist::WriteReq 27607 # Transaction distribution -system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 124418 # Transaction distribution +system.membus.trans_dist::ReadReq 71726 # Transaction distribution +system.membus.trans_dist::ReadResp 71726 # Transaction distribution +system.membus.trans_dist::WriteReq 27583 # Transaction distribution +system.membus.trans_dist::WriteResp 27583 # Transaction distribution +system.membus.trans_dist::Writeback 124578 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution -system.membus.trans_dist::ReadExReq 129351 # Transaction distribution -system.membus.trans_dist::ReadExResp 129351 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution +system.membus.trans_dist::ReadExReq 129395 # Transaction distribution +system.membus.trans_dist::ReadExResp 129395 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 332202 # Request fanout histogram +system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 504 # Total snoops (count) +system.membus.snoop_fanout::samples 332271 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332202 # Request fanout histogram -system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332271 # Request fanout histogram +system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index c276b537b..b7b8c766f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827025 # Number of seconds simulated -sim_ticks 2827025397500 # Number of ticks simulated -final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827616 # Number of seconds simulated +sim_ticks 2827616186000 # Number of ticks simulated +final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71679 # Simulator instruction rate (inst/s) -host_op_rate 86943 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1789973688 # Simulator tick rate (ticks/s) -host_mem_usage 620632 # Number of bytes of host memory used -host_seconds 1579.37 # Real time elapsed on the host -sim_insts 113206948 # Number of instructions simulated -sim_ops 137314363 # Number of ops (including micro ops) simulated +host_inst_rate 69501 # Simulator instruction rate (inst/s) +host_op_rate 84304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1736810486 # Simulator tick rate (ticks/s) +host_mem_usage 620504 # Number of bytes of host memory used +host_seconds 1628.05 # Real time elapsed on the host +sim_insts 113151083 # Number of instructions simulated +sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory +system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171932 # Number of read requests accepted -system.physmem.writeReqs 167449 # Number of write requests accepted -system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11320 # Per bank write bursts -system.physmem.perBankRdBursts::1 10283 # Per bank write bursts -system.physmem.perBankRdBursts::2 11137 # Per bank write bursts -system.physmem.perBankRdBursts::3 11363 # Per bank write bursts -system.physmem.perBankRdBursts::4 13028 # Per bank write bursts -system.physmem.perBankRdBursts::5 10237 # Per bank write bursts -system.physmem.perBankRdBursts::6 10954 # Per bank write bursts -system.physmem.perBankRdBursts::7 11381 # Per bank write bursts -system.physmem.perBankRdBursts::8 10407 # Per bank write bursts -system.physmem.perBankRdBursts::9 11232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10729 # Per bank write bursts -system.physmem.perBankRdBursts::11 9386 # Per bank write bursts -system.physmem.perBankRdBursts::12 9853 # Per bank write bursts -system.physmem.perBankRdBursts::13 10909 # Per bank write bursts -system.physmem.perBankRdBursts::14 9951 # Per bank write bursts -system.physmem.perBankRdBursts::15 9636 # Per bank write bursts -system.physmem.perBankWrBursts::0 10810 # Per bank write bursts -system.physmem.perBankWrBursts::1 10132 # Per bank write bursts -system.physmem.perBankWrBursts::2 10502 # Per bank write bursts -system.physmem.perBankWrBursts::3 10558 # Per bank write bursts -system.physmem.perBankWrBursts::4 9654 # Per bank write bursts -system.physmem.perBankWrBursts::5 9978 # Per bank write bursts -system.physmem.perBankWrBursts::6 10358 # Per bank write bursts -system.physmem.perBankWrBursts::7 10535 # Per bank write bursts -system.physmem.perBankWrBursts::8 10309 # Per bank write bursts -system.physmem.perBankWrBursts::9 10935 # Per bank write bursts -system.physmem.perBankWrBursts::10 10009 # Per bank write bursts -system.physmem.perBankWrBursts::11 9154 # Per bank write bursts -system.physmem.perBankWrBursts::12 9556 # Per bank write bursts -system.physmem.perBankWrBursts::13 10555 # Per bank write bursts -system.physmem.perBankWrBursts::14 9521 # Per bank write bursts -system.physmem.perBankWrBursts::15 9009 # Per bank write bursts +system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.writeReqs 171661 # Number of write requests accepted +system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11334 # Per bank write bursts +system.physmem.perBankRdBursts::1 10890 # Per bank write bursts +system.physmem.perBankRdBursts::2 10732 # Per bank write bursts +system.physmem.perBankRdBursts::3 10393 # Per bank write bursts +system.physmem.perBankRdBursts::4 14045 # Per bank write bursts +system.physmem.perBankRdBursts::5 11531 # Per bank write bursts +system.physmem.perBankRdBursts::6 11498 # Per bank write bursts +system.physmem.perBankRdBursts::7 11674 # Per bank write bursts +system.physmem.perBankRdBursts::8 10645 # Per bank write bursts +system.physmem.perBankRdBursts::9 10993 # Per bank write bursts +system.physmem.perBankRdBursts::10 10307 # Per bank write bursts +system.physmem.perBankRdBursts::11 9597 # Per bank write bursts +system.physmem.perBankRdBursts::12 9956 # Per bank write bursts +system.physmem.perBankRdBursts::13 10908 # Per bank write bursts +system.physmem.perBankRdBursts::14 10689 # Per bank write bursts +system.physmem.perBankRdBursts::15 10844 # Per bank write bursts +system.physmem.perBankWrBursts::0 9257 # Per bank write bursts +system.physmem.perBankWrBursts::1 9346 # Per bank write bursts +system.physmem.perBankWrBursts::2 9336 # Per bank write bursts +system.physmem.perBankWrBursts::3 8962 # Per bank write bursts +system.physmem.perBankWrBursts::4 9705 # Per bank write bursts +system.physmem.perBankWrBursts::5 9746 # Per bank write bursts +system.physmem.perBankWrBursts::6 9125 # Per bank write bursts +system.physmem.perBankWrBursts::7 9630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9307 # Per bank write bursts +system.physmem.perBankWrBursts::9 9634 # Per bank write bursts +system.physmem.perBankWrBursts::10 8942 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8881 # Per bank write bursts +system.physmem.perBankWrBursts::13 9361 # Per bank write bursts +system.physmem.perBankWrBursts::14 9018 # Per bank write bursts +system.physmem.perBankWrBursts::15 9072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827025186500 # Total gap between requests +system.physmem.numWrRetry 58 # Number of times write queue was full causing retry +system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2993 # Read request sizes (log2) +system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168384 # Read request sizes (log2) +system.physmem.readPktSize::6 172624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163068 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,175 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads -system.physmem.totQLat 2011805750 # Total ticks spent queuing -system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6349 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads +system.physmem.totQLat 2104910750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing -system.physmem.readRowHits 141825 # Number of row buffer hits during reads -system.physmem.writeRowHits 127038 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes -system.physmem.avgGap 8329945.36 # Average gap between requests -system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.379373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing +system.physmem.readRowHits 145058 # Number of row buffer hits during reads +system.physmem.writeRowHits 112529 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes +system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.422846 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.289511 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.324331 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -347,15 +333,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46965884 # Number of BP lookups -system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits +system.cpu.branchPred.lookups 46937284 # Number of BP lookups +system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -386,45 +372,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9687 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9687 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9687 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9687 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9687 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 207947000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 207947000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 207947000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6190 82.28% 82.28% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1333 17.72% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7523 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9687 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 9923 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9923 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9923 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9923 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9923 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 230116500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 230116500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 230116500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6339 81.70% 81.70% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1420 18.30% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7759 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9923 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9687 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7523 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7759 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7523 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17210 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7759 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17682 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24601959 # DTB read hits -system.cpu.checker.dtb.read_misses 8249 # DTB read misses -system.cpu.checker.dtb.write_hits 19645805 # DTB write hits -system.cpu.checker.dtb.write_misses 1438 # DTB write misses +system.cpu.checker.dtb.read_hits 24588859 # DTB read hits +system.cpu.checker.dtb.read_misses 8478 # DTB read misses +system.cpu.checker.dtb.write_hits 19638229 # DTB write hits +system.cpu.checker.dtb.write_misses 1445 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4297 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4321 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24610208 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19647243 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24597337 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19639674 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44247764 # DTB hits -system.cpu.checker.dtb.misses 9687 # DTB misses -system.cpu.checker.dtb.accesses 44257451 # DTB accesses +system.cpu.checker.dtb.hits 44227088 # DTB hits +system.cpu.checker.dtb.misses 9923 # DTB misses +system.cpu.checker.dtb.accesses 44237011 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -459,9 +445,9 @@ system.cpu.checker.itb.walker.walksShort 4826 # Ta system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 207571000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 207571000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 207571000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::samples 229704000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 229704000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 229704000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated @@ -472,7 +458,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115911347 # ITB inst hits +system.cpu.checker.itb.inst_hits 115853330 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -489,11 +475,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115916173 # ITB inst accesses -system.cpu.checker.itb.hits 115911347 # DTB hits +system.cpu.checker.itb.inst_accesses 115858156 # ITB inst accesses +system.cpu.checker.itb.hits 115853330 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115916173 # DTB accesses -system.cpu.checker.numCycles 139170806 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115858156 # DTB accesses +system.cpu.checker.numCycles 139105254 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -525,81 +511,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 69937 # Table walker walks requested -system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72371 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25472400 # DTB read hits -system.cpu.dtb.read_misses 60528 # DTB read misses -system.cpu.dtb.write_hits 19920178 # DTB write hits -system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_misses 62291 # DTB read misses +system.cpu.dtb.write_hits 19915387 # DTB write hits +system.cpu.dtb.write_misses 10080 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532928 # DTB read accesses -system.cpu.dtb.write_accesses 19929587 # DTB write accesses +system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45392578 # DTB hits -system.cpu.dtb.misses 69937 # DTB misses -system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.misses 72371 # DTB misses +system.cpu.dtb.accesses 45449628 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -629,55 +618,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11957 # Table walker walks requested -system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11974 # Table walker walks requested +system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66242388 # ITB inst hits -system.cpu.itb.inst_misses 11957 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66270436 # ITB inst hits +system.cpu.itb.inst_misses 11974 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -686,98 +676,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66254345 # ITB inst accesses -system.cpu.itb.hits 66242388 # DTB hits -system.cpu.itb.misses 11957 # DTB misses -system.cpu.itb.accesses 66254345 # DTB accesses -system.cpu.numCycles 260505842 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66282410 # ITB inst accesses +system.cpu.itb.hits 66270436 # DTB hits +system.cpu.itb.misses 11974 # DTB misses +system.cpu.itb.accesses 66282410 # DTB accesses +system.cpu.numCycles 263104506 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -785,44 +775,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -846,101 +836,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued -system.cpu.iq.rate 0.550386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.rate 0.544758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200965 # number of nop insts executed -system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544582 # Number of branches executed -system.cpu.iew.exec_stores 20883032 # Number of stores executed -system.cpu.iew.exec_rate 0.546767 # Inst execution rate -system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301991 # num instructions producing a value -system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value +system.cpu.iew.exec_nop 201053 # number of nop insts executed +system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_branches 26530134 # Number of branches executed +system.cpu.iew.exec_stores 20877849 # Number of stores executed +system.cpu.iew.exec_rate 0.541163 # Inst execution rate +system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271750 # num instructions producing a value +system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113361853 # Number of instructions committed -system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113305988 # Number of instructions committed +system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45532382 # Number of memory references committed -system.cpu.commit.loads 24928817 # Number of loads committed -system.cpu.commit.membars 814713 # Number of memory barriers committed -system.cpu.commit.branches 26060941 # Number of branches committed +system.cpu.commit.refs 45511652 # Number of memory references committed +system.cpu.commit.loads 24916104 # Number of loads committed +system.cpu.commit.membars 814017 # Number of memory barriers committed +system.cpu.commit.branches 26045610 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896517 # Number of function calls committed. +system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892502 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -964,214 +954,214 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373323554 # The number of ROB reads -system.cpu.rob.rob_writes 293054802 # The number of ROB writes -system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113206948 # Number of Instructions Simulated -system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155872747 # number of integer regfile reads -system.cpu.int_regfile_writes 88664447 # number of integer regfile writes -system.cpu.fp_regfile_reads 9607 # number of floating regfile reads +system.cpu.rob.rob_reads 375672050 # The number of ROB reads +system.cpu.rob.rob_writes 292972268 # The number of ROB writes +system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113151083 # Number of Instructions Simulated +system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_writes 88633022 # number of integer regfile writes +system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503168369 # number of cc regfile reads -system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes -system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837844 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502981884 # number of cc regfile reads +system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes +system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839617 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits -system.cpu.dcache.overall_hits::total 39264228 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses -system.cpu.dcache.overall_misses::total 4453577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7397 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # 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average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks +system.cpu.dcache.writebacks::total 696320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # 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Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64258114 # 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miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029915 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029915 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13507.381187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13507.381187 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2017 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # 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number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87002 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87002 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87002 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87002 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22163460869 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22163460869 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98730 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65075.133005 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3019277 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163872 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5229.614939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.757349 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155608 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.079798 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2965 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6995 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54988 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # 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number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 20 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # 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number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1558,65 +1548,61 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65703 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.010231 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 62589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3525674 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 36444 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3526784 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36501 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1637,11 +1623,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1662,11 +1648,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1706,52 +1692,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses -system.iocache.demand_misses::total 220 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 220 # number of overall misses -system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses +system.iocache.demand_misses::total 233 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 233 # number of overall misses +system.iocache.overall_misses::total 233 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1760,40 +1746,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1802,66 +1788,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67820 # Transaction distribution -system.membus.trans_dist::ReadResp 67819 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126844 # Transaction distribution +system.membus.trans_dist::ReadReq 68566 # Transaction distribution +system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131056 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution -system.membus.trans_dist::ReadExReq 135185 # Transaction distribution -system.membus.trans_dist::ReadExResp 135185 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution +system.membus.trans_dist::ReadExReq 138681 # Transaction distribution +system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336478 # Request fanout histogram +system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoop_fanout::samples 345038 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336478 # Request fanout histogram -system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1895,6 +1881,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 069845b38..3cbfaeabe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825254 # Number of seconds simulated -sim_ticks 2825254262000 # Number of ticks simulated -final_tick 2825254262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.625396 # Number of seconds simulated +sim_ticks 2625395606000 # Number of ticks simulated +final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94727 # Simulator instruction rate (inst/s) -host_op_rate 114921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2228089891 # Simulator tick rate (ticks/s) -host_mem_usage 647304 # Number of bytes of host memory used -host_seconds 1268.02 # Real time elapsed on the host -sim_insts 120114928 # Number of instructions simulated -sim_ops 145721614 # Number of ops (including micro ops) simulated +host_inst_rate 95828 # Simulator instruction rate (inst/s) +host_op_rate 116265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2090645655 # Simulator tick rate (ticks/s) +host_mem_usage 649348 # Number of bytes of host memory used +host_seconds 1255.78 # Real time elapsed on the host +sim_insts 120339436 # Number of instructions simulated +sim_ops 146004136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1295328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1287356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8203456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1180896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1238652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8338496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 192592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 613216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 685312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 327120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 750304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 683328 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12280396 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1295328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 192592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1487920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8689216 # Number of bytes written to this memory +system.physmem.bytes_read::total 12522572 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1180896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 327120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1508016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8921792 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8706960 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8939536 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 20697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3076 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10708 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10677 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 194742 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135769 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139403 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140205 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 458482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 455660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2903617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 68168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 217048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 242566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4346652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 458482 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 68168 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 526650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3075552 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6266 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3081832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3075552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 458482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 461927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2903617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 68168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 217062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 242566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7428484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 194742 # Number of read requests accepted -system.physmem.writeReqs 176429 # Number of write requests accepted -system.physmem.readBursts 194742 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12454272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue -system.physmem.bytesWritten 10909824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12280396 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11025296 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5937 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13544 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12112 # Per bank write bursts -system.physmem.perBankRdBursts::1 11748 # Per bank write bursts -system.physmem.perBankRdBursts::2 12331 # Per bank write bursts -system.physmem.perBankRdBursts::3 12396 # Per bank write bursts -system.physmem.perBankRdBursts::4 14329 # Per bank write bursts -system.physmem.perBankRdBursts::5 12174 # Per bank write bursts -system.physmem.perBankRdBursts::6 12464 # Per bank write bursts -system.physmem.perBankRdBursts::7 12653 # Per bank write bursts -system.physmem.perBankRdBursts::8 12280 # Per bank write bursts -system.physmem.perBankRdBursts::9 12648 # Per bank write bursts -system.physmem.perBankRdBursts::10 12320 # Per bank write bursts -system.physmem.perBankRdBursts::11 11195 # Per bank write bursts -system.physmem.perBankRdBursts::12 11560 # Per bank write bursts -system.physmem.perBankRdBursts::13 11958 # Per bank write bursts -system.physmem.perBankRdBursts::14 11562 # Per bank write bursts -system.physmem.perBankRdBursts::15 10868 # Per bank write bursts -system.physmem.perBankWrBursts::0 10717 # Per bank write bursts -system.physmem.perBankWrBursts::1 10772 # Per bank write bursts -system.physmem.perBankWrBursts::2 11107 # Per bank write bursts -system.physmem.perBankWrBursts::3 11182 # Per bank write bursts -system.physmem.perBankWrBursts::4 10467 # Per bank write bursts -system.physmem.perBankWrBursts::5 10805 # Per bank write bursts -system.physmem.perBankWrBursts::6 10968 # Per bank write bursts -system.physmem.perBankWrBursts::7 10867 # Per bank write bursts -system.physmem.perBankWrBursts::8 10652 # Per bank write bursts -system.physmem.perBankWrBursts::9 11077 # Per bank write bursts -system.physmem.perBankWrBursts::10 11118 # Per bank write bursts -system.physmem.perBankWrBursts::11 10634 # Per bank write bursts -system.physmem.perBankWrBursts::12 10720 # Per bank write bursts -system.physmem.perBankWrBursts::13 10162 # Per bank write bursts -system.physmem.perBankWrBursts::14 9784 # Per bank write bursts -system.physmem.perBankWrBursts::15 9434 # Per bank write bursts +system.physmem.num_writes::total 143839 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 449797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 471796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3176091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 285787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 260276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4769785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 574396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3398266 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3405024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3398266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 478540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3176091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 285802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 260276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8174809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198527 # Number of read requests accepted +system.physmem.writeReqs 180063 # Number of write requests accepted +system.physmem.readBursts 198527 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 180063 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12696000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.bytesWritten 10018560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12522636 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11257872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23492 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14407 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12827 # Per bank write bursts +system.physmem.perBankRdBursts::1 12491 # Per bank write bursts +system.physmem.perBankRdBursts::2 12947 # Per bank write bursts +system.physmem.perBankRdBursts::3 12890 # Per bank write bursts +system.physmem.perBankRdBursts::4 14947 # Per bank write bursts +system.physmem.perBankRdBursts::5 12185 # Per bank write bursts +system.physmem.perBankRdBursts::6 12844 # Per bank write bursts +system.physmem.perBankRdBursts::7 12385 # Per bank write bursts +system.physmem.perBankRdBursts::8 12025 # Per bank write bursts +system.physmem.perBankRdBursts::9 12120 # Per bank write bursts +system.physmem.perBankRdBursts::10 11888 # Per bank write bursts +system.physmem.perBankRdBursts::11 11181 # Per bank write bursts +system.physmem.perBankRdBursts::12 11694 # Per bank write bursts +system.physmem.perBankRdBursts::13 12452 # Per bank write bursts +system.physmem.perBankRdBursts::14 11831 # Per bank write bursts +system.physmem.perBankRdBursts::15 11668 # Per bank write bursts +system.physmem.perBankWrBursts::0 10196 # Per bank write bursts +system.physmem.perBankWrBursts::1 10156 # Per bank write bursts +system.physmem.perBankWrBursts::2 10450 # Per bank write bursts +system.physmem.perBankWrBursts::3 10103 # Per bank write bursts +system.physmem.perBankWrBursts::4 9839 # Per bank write bursts +system.physmem.perBankWrBursts::5 9619 # Per bank write bursts +system.physmem.perBankWrBursts::6 10216 # Per bank write bursts +system.physmem.perBankWrBursts::7 9774 # Per bank write bursts +system.physmem.perBankWrBursts::8 9494 # Per bank write bursts +system.physmem.perBankWrBursts::9 9611 # Per bank write bursts +system.physmem.perBankWrBursts::10 9445 # Per bank write bursts +system.physmem.perBankWrBursts::11 9199 # Per bank write bursts +system.physmem.perBankWrBursts::12 9616 # Per bank write bursts +system.physmem.perBankWrBursts::13 9900 # Per bank write bursts +system.physmem.perBankWrBursts::14 9667 # Per bank write bursts +system.physmem.perBankWrBursts::15 9255 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2825253981000 # Total gap between requests +system.physmem.numWrRetry 63 # Number of times write queue was full causing retry +system.physmem.totGap 2625395343000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 191072 # Read request sizes (log2) +system.physmem.readPktSize::6 194857 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171993 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 246 # What read queue length does an incoming req see +system.physmem.writePktSize::6 175627 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 264 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,160 +188,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 261.529865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.433799 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.548299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46507 52.06% 52.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17145 19.19% 71.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5910 6.62% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3229 3.61% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2663 2.98% 84.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1401 1.57% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 977 1.09% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1056 1.18% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10448 11.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7194 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.049903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 528.366464 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7192 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7194 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7194 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.695580 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.063476 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.872294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 6078 84.49% 84.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 276 3.84% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 196 2.72% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 78 1.08% 92.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 140 1.95% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 36 0.50% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 37 0.51% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 44 0.61% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 68 0.95% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 17 0.24% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 97 1.35% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.19% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 17 0.24% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 12 0.17% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 42 0.58% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 10 0.14% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 8 0.11% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.06% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7194 # Writes before turning the bus around for reads -system.physmem.totQLat 6681295250 # Total ticks spent queuing -system.physmem.totMemAccLat 10330007750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 972990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34333.83 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 224 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 247.658515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 138.206739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 311.047088 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48645 53.04% 53.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18050 19.68% 72.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5879 6.41% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3418 3.73% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2896 3.16% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1497 1.63% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 939 1.02% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1042 1.14% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9351 10.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91717 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6649 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.834862 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.193500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6647 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6649 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.543390 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.659302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 38.965105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6283 94.50% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 92 1.38% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 34 0.51% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 28 0.42% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 36 0.54% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 35 0.53% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.20% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.26% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.06% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.26% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 15 0.23% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.18% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 5 0.08% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 13 0.20% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6649 # Writes before turning the bus around for reads +system.physmem.totQLat 7005041065 # Total ticks spent queuing +system.physmem.totMemAccLat 10724572315 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35312.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53083.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.35 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54062.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing -system.physmem.readRowHits 162654 # Number of row buffer hits during reads -system.physmem.writeRowHits 113073 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.32 # Row buffer hit rate for writes -system.physmem.avgGap 7611731.47 # Average gap between requests -system.physmem.pageHitRate 75.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 347571000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189646875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 781614600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 563014800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79272493785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625612031750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891297877370 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.427007 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704246406250 # Time in different power states -system.physmem_0.memoryStateTime::REF 94341260000 # Time in different power states +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.13 # Average write queue length when enqueuing +system.physmem.readRowHits 165504 # Number of row buffer hits during reads +system.physmem.writeRowHits 97693 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.40 # Row buffer hit rate for writes +system.physmem.avgGap 6934666.38 # Average gap between requests +system.physmem.pageHitRate 74.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 361050480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197001750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 807424800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 520687440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 75248496990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1509227374500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1757839822440 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.553437 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2510629171267 # Time in different power states +system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26661192500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27094642483 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 327809160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178864125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 736242000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 541604880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78684430770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626127876500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891128331995 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.366996 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705112983500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94341260000 # Time in different power states +system.physmem_1.actEnergy 332330040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181330875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 739892400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 493691760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74790166545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1509629418750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1757644616850 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.479084 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2511304272827 # Time in different power states +system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25799982000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26423733173 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -352,30 +353,30 @@ system.realview.nvmem.bytes_inst_read::total 320 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 23750953 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15527618 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 965372 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14472059 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10661692 # Number of BTB hits +system.cpu0.branchPred.lookups 51768532 # Number of BP lookups +system.cpu0.branchPred.condPredicted 23412360 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 919881 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 31255966 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 23302169 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.670872 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3843618 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32002 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.552708 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15318582 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29481 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,87 +407,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 61986 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 61986 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26264 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18370 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 17352 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 336.413945 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2220.174334 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43963 98.50% 98.50% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 507 1.14% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 73 0.16% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.14% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 13427 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 7972.648842 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 6416.497879 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8239.915942 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 13383 99.67% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 25 0.19% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.07% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 13427 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 89356407948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.591290 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.497127 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 36606156956 40.97% 40.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 52714291992 58.99% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2 18812000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::3 8121500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4 2346000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::5 1919500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6 1535000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::7 979500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8 384000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::9 515500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10 241000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::11 224500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12 422000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::13 109500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14 86500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::15 262500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 89356407948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4894 78.56% 78.56% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1336 21.44% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6230 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61986 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 62660 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 62660 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24194 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18908 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 19558 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 43102 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 433.564568 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2585.553866 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-4095 41662 96.66% 96.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::4096-8191 436 1.01% 97.67% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-12287 432 1.00% 98.67% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::12288-16383 320 0.74% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-20479 76 0.18% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::20480-24575 60 0.14% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-28671 79 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::28672-32767 9 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-36863 4 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-45055 16 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::45056-49151 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-53247 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 43102 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 15681 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9053.791276 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7430.926564 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8773.860990 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14744 94.02% 94.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 873 5.57% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 41 0.26% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 10 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 7 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 15681 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 91363987860 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.449877 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.503999 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 91318747860 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 34013000 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 5422000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3241000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1011500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 587500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 452000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 12000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 91363987860 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5167 76.75% 76.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1565 23.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6732 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62660 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61986 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6230 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62660 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6732 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6230 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 68216 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6732 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 69392 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17554590 # DTB read hits -system.cpu0.dtb.read_misses 54209 # DTB read misses -system.cpu0.dtb.write_hits 14392399 # DTB write hits -system.cpu0.dtb.write_misses 7777 # DTB write misses +system.cpu0.dtb.read_hits 22710900 # DTB read hits +system.cpu0.dtb.read_misses 53664 # DTB read misses +system.cpu0.dtb.write_hits 16914206 # DTB write hits +system.cpu0.dtb.write_misses 8996 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 317 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2330 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3521 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 84 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1885 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17608799 # DTB read accesses -system.cpu0.dtb.write_accesses 14400176 # DTB write accesses +system.cpu0.dtb.perms_faults 828 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 22764564 # DTB read accesses +system.cpu0.dtb.write_accesses 16923202 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31946989 # DTB hits -system.cpu0.dtb.misses 61986 # DTB misses -system.cpu0.dtb.accesses 32008975 # DTB accesses +system.cpu0.dtb.hits 39625106 # DTB hits +system.cpu0.dtb.misses 62660 # DTB misses +system.cpu0.dtb.accesses 39687766 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -516,62 +516,59 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10002 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10002 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3947 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 65 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9937 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 314.380598 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 1718.762352 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-2047 9514 95.74% 95.74% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::2048-4095 89 0.90% 96.64% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-6143 92 0.93% 97.56% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::6144-8191 156 1.57% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-10239 23 0.23% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::10240-12287 21 0.21% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-14335 10 0.10% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::14336-16383 9 0.09% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-18431 7 0.07% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::18432-20479 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-22527 2 0.02% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::22528-24575 4 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-26623 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::26624-28671 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9937 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2600 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9117.887308 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7551.234816 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5655.414847 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1525 58.65% 58.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 976 37.54% 96.19% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 32 1.23% 97.42% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 60 2.31% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2600 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 20627596212 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.981751 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.134001 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 376836000 1.83% 1.83% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 20250383712 98.17% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 360000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 20627596212 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2218 87.50% 87.50% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 317 12.50% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2535 # Table walker page sizes translated +system.cpu0.itb.walker.walks 9923 # Table walker walks requested +system.cpu0.itb.walker.walksShort 9923 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3743 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6075 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 105 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9818 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 399.113872 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2107.706971 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9439 96.14% 96.14% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 239 2.43% 98.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 79 0.80% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 28 0.29% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 10 0.10% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 11 0.11% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 5 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9818 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2687 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10340.528470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8874.826622 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6037.575177 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 928 34.54% 34.54% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1618 60.22% 94.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 45 1.67% 96.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.16% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2687 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 18349502828 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.974755 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.157116 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 463854500 2.53% 2.53% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17885129828 97.47% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 423500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 95000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 18349502828 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2262 87.61% 87.61% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.39% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2582 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10002 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10002 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9923 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2535 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2535 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 12537 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 37321844 # ITB inst hits -system.cpu0.itb.inst_misses 10002 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2582 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 12505 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 70918524 # ITB inst hits +system.cpu0.itb.inst_misses 9923 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -580,500 +577,500 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37331846 # ITB inst accesses -system.cpu0.itb.hits 37321844 # DTB hits -system.cpu0.itb.misses 10002 # DTB misses -system.cpu0.itb.accesses 37331846 # DTB accesses -system.cpu0.numCycles 127490392 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70928447 # ITB inst accesses +system.cpu0.itb.hits 70918524 # DTB hits +system.cpu0.itb.misses 9923 # DTB misses +system.cpu0.itb.accesses 70928447 # DTB accesses +system.cpu0.numCycles 192710246 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18416586 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 111347815 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 23750953 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14505310 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 103542853 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2791794 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 127823 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 53549 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 359263 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 418714 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 68477 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37322509 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 269100 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3836 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 124383162 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.079346 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.261981 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19172907 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 190300440 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 51768532 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 38620751 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 166603353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5605830 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133760 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 54794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 348448 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 420234 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 74628 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 70919147 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257234 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4157 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 189611039 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.227807 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.311092 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62596919 50.33% 50.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21226112 17.07% 67.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8654044 6.96% 74.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 31906087 25.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 87830492 46.32% 46.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 29214542 15.41% 61.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14106780 7.44% 69.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 58459225 30.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 124383162 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.186296 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.873382 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19346102 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58140113 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 40971754 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4869688 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1055505 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3027271 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 344448 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 109400605 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3934770 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1055505 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25005985 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11977086 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36202111 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40046327 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10096148 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 104386948 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1045357 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1411792 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 159433 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 59086 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5966912 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 108436619 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 476371377 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 119317721 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9226 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 97033193 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11403415 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1211111 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1071444 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12097609 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18549268 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 15931724 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1681801 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2123013 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 101474466 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1673346 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 99505309 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 475979 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8870309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22101778 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 120255 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 124383162 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.799990 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.034146 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 189611039 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.268634 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.987495 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24427882 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 101305691 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 56642715 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4754811 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2479940 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 2942193 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 327073 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 148781526 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3762312 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2479940 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 32842566 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11912016 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 79322122 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 52855770 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10198625 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 132285921 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1008096 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1377906 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 148604 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 51873 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6170558 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 135790293 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 611071310 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 146878490 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9376 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 124889963 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10900327 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2656202 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2518524 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22032615 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 23644678 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 18416726 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1638849 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2450280 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 129422072 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8506052 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.672916 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.964306 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 68905319 55.40% 55.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 22874220 18.39% 73.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22288669 17.92% 91.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9206102 7.40% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1108815 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 115784330 61.06% 61.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 32509497 17.15% 78.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 29946391 15.79% 94.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10293248 5.43% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1077539 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 124383162 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189611039 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9283826 40.69% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 70 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5520798 24.20% 64.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8011764 35.11% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10302435 44.02% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 127 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5400760 23.08% 67.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 7700326 32.90% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2266 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 65682798 66.01% 66.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 92825 0.09% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8012 0.01% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18253823 18.34% 84.46% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15465584 15.54% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 86139109 67.51% 67.51% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 105637 0.08% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7185 0.01% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 23381898 18.33% 85.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 17956248 14.07% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 99505309 # Type of FU issued -system.cpu0.iq.rate 0.780493 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 22816458 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229299 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 346654844 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 112025701 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 97442801 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 31372 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11049 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9514 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 122299120 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20381 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 360751 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 127592349 # Type of FU issued +system.cpu0.iq.rate 0.662094 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 139596675 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 150972031 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21694 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349342 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1973339 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2498 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18704 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1001610 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1883137 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2543 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18891 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 974261 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 104951 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 329906 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 112825 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 327783 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1055505 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1579113 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 185823 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 103314574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2479940 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1553148 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 173644 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 131254258 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18549268 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 15931724 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 862014 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 287589 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 683109 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 23644678 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 18416726 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 851019 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 166762 # number of nop insts executed -system.cpu0.iew.exec_refs 33081779 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16674739 # Number of branches executed -system.cpu0.iew.exec_stores 15278173 # Number of stores executed -system.cpu0.iew.exec_rate 0.772009 # Inst execution rate -system.cpu0.iew.wb_sent 97898733 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 97452315 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 50771632 # num instructions producing a value -system.cpu0.iew.wb_consumers 83764488 # num instructions consuming a value +system.cpu0.iew.exec_nop 171188 # number of nop insts executed +system.cpu0.iew.exec_refs 40733276 # number of memory reference insts executed +system.cpu0.iew.exec_branches 24565455 # Number of branches executed +system.cpu0.iew.exec_stores 17777509 # Number of stores executed +system.cpu0.iew.exec_rate 0.656753 # Inst execution rate +system.cpu0.iew.wb_sent 126045909 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 124138382 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 63204033 # num instructions producing a value +system.cpu0.iew.wb_consumers 102166760 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.764389 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.606124 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.644171 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618636 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8390139 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1553091 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 624980 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 122653513 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.765118 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.477688 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9496881 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1543776 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 596906 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186488308 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.647310 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.345681 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 78804860 64.25% 64.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24438835 19.93% 84.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8183554 6.67% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3164514 2.58% 93.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3412948 2.78% 96.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1509244 1.23% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1121963 0.91% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 525683 0.43% 98.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1491912 1.22% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 128655160 68.99% 68.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 31929494 17.12% 86.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12238036 6.56% 92.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3079239 1.65% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4650991 2.49% 96.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2566190 1.38% 98.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1394957 0.75% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 526048 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1448193 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 122653513 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78072085 # Number of instructions committed -system.cpu0.commit.committedOps 93844352 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186488308 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 99634335 # Number of instructions committed +system.cpu0.commit.committedOps 120715819 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31506042 # Number of memory references committed -system.cpu0.commit.loads 16575928 # Number of loads committed -system.cpu0.commit.membars 642248 # Number of memory barriers committed -system.cpu0.commit.branches 16047033 # Number of branches committed -system.cpu0.commit.fp_insts 9500 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 80932371 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1914804 # Number of function calls committed. +system.cpu0.commit.refs 39204006 # Number of memory references committed +system.cpu0.commit.loads 21761541 # Number of loads committed +system.cpu0.commit.membars 628761 # Number of memory barriers committed +system.cpu0.commit.branches 23967170 # Number of branches committed +system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 105564175 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4749359 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62239958 66.32% 66.32% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 90340 0.10% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8012 0.01% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16575928 17.66% 84.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 14930114 15.91% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 81401150 67.43% 67.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 103478 0.09% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7185 0.01% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 21761541 18.03% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 17442465 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 93844352 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1491912 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 219244998 # The number of ROB reads -system.cpu0.rob.rob_writes 206197797 # The number of ROB writes -system.cpu0.timesIdled 126478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3107230 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5523018391 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 77956509 # Number of Instructions Simulated -system.cpu0.committedOps 93728776 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.635404 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.635404 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.611470 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.611470 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 109237443 # number of integer regfile reads -system.cpu0.int_regfile_writes 59093647 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8049 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2136 # number of floating regfile writes -system.cpu0.cc_regfile_reads 346833598 # number of cc regfile reads -system.cpu0.cc_regfile_writes 40564465 # number of cc regfile writes -system.cpu0.misc_regfile_reads 243214174 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1207250 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 702516 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.143728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28480758 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 703028 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.511556 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 256726000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.143728 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970984 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.970984 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 292184577 # The number of ROB reads +system.cpu0.rob.rob_writes 263546817 # The number of ROB writes +system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3099207 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5058081346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 99512641 # Number of Instructions Simulated +system.cpu0.committedOps 120594125 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.936540 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.936540 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.516385 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.516385 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 137143613 # number of integer regfile reads +system.cpu0.int_regfile_writes 78685231 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8206 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes +system.cpu0.cc_regfile_reads 446712527 # number of cc regfile reads +system.cpu0.cc_regfile_writes 47224279 # number of cc regfile writes +system.cpu0.misc_regfile_reads 373664445 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1193481 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 673244 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.859625 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 36215686 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 673756 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.751931 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 278115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.859625 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946991 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.946991 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62650967 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62650967 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15440226 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15440226 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11830536 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11830536 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306667 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 306667 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 359893 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 359893 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 358331 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 358331 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27270762 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27270762 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27577429 # number of overall hits -system.cpu0.dcache.overall_hits::total 27577429 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 630655 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 630655 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1827082 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1827082 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147933 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147933 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25364 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25364 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20059 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20059 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2457737 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2457737 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2605670 # number of overall misses -system.cpu0.dcache.overall_misses::total 2605670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8272706723 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8272706723 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25439418868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25439418868 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389472743 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 389472743 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444610334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444610334 # number of StoreCondReq miss cycles +system.cpu0.dcache.tags.tag_accesses 77975696 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 77975696 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 20636575 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 20636575 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14390339 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14390339 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296451 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 296451 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354772 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 354772 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351523 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 351523 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 35026914 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 35026914 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35323365 # number of overall hits +system.cpu0.dcache.overall_hits::total 35323365 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 606585 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 606585 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1800589 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1800589 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141770 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141770 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24267 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24267 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21226 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21226 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2407174 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2407174 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2548944 # number of overall misses +system.cpu0.dcache.overall_misses::total 2548944 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8152337496 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8152337496 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26333386263 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26333386263 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385690944 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 385690944 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485736540 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485736540 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 33712125591 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 33712125591 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 33712125591 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 33712125591 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16070881 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16070881 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13657618 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13657618 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 454600 # 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average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13439.728144 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14624.873451 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14624.873451 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15893.639263 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15893.639263 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22884.035617 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22884.035617 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13716.734374 # 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average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13529.416009 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13529.416009 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 842 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3715311 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 190617 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.541667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 19.490974 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 508420 # number of writebacks -system.cpu0.dcache.writebacks::total 508420 # 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number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3183836000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3183836000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7398897000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7398897000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023939 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023939 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023309 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023309 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225128 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225128 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016823 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016823 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053011 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053011 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026684 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026684 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10630.280081 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10630.280081 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15557.354604 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15557.354604 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15268.191317 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15268.191317 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14603.224965 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14603.224965 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20133.090682 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20133.090682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 491598 # 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number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452955960 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452955960 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 405000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 405000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9368097063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9368097063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10938124765 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10938124765 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5613897000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5613897000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4260937012 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4260937012 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9874834012 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9874834012 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017253 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019273 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019273 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224574 # 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average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11257.631689 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16798.862885 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16798.862885 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15953.458405 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.458405 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15033.911452 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15033.911452 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21339.675869 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21339.675869 # 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miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034727 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034727 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034727 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034727 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034727 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.227931 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.227931 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9851.227931 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9851.227931 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1314207 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 320 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 107284 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.249795 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 143036633 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 143036633 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69666497 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69666497 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69666497 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69666497 # 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average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36393.851676 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30094.475574 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48180.926443 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210650 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22380.478778 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29128.987054 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65232.824954 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19483.134431 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19483.134431 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14962.568676 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.568676 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 160999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 160999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40778.326071 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40778.326071 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31592.482214 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50172.703537 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1513,68 +1518,65 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1959682 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1897898 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 508419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 329547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 131 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88597 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112274 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 292255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 279169 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2512932 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2353027 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27983 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 115316 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5009258 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80268960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 85221321 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 209248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 165747753 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 677561 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3234113 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.173543 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.378716 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1908189 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1835262 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 491597 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 299764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 91875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43573 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284602 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270315 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2416584 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2311982 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27986 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112626 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4869178 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77186016 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82205272 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48372 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202464 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 159642124 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 659500 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3123483 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.174208 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.379288 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2672856 82.65% 82.65% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 561257 17.35% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2579348 82.58% 82.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 544135 17.42% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3234113 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1876283497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3123483 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1823730646 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114853000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 112580498 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1888093495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1815085939 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1210751284 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1180413157 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15934735 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15906731 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63036190 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 62058933 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 34134097 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11727075 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 316019 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18898892 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 15069568 # Number of BTB hits +system.cpu1.branchPred.lookups 6179090 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3881916 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 362855 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3346788 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2458848 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.737839 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12517859 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7561 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.468890 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1048082 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 10606 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1604,91 +1606,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 23600 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 23600 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8914 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6871 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7815 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 15785 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 672.093760 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3265.172364 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 14984 94.93% 94.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 394 2.50% 97.42% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 71 0.45% 97.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 205 1.30% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 14 0.09% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.19% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 46 0.29% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 19 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.10% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 15785 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 7948.780916 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 6651.023666 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5565.886785 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4665 77.96% 77.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 897 14.99% 92.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 299 5.00% 97.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 93 1.55% 99.50% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 7 0.12% 99.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 21 0.35% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 2 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 71907287764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.149161 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.363512 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 61231753172 85.15% 85.15% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 10656881592 14.82% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 10600500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3048000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1243000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 909500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 707500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 390500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 165000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 220500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 87000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 114500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 127500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 62500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 410000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 567000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 71907287764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2101 76.21% 76.21% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 656 23.79% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2757 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23600 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 24514 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 24514 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11457 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6002 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7055 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 17459 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 393.464689 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2513.400268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 16937 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 156 0.89% 97.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 187 1.07% 98.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 85 0.49% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 23 0.13% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 6 0.03% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 44 0.25% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 3 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 17459 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5476 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9377.190285 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8039.034346 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5934.391980 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2488 45.43% 45.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2481 45.31% 90.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 381 6.96% 97.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 96 1.75% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 6 0.11% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 20 0.37% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5476 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 69614954880 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.366193 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.484439 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 44157971700 63.43% 63.43% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 25439149180 36.54% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 11249000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3199000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 940000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 768000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 744500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 290500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 107000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 122500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 85500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 64000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 71500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 31000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 135000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 69614954880 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1964 73.78% 73.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 698 26.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2662 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24514 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23600 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2757 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24514 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2662 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2757 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26357 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2662 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 27176 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10322903 # DTB read hits -system.cpu1.dtb.read_misses 19223 # DTB read misses -system.cpu1.dtb.write_hits 6788033 # DTB write hits -system.cpu1.dtb.write_misses 4377 # DTB write misses +system.cpu1.dtb.read_hits 5241297 # DTB read hits +system.cpu1.dtb.read_misses 21288 # DTB read misses +system.cpu1.dtb.write_hits 4318497 # DTB write hits +system.cpu1.dtb.write_misses 3226 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2089 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 54 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 72 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 621 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 398 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10342126 # DTB read accesses -system.cpu1.dtb.write_accesses 6792410 # DTB write accesses +system.cpu1.dtb.perms_faults 379 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5262585 # DTB read accesses +system.cpu1.dtb.write_accesses 4321723 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17110936 # DTB hits -system.cpu1.dtb.misses 23600 # DTB misses -system.cpu1.dtb.accesses 17134536 # DTB accesses +system.cpu1.dtb.hits 9559794 # DTB hits +system.cpu1.dtb.misses 24514 # DTB misses +system.cpu1.dtb.accesses 9584308 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,65 +1720,67 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7135 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7135 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4170 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2894 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 71 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7064 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 161.877123 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1382.094776 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 6918 97.93% 97.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 45 0.64% 98.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 37 0.52% 99.09% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 22 0.31% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 14 0.20% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 9 0.13% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 3 0.04% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.03% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 1 0.01% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 6863 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6863 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4096 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2697 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 70 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6793 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 193.655233 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1558.039702 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 6647 97.85% 97.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 36 0.53% 98.38% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 98.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 24 0.35% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 16 0.24% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 12 0.18% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 8 0.12% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 3 0.04% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.04% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7064 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1280 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9064.455469 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7676.805908 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5570.114480 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 198 15.47% 15.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 721 56.33% 71.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 25 1.95% 73.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 272 21.25% 95.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 5 0.39% 95.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 10 0.78% 96.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.64% 97.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.48% 99.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.08% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.47% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1280 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16042620916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.990716 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.095951 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 149006264 0.93% 0.93% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 15893540152 99.07% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 74500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16042620916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1033 85.44% 85.44% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 176 14.56% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1209 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::30720-32767 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6793 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1235 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10095.547368 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8796.441001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5908.625766 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 181 14.66% 14.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.17% 28.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 552 44.70% 73.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 256 20.73% 94.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.57% 94.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 7 0.57% 95.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.27% 97.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 18 1.46% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.24% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.40% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.16% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1235 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 18043801328 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.988843 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.105174 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 201557764 1.12% 1.12% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 17842013064 98.88% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 213500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 18043801328 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7135 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6863 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1209 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1209 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8344 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 43998995 # ITB inst hits -system.cpu1.itb.inst_misses 7135 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8028 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10532607 # ITB inst hits +system.cpu1.itb.inst_misses 6863 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1785,499 +1789,499 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1239 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1195 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 569 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 44006130 # ITB inst accesses -system.cpu1.itb.hits 43998995 # DTB hits -system.cpu1.itb.misses 7135 # DTB misses -system.cpu1.itb.accesses 44006130 # DTB accesses -system.cpu1.numCycles 106356723 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10539470 # ITB inst accesses +system.cpu1.itb.hits 10532607 # DTB hits +system.cpu1.itb.misses 6863 # DTB misses +system.cpu1.itb.accesses 10539470 # DTB accesses +system.cpu1.numCycles 43132973 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 10248604 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 110247468 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 34134097 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27587427 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 92894950 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3804096 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79886 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 35043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 199386 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 306315 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 18555 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43998345 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 120822 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2367 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 105684787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.292794 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339203 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9545781 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 31669827 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 6179090 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 3506930 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 31408441 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 995212 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 85708 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 38872 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 217286 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 331419 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 27804 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10531999 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 133008 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2352 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 42152917 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.913975 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225517 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 48118877 45.53% 45.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14213464 13.45% 58.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7642144 7.23% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35710302 33.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 24362526 57.80% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 6315176 14.98% 72.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2214119 5.25% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 9261096 21.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 105684787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.320940 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.036582 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13299736 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62299682 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 27136759 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1184524 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1764086 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 778297 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 140897 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69265057 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1207807 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1764086 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17799261 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2243721 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 57294733 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23798018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2784968 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 56317455 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 239325 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 267963 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37417 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15706 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1709289 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 56195584 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 266063253 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 60158486 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1810 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 53296548 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2899036 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1893782 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1819648 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13269922 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10622155 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7171113 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 643276 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 895479 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 55388735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 607798 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 55019063 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 118019 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2383882 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 6031867 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 50125 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 105684787 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.520596 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.855641 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 42152917 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.143257 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.734237 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8274124 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 20645023 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11553748 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1337865 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 342157 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 880050 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 158552 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 30233981 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1392367 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 342157 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10058392 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2609511 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14923378 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11073163 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3146316 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 28748329 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 284293 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 329352 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 50565 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 19779 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1931384 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 29150261 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 132893523 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 32973401 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1672 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 25705063 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3445198 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 453540 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375844 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3445196 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 5586646 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 4747027 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 699100 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 721726 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 27759685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2799528 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.646658 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.966330 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71804994 67.94% 67.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16804413 15.90% 83.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13307202 12.59% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3472478 3.29% 99.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 295688 0.28% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 26379254 62.58% 62.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7348926 17.43% 80.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5684884 13.49% 93.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2419597 5.74% 99.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 320238 0.76% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 105684787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 42152917 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3013223 44.49% 44.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 670 0.01% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1729221 25.53% 70.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2029703 29.97% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2004888 32.52% 32.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 611 0.01% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1891782 30.69% 63.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2267092 36.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 73 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37421348 68.02% 68.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46238 0.08% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3333 0.01% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10544210 19.16% 87.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7003861 12.73% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 17154225 62.93% 62.93% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 35391 0.13% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4079 0.01% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 5491685 20.15% 83.22% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 4573079 16.78% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 55019063 # Type of FU issued -system.cpu1.iq.rate 0.517307 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6772817 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.123099 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 222607082 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58388753 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53008185 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6667 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2258 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1929 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 61787450 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4357 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94839 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 27258527 # Type of FU issued +system.cpu1.iq.rate 0.631965 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 31195241 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2049 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 107638 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 509093 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10627 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 368944 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 606025 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 849 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10642 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 402770 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 52621 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 79740 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 45923 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 97906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1764086 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 541667 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 103172 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56056220 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 342157 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 666539 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 117242 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 28442190 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10622155 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7171113 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 314475 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9900 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 85548 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10627 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 58910 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 131027 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 189937 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 54736921 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10438101 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 258564 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 5586646 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 4747027 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 329140 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 12736 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 94970 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10642 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 72014 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 152187 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 224201 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 26920844 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 5360548 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 313188 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 59687 # number of nop insts executed -system.cpu1.iew.exec_refs 17373742 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11974777 # Number of branches executed -system.cpu1.iew.exec_stores 6935641 # Number of stores executed -system.cpu1.iew.exec_rate 0.514654 # Inst execution rate -system.cpu1.iew.wb_sent 54589285 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53010114 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25746768 # num instructions producing a value -system.cpu1.iew.wb_consumers 39490922 # num instructions consuming a value +system.cpu1.iew.exec_nop 55032 # number of nop insts executed +system.cpu1.iew.exec_refs 9857010 # number of memory reference insts executed +system.cpu1.iew.exec_branches 4125375 # Number of branches executed +system.cpu1.iew.exec_stores 4496462 # Number of stores executed +system.cpu1.iew.exec_rate 0.624136 # Inst execution rate +system.cpu1.iew.wb_sent 26746276 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 26625754 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 13483465 # num instructions producing a value +system.cpu1.iew.wb_consumers 21315020 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.498418 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.651967 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.617295 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.632580 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3744166 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 557673 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 178057 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103735818 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.501583 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.163784 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2680688 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 573503 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 207406 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 41589167 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.611775 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.358099 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77652029 74.86% 74.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14577800 14.05% 88.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6160967 5.94% 94.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 757264 0.73% 95.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2015553 1.94% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1576437 1.52% 99.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 460071 0.44% 99.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 129756 0.13% 99.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 405941 0.39% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 29454101 70.82% 70.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7064012 16.99% 87.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2119517 5.10% 92.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 873586 2.10% 95.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 770133 1.85% 96.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 442153 1.06% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 274514 0.66% 98.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 148169 0.36% 98.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 442982 1.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103735818 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 42197750 # Number of instructions committed -system.cpu1.commit.committedOps 52032169 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 41589167 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20860008 # Number of instructions committed +system.cpu1.commit.committedOps 25443224 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16915231 # Number of memory references committed -system.cpu1.commit.loads 10113062 # Number of loads committed -system.cpu1.commit.membars 214317 # Number of memory barriers committed -system.cpu1.commit.branches 11798243 # Number of branches committed -system.cpu1.commit.fp_insts 1928 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 46741115 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3380053 # Number of function calls committed. +system.cpu1.commit.refs 9324878 # Number of memory references committed +system.cpu1.commit.loads 4980621 # Number of loads committed +system.cpu1.commit.membars 230323 # Number of memory barriers committed +system.cpu1.commit.branches 3917567 # Number of branches committed +system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 22363157 # Number of committed integer instructions. +system.cpu1.commit.function_calls 552505 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 35068266 67.40% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45339 0.09% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3333 0.01% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10113062 19.44% 86.93% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6802169 13.07% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 16079933 63.20% 63.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 34334 0.13% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4079 0.02% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4980621 19.58% 82.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 4344257 17.07% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 52032169 # Class of committed instruction -system.cpu1.commit.bw_lim_events 405941 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction +system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 139039973 # The number of ROB reads -system.cpu1.rob.rob_writes 113498046 # The number of ROB writes -system.cpu1.timesIdled 59982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 671936 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5543606797 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 42158419 # Number of Instructions Simulated -system.cpu1.committedOps 51992838 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.522787 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.522787 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.396387 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.396387 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 57596911 # number of integer regfile reads -system.cpu1.int_regfile_writes 36337307 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1495 # number of floating regfile reads -system.cpu1.fp_regfile_writes 580 # number of floating regfile writes -system.cpu1.cc_regfile_reads 194912842 # number of cc regfile reads -system.cpu1.cc_regfile_writes 16071052 # number of cc regfile writes -system.cpu1.misc_regfile_reads 208513912 # number of misc regfile reads -system.cpu1.misc_regfile_writes 404751 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 201045 # number of replacements -system.cpu1.dcache.tags.tagsinuse 470.607708 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 16083620 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 201364 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 79.873364 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 93308892000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.607708 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919156 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.919156 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33778764 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33778764 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9715738 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9715738 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6106545 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6106545 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50809 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50809 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81509 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81509 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73252 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73252 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15822283 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15822283 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15873092 # number of overall hits -system.cpu1.dcache.overall_hits::total 15873092 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 224637 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 224637 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 441375 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 441375 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31038 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 31038 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18294 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18294 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 666012 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 666012 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 697050 # number of overall misses -system.cpu1.dcache.overall_misses::total 697050 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3524459329 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3524459329 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10055246312 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10055246312 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 359810249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 359810249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545166265 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 545166265 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 431000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 431000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13579705641 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13579705641 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13579705641 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13579705641 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9940375 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9940375 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6547920 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6547920 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81847 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81847 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 99803 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 99803 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 96921 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 96921 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16488295 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16488295 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16570142 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16570142 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022598 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022598 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067407 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.067407 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.183301 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.183301 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.244209 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.244209 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040393 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040393 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042067 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.042067 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15689.576201 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15689.576201 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22781.639903 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22781.639903 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19668.210834 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19668.210834 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23032.923444 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23032.923444 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 68115809 # The number of ROB reads +system.cpu1.rob.rob_writes 56808236 # The number of ROB writes +system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 980056 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5207108948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 20826795 # Number of Instructions Simulated +system.cpu1.committedOps 25410011 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.071033 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.071033 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.482851 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.482851 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 30054591 # number of integer regfile reads +system.cpu1.int_regfile_writes 16942565 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1393 # number of floating regfile reads +system.cpu1.fp_regfile_writes 518 # number of floating regfile writes +system.cpu1.cc_regfile_reads 96178951 # number of cc regfile reads +system.cpu1.cc_regfile_writes 9490884 # number of cc regfile writes +system.cpu1.misc_regfile_reads 81077063 # number of misc regfile reads +system.cpu1.misc_regfile_writes 422777 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 228827 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.548130 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8439386 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 229141 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.830537 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103436351500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.548130 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934664 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.934664 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18658844 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18658844 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4567362 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4567362 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3580643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3580643 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63652 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 63652 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87547 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87547 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79571 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79571 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8148005 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8148005 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8211657 # number of overall hits +system.cpu1.dcache.overall_hits::total 8211657 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253908 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253908 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 480072 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 480072 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 36130 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 36130 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19184 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19184 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23489 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23489 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 733980 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 733980 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 770110 # number of overall misses +system.cpu1.dcache.overall_misses::total 770110 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4026677920 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4026677920 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11127636122 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11127636122 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 374723986 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 374723986 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547048827 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 547048827 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1003000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1003000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15154314042 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15154314042 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15154314042 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15154314042 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4821270 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4821270 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4060715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4060715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99782 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 99782 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106731 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 106731 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103060 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 103060 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8881985 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8881985 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8981767 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8981767 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.052664 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.052664 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118224 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.118224 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.362089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.362089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179742 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179742 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227916 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227916 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.082637 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.082637 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.085741 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.085741 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15858.806812 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15858.806812 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23179.098389 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23179.098389 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19533.151897 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19533.151897 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23289.574993 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23289.574993 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20389.581030 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20389.581030 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19481.680856 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19481.680856 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1443381 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 46 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 45166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.391304 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 31.957247 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20646.766999 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20646.766999 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19678.116168 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19678.116168 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1600979 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 49143 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.363636 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32.577966 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 125175 # number of writebacks -system.cpu1.dcache.writebacks::total 125175 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 81304 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 81304 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 345063 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 345063 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13214 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13214 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 426367 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 426367 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 426367 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 426367 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143333 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143333 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 96312 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 96312 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29478 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29478 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5080 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5080 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 239645 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 239645 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 269123 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 269123 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1836231651 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1836231651 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2306828153 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2306828153 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 473894752 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 473894752 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85053999 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85053999 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 496613735 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 496613735 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 413000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 413000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4143059804 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4143059804 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4616954556 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4616954556 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298741750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298741750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826982999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826982999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125724749 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125724749 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014419 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014419 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360160 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360160 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050900 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050900 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.244209 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.244209 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014534 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014534 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016241 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016241 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12810.948288 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12810.948288 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23951.617171 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23951.617171 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16076.217925 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.217925 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16742.913189 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16742.913189 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20981.610334 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.610334 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 137785 # number of writebacks +system.cpu1.dcache.writebacks::total 137785 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 90105 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 90105 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375217 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 375217 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13775 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13775 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 465322 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 465322 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 465322 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 465322 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163803 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163803 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104855 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 104855 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32523 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32523 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5409 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5409 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23489 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23489 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 268658 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 268658 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 301181 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 301181 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2171865461 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2171865461 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2612489394 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2612489394 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 519825898 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 519825898 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98469253 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98469253 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 510672173 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 510672173 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 974500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 974500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4784354855 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4784354855 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5304180753 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5304180753 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 979094500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 979094500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827869001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827869001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033975 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033975 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025822 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025822 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.325941 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.325941 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050679 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050679 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227916 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227916 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030248 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030248 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033532 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13259.009060 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13259.009060 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24915.258157 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24915.258157 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15983.331734 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15983.331734 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18204.705676 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18204.705676 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21740.907361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21740.907361 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17288.321492 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17288.321492 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17155.555475 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17155.555475 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17808.346876 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17808.346876 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17611.272799 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17611.272799 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2285,425 +2289,415 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 614958 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.494107 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43363824 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 615470 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 70.456438 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78768329500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.494107 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975574 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975574 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 667401 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.527528 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9840970 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 667913 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 14.733910 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78865217000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.527528 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973687 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973687 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 88611673 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 88611673 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43363824 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43363824 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43363824 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43363824 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43363824 # number of overall hits -system.cpu1.icache.overall_hits::total 43363824 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 634277 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 634277 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 634277 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 634277 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 634277 # number of overall misses -system.cpu1.icache.overall_misses::total 634277 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5597748699 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5597748699 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5597748699 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5597748699 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5597748699 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5597748699 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43998101 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43998101 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43998101 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43998101 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43998101 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43998101 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014416 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014416 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014416 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014416 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014416 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014416 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8825.400730 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8825.400730 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8825.400730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8825.400730 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 423261 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 12 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 39865 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 21731377 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21731377 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9840970 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9840970 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9840970 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9840970 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9840970 # number of overall hits +system.cpu1.icache.overall_hits::total 9840970 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 690756 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 690756 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 690756 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 690756 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 690756 # number of overall misses +system.cpu1.icache.overall_misses::total 690756 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6328356335 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6328356335 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6328356335 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6328356335 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6328356335 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6328356335 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10531726 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10531726 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10531726 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10531726 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10531726 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10531726 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065588 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.065588 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065588 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.065588 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065588 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.065588 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9161.493110 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9161.493110 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9161.493110 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9161.493110 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 590927 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 49303 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.617359 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 12 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.985620 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18806 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 18806 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 18806 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 18806 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 18806 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 18806 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615471 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 615471 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 615471 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 615471 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 615471 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 615471 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4523939883 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4523939883 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4523939883 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4523939883 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4523939883 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4523939883 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8397000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8397000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013989 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013989 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013989 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7350.370502 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22831 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22831 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22831 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22831 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22831 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22831 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 667925 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 667925 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 667925 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 667925 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 667925 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 667925 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5443930957 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5443930957 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5443930957 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5443930957 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5443930957 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5443930957 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8774500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8774500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8774500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8774500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063420 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.063420 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.063420 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8150.512343 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 229039 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 229849 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 714 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 270002 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 271052 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 936 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59807 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 55576 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15296.446244 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 851759 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 70922 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.009799 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 67932 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 66588 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15581.068012 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 931760 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81198 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.475159 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8246.965221 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 13.312576 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.835357 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3924.928701 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2437.613409 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 669.790981 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.503355 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000813 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000234 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.239559 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.148780 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040881 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.933621 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 766 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14561 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6676.895279 # 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number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484903709 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484903709 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 334604857 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 334604857 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 832000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 832000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1217604967 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1217604967 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3646000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 759958022 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2477443378 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3247908900 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3646000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 759958022 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2477443378 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4867282642 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 934007000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941982000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811858998 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811858998 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7975000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1745865998 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1753840998 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.363653 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107333 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946055 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946055 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957707 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.957707 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.507655 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.507655 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139631 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926203 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926203 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952276 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952276 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.473128 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.473128 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135203 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.171625 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.442638 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17532.812215 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63187.747628 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14546.805631 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14546.805631 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13617.957074 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13617.957074 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 341000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 341000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30266.404353 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30266.404353 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21040.945973 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28897.762712 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173717 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 17175.242815 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21082.676715 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43292.975324 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16624.510045 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16624.510045 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.086955 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.086955 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34777.783182 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34777.783182 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24734.100203 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28848.626951 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2713,70 +2707,68 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1181364 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 879041 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 125175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 39550 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75362 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41966 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86419 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 89279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 71717 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1231143 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 850974 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17917 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 40354 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2140388 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39391696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 26549567 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31836 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 66043891 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 585425 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1574316 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.319194 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.466164 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1243272 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 949021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 137784 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 47376 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75841 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89718 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 96830 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79934 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1336034 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 901614 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17159 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 43403 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2298210 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42747664 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29480945 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 79768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 72339053 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 592219 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1674781 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.301785 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.459032 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1071804 68.08% 68.08% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 502512 31.92% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 1169358 69.82% 69.82% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 505423 30.18% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1574316 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 680504524 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1674781 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 730243456 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81017999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87400998 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 924938756 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1002964345 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 418581676 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 454923751 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 10092231 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9604282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 22735342 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 23499938 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31021 # Transaction distribution -system.iobus.trans_dist::ReadResp 31021 # Transaction distribution -system.iobus.trans_dist::WriteReq 59439 # Transaction distribution -system.iobus.trans_dist::WriteResp 23215 # Transaction distribution +system.iobus.trans_dist::ReadReq 31011 # Transaction distribution +system.iobus.trans_dist::ReadResp 31011 # Transaction distribution +system.iobus.trans_dist::WriteReq 59421 # Transaction distribution +system.iobus.trans_dist::WriteResp 23197 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2792,16 +2784,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180920 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2817,11 +2809,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2831,7 +2823,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2861,23 +2853,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347085145 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198996708 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36840554 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36791507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.558041 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.446927 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254609644000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.558041 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909878 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909878 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254830116000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.446927 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902933 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902933 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2891,14 +2883,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31425377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31425377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9633411214 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9633411214 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31425377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31425377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31425377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31425377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32290377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32290377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6656632824 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6656632824 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32290377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32290377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32290377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32290377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2915,19 +2907,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124703.876984 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124703.876984 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265940.018054 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265940.018054 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124703.876984 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124703.876984 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56535 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128136.416667 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128136.416667 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183763.052783 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183763.052783 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128136.416667 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128136.416667 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23055 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7211 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3532 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.840105 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.527463 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2941,14 +2933,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18320377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18320377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7749655322 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7749655322 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18320377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18320377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18320377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18320377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19155377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19155377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772970838 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772970838 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19155377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19155377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19155377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19155377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2957,521 +2949,518 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72699.908730 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72699.908730 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213937.039587 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213937.039587 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76013.400794 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76013.400794 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131762.666685 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131762.666685 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 131156 # number of replacements -system.l2c.tags.tagsinuse 63989.320892 # Cycle average of tags in use -system.l2c.tags.total_refs 352673 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195503 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.803926 # Average number of references to valid blocks. +system.l2c.tags.replacements 136223 # number of replacements +system.l2c.tags.tagsinuse 64041.513044 # Cycle average of tags in use +system.l2c.tags.total_refs 356136 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200557 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.775735 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11841.549695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.064672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.035376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7520.794001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2869.625937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37329.338161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.624339 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1925.336025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 701.530072 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1779.513002 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.180688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.114758 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.569600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000071 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12781.567033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.527645 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.082100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5930.123644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1752.659752 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33401.860992 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.992291 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3387.143441 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1822.858320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4939.794575 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.195031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000017 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.090487 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.026743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.509672 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000122 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029378 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976400 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31812 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6391 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25201 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.051684 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.027815 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.075375 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977196 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31391 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32916 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6119 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25156 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 410 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 25933 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.485413 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.496155 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5013444 # Number of tag accesses -system.l2c.tags.data_accesses 5013444 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 174 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 66 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 34010 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 46649 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 75 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 15163 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4879 # number of ReadReq hits -system.l2c.ReadReq_hits::total 156615 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227099 # number of Writeback hits -system.l2c.Writeback_hits::total 227099 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2891 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 673 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3564 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3845 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1635 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5480 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 174 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 66 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 34010 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 50494 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 75 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 15163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11603 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4879 # number of demand (read+write) hits -system.l2c.demand_hits::total 162095 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 174 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 66 # number of overall hits -system.l2c.overall_hits::cpu0.inst 34010 # number of overall hits -system.l2c.overall_hits::cpu0.data 50494 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45581 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits -system.l2c.overall_hits::cpu1.inst 15163 # number of overall hits -system.l2c.overall_hits::cpu1.data 11603 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4879 # number of overall hits -system.l2c.overall_hits::total 162095 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 19495 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9130 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128336 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4913 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27508 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.478989 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.502258 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5099427 # Number of tag accesses +system.l2c.tags.data_accesses 5099427 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 187 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 89 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 32294 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45191 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 42802 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 34 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 17148 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11819 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7598 # number of ReadReq hits +system.l2c.ReadReq_hits::total 157222 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 232253 # number of Writeback hits +system.l2c.Writeback_hits::total 232253 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2477 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 788 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3265 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 61 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3656 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1776 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5432 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 32294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 48847 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 42802 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 60 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 7598 # 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number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 17722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8264 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2993 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1306 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10708 # number of ReadReq misses -system.l2c.ReadReq_misses::total 172002 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8592 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2954 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11546 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 671 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1237 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8380737065 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5954500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1545090002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10113260817 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154597 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173843 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.526303 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772397 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828807 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.789164 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791457 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949293 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.870672 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755435 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839218 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.791037 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.545528 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.545528 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78251.487415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76766.721351 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95272.828776 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17826.656317 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17775.439318 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17810.668030 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17879.830688 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17750.125219 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17808.856253 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83153.498627 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71480.450593 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 77891.175266 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3486,57 +3475,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 210212 # Transaction distribution -system.membus.trans_dist::ReadResp 210211 # Transaction distribution -system.membus.trans_dist::WriteReq 30942 # Transaction distribution -system.membus.trans_dist::WriteResp 30942 # Transaction distribution -system.membus.trans_dist::Writeback 135769 # Transaction distribution +system.membus.trans_dist::ReadReq 213069 # Transaction distribution +system.membus.trans_dist::ReadResp 213068 # Transaction distribution +system.membus.trans_dist::WriteReq 31079 # Transaction distribution +system.membus.trans_dist::WriteResp 31079 # Transaction distribution +system.membus.trans_dist::Writeback 139403 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76140 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40614 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13546 # Transaction distribution -system.membus.trans_dist::ReadExReq 39344 # Transaction distribution -system.membus.trans_dist::ReadExResp 19397 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77234 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14409 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 40484 # Transaction distribution +system.membus.trans_dist::ReadExResp 20462 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 770072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 784904 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 878993 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 893825 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18669148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18859512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19143964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19335481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23495992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123727 # Total snoops (count) -system.membus.snoop_fanout::samples 500337 # Request fanout histogram +system.membus.pkt_size::total 23971961 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125081 # Total snoops (count) +system.membus.snoop_fanout::samples 510035 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 500337 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 510035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 500337 # Request fanout histogram -system.membus.reqLayer0.occupancy 81279500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 510035 # Request fanout histogram +system.membus.reqLayer0.occupancy 81680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 26000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11516000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11944988 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1822464250 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1904793274 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38546446 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1164089698 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1154561869 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3569,48 +3559,48 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 489006 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 488990 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30942 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30942 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227099 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79612 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40957 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 120569 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50358 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50358 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1016462 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 341372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1357834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31696041 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5742799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37438840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 287500 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 885309 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.041201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.198756 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 494432 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 494416 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31079 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31079 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232253 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80398 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41961 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 122359 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50963 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50963 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1036150 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339974 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1376124 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31294456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6755201 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38049657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 290334 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 898197 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.040648 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.197474 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 848833 95.88% 95.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 4.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 861687 95.94% 95.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36510 4.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 885309 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1431615961 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1066500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 898197 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 772973190 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1714942226 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 674969400 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 636594669 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 265283017 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2748 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 8914a4f8a..e4b623d06 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827025 # Number of seconds simulated -sim_ticks 2827025397500 # Number of ticks simulated -final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827616 # Number of seconds simulated +sim_ticks 2827616186000 # Number of ticks simulated +final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96738 # Simulator instruction rate (inst/s) -host_op_rate 117339 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2415768223 # Simulator tick rate (ticks/s) -host_mem_usage 619580 # Number of bytes of host memory used -host_seconds 1170.24 # Real time elapsed on the host -sim_insts 113206948 # Number of instructions simulated -sim_ops 137314363 # Number of ops (including micro ops) simulated +host_inst_rate 99248 # Simulator instruction rate (inst/s) +host_op_rate 120386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2480177298 # Simulator tick rate (ticks/s) +host_mem_usage 619560 # Number of bytes of host memory used +host_seconds 1140.09 # Real time elapsed on the host +sim_insts 113151083 # Number of instructions simulated +sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory +system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171932 # Number of read requests accepted -system.physmem.writeReqs 167449 # Number of write requests accepted -system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11320 # Per bank write bursts -system.physmem.perBankRdBursts::1 10283 # Per bank write bursts -system.physmem.perBankRdBursts::2 11137 # Per bank write bursts -system.physmem.perBankRdBursts::3 11363 # Per bank write bursts -system.physmem.perBankRdBursts::4 13028 # Per bank write bursts -system.physmem.perBankRdBursts::5 10237 # Per bank write bursts -system.physmem.perBankRdBursts::6 10954 # Per bank write bursts -system.physmem.perBankRdBursts::7 11381 # Per bank write bursts -system.physmem.perBankRdBursts::8 10407 # Per bank write bursts -system.physmem.perBankRdBursts::9 11232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10729 # Per bank write bursts -system.physmem.perBankRdBursts::11 9386 # Per bank write bursts -system.physmem.perBankRdBursts::12 9853 # Per bank write bursts -system.physmem.perBankRdBursts::13 10909 # Per bank write bursts -system.physmem.perBankRdBursts::14 9951 # Per bank write bursts -system.physmem.perBankRdBursts::15 9636 # Per bank write bursts -system.physmem.perBankWrBursts::0 10810 # Per bank write bursts -system.physmem.perBankWrBursts::1 10132 # Per bank write bursts -system.physmem.perBankWrBursts::2 10502 # Per bank write bursts -system.physmem.perBankWrBursts::3 10558 # Per bank write bursts -system.physmem.perBankWrBursts::4 9654 # Per bank write bursts -system.physmem.perBankWrBursts::5 9978 # Per bank write bursts -system.physmem.perBankWrBursts::6 10358 # Per bank write bursts -system.physmem.perBankWrBursts::7 10535 # Per bank write bursts -system.physmem.perBankWrBursts::8 10309 # Per bank write bursts -system.physmem.perBankWrBursts::9 10935 # Per bank write bursts -system.physmem.perBankWrBursts::10 10009 # Per bank write bursts -system.physmem.perBankWrBursts::11 9154 # Per bank write bursts -system.physmem.perBankWrBursts::12 9556 # Per bank write bursts -system.physmem.perBankWrBursts::13 10555 # Per bank write bursts -system.physmem.perBankWrBursts::14 9521 # Per bank write bursts -system.physmem.perBankWrBursts::15 9009 # Per bank write bursts +system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.writeReqs 171661 # Number of write requests accepted +system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11334 # Per bank write bursts +system.physmem.perBankRdBursts::1 10890 # Per bank write bursts +system.physmem.perBankRdBursts::2 10732 # Per bank write bursts +system.physmem.perBankRdBursts::3 10393 # Per bank write bursts +system.physmem.perBankRdBursts::4 14045 # Per bank write bursts +system.physmem.perBankRdBursts::5 11531 # Per bank write bursts +system.physmem.perBankRdBursts::6 11498 # Per bank write bursts +system.physmem.perBankRdBursts::7 11674 # Per bank write bursts +system.physmem.perBankRdBursts::8 10645 # Per bank write bursts +system.physmem.perBankRdBursts::9 10993 # Per bank write bursts +system.physmem.perBankRdBursts::10 10307 # Per bank write bursts +system.physmem.perBankRdBursts::11 9597 # Per bank write bursts +system.physmem.perBankRdBursts::12 9956 # Per bank write bursts +system.physmem.perBankRdBursts::13 10908 # Per bank write bursts +system.physmem.perBankRdBursts::14 10689 # Per bank write bursts +system.physmem.perBankRdBursts::15 10844 # Per bank write bursts +system.physmem.perBankWrBursts::0 9257 # Per bank write bursts +system.physmem.perBankWrBursts::1 9346 # Per bank write bursts +system.physmem.perBankWrBursts::2 9336 # Per bank write bursts +system.physmem.perBankWrBursts::3 8962 # Per bank write bursts +system.physmem.perBankWrBursts::4 9705 # Per bank write bursts +system.physmem.perBankWrBursts::5 9746 # Per bank write bursts +system.physmem.perBankWrBursts::6 9125 # Per bank write bursts +system.physmem.perBankWrBursts::7 9630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9307 # Per bank write bursts +system.physmem.perBankWrBursts::9 9634 # Per bank write bursts +system.physmem.perBankWrBursts::10 8942 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8881 # Per bank write bursts +system.physmem.perBankWrBursts::13 9361 # Per bank write bursts +system.physmem.perBankWrBursts::14 9018 # Per bank write bursts +system.physmem.perBankWrBursts::15 9072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827025186500 # Total gap between requests +system.physmem.numWrRetry 58 # Number of times write queue was full causing retry +system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2993 # Read request sizes (log2) +system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168384 # Read request sizes (log2) +system.physmem.readPktSize::6 172624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163068 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,175 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads -system.physmem.totQLat 2011805750 # Total ticks spent queuing -system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads +system.physmem.totQLat 2104910750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing -system.physmem.readRowHits 141825 # Number of row buffer hits during reads -system.physmem.writeRowHits 127038 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes -system.physmem.avgGap 8329945.36 # Average gap between requests -system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.379373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing +system.physmem.readRowHits 145058 # Number of row buffer hits during reads +system.physmem.writeRowHits 112529 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes +system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.422846 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.289511 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.324331 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -347,15 +333,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46965884 # Number of BP lookups -system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits +system.cpu.branchPred.lookups 46937284 # Number of BP lookups +system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -386,81 +372,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 69937 # Table walker walks requested -system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72371 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25472400 # DTB read hits -system.cpu.dtb.read_misses 60528 # DTB read misses -system.cpu.dtb.write_hits 19920178 # DTB write hits -system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_misses 62291 # DTB read misses +system.cpu.dtb.write_hits 19915387 # DTB write hits +system.cpu.dtb.write_misses 10080 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532928 # DTB read accesses -system.cpu.dtb.write_accesses 19929587 # DTB write accesses +system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45392578 # DTB hits -system.cpu.dtb.misses 69937 # DTB misses -system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.misses 72371 # DTB misses +system.cpu.dtb.accesses 45449628 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -490,55 +479,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11957 # Table walker walks requested -system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11974 # Table walker walks requested +system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66242388 # ITB inst hits -system.cpu.itb.inst_misses 11957 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66270436 # ITB inst hits +system.cpu.itb.inst_misses 11974 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -547,98 +537,98 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66254345 # ITB inst accesses -system.cpu.itb.hits 66242388 # DTB hits -system.cpu.itb.misses 11957 # DTB misses -system.cpu.itb.accesses 66254345 # DTB accesses -system.cpu.numCycles 260505842 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66282410 # ITB inst accesses +system.cpu.itb.hits 66270436 # DTB hits +system.cpu.itb.misses 11974 # DTB misses +system.cpu.itb.accesses 66282410 # DTB accesses +system.cpu.numCycles 263104506 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -646,44 +636,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -707,101 +697,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued -system.cpu.iq.rate 0.550386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.rate 0.544758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200965 # number of nop insts executed -system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544582 # Number of branches executed -system.cpu.iew.exec_stores 20883032 # Number of stores executed -system.cpu.iew.exec_rate 0.546767 # Inst execution rate -system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301991 # num instructions producing a value -system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value +system.cpu.iew.exec_nop 201053 # number of nop insts executed +system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_branches 26530134 # Number of branches executed +system.cpu.iew.exec_stores 20877849 # Number of stores executed +system.cpu.iew.exec_rate 0.541163 # Inst execution rate +system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271750 # num instructions producing a value +system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113361853 # Number of instructions committed -system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113305988 # Number of instructions committed +system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45532382 # Number of memory references committed -system.cpu.commit.loads 24928817 # Number of loads committed -system.cpu.commit.membars 814713 # Number of memory barriers committed -system.cpu.commit.branches 26060941 # Number of branches committed +system.cpu.commit.refs 45511652 # Number of memory references committed +system.cpu.commit.loads 24916104 # Number of loads committed +system.cpu.commit.membars 814017 # Number of memory barriers committed +system.cpu.commit.branches 26045610 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896517 # Number of function calls committed. +system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892502 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -825,214 +815,214 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373323554 # The number of ROB reads -system.cpu.rob.rob_writes 293054802 # The number of ROB writes -system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113206948 # Number of Instructions Simulated -system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155872747 # number of integer regfile reads -system.cpu.int_regfile_writes 88664446 # number of integer regfile writes -system.cpu.fp_regfile_reads 9607 # number of floating regfile reads +system.cpu.rob.rob_reads 375672050 # The number of ROB reads +system.cpu.rob.rob_writes 292972268 # The number of ROB writes +system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113151083 # Number of Instructions Simulated +system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_writes 88633021 # number of integer regfile writes +system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503168366 # number of cc regfile reads -system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes -system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837844 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads +system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes +system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839617 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits -system.cpu.dcache.overall_hits::total 39264228 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3575875 # 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number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # 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average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks +system.cpu.dcache.writebacks::total 696320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # 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number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # 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number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98730 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65075.133005 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3019277 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163872 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5229.614939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.757349 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # 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average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1419,61 +1409,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65703 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010231 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 62589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3525674 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1494,11 +1482,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1519,11 +1507,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1563,52 +1551,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses -system.iocache.demand_misses::total 220 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 220 # number of overall misses -system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses +system.iocache.demand_misses::total 233 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 233 # number of overall misses +system.iocache.overall_misses::total 233 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1617,40 +1605,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1659,66 +1647,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67820 # Transaction distribution -system.membus.trans_dist::ReadResp 67819 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126844 # Transaction distribution +system.membus.trans_dist::ReadReq 68566 # Transaction distribution +system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131056 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution -system.membus.trans_dist::ReadExReq 135185 # Transaction distribution -system.membus.trans_dist::ReadExResp 135185 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution +system.membus.trans_dist::ReadExReq 138681 # Transaction distribution +system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336478 # Request fanout histogram +system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoop_fanout::samples 345038 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336478 # Request fanout histogram -system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1752,6 +1740,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index da0ad220f..2b4d78664 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.818071 # Number of seconds simulated -sim_ticks 2818071194500 # Number of ticks simulated -final_tick 2818071194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817778 # Number of seconds simulated +sim_ticks 2817777605000 # Number of ticks simulated +final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 294940 # Simulator instruction rate (inst/s) -host_op_rate 358127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6587540433 # Simulator tick rate (ticks/s) -host_mem_usage 622484 # Number of bytes of host memory used -host_seconds 427.79 # Real time elapsed on the host -sim_insts 126171688 # Number of instructions simulated -sim_ops 153202470 # Number of ops (including micro ops) simulated +host_inst_rate 297325 # Simulator instruction rate (inst/s) +host_op_rate 361032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6636656496 # Simulator tick rate (ticks/s) +host_mem_usage 622556 # Number of bytes of host memory used +host_seconds 424.58 # Real time elapsed on the host +sim_insts 126237777 # Number of instructions simulated +sim_ops 153286368 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 666276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4385696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 655396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4517280 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 127360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1038980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 505600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4227776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 125824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1063044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 519744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4071296 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10959048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 666276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 127360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 505600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1299236 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8262336 # Number of bytes written to this memory +system.physmem.bytes_read::total 10959816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 655396 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 125824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 519744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1300964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8260864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8279860 # Number of bytes written to this memory +system.physmem.bytes_written::total 8278388 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 71101 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 66059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 63614 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180208 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129099 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180220 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129076 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133480 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133457 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 236430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1556276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 232593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1603136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 368685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 179413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1500237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 44654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 377263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 184452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1444861 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3888847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 236430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 179413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2931912 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3889525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 232593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 44654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 184452 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2931695 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2938130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2931912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2937914 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2931695 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 236430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1562491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 232593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1609352 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 368688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 179413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1500237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 44654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 377266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 184452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1444861 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6826977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 92280 # Number of read requests accepted -system.physmem.writeReqs 90311 # Number of write requests accepted -system.physmem.readBursts 92280 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 90311 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5901184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4736 # Total number of bytes read from write queue -system.physmem.bytesWritten 5694528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5905860 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5779784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 74 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1313 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2491 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6033 # Per bank write bursts -system.physmem.perBankRdBursts::1 5793 # Per bank write bursts -system.physmem.perBankRdBursts::2 5545 # Per bank write bursts -system.physmem.perBankRdBursts::3 6032 # Per bank write bursts -system.physmem.perBankRdBursts::4 5564 # Per bank write bursts -system.physmem.perBankRdBursts::5 5452 # Per bank write bursts -system.physmem.perBankRdBursts::6 6124 # Per bank write bursts -system.physmem.perBankRdBursts::7 6804 # Per bank write bursts -system.physmem.perBankRdBursts::8 6414 # Per bank write bursts -system.physmem.perBankRdBursts::9 6339 # Per bank write bursts -system.physmem.perBankRdBursts::10 5684 # Per bank write bursts -system.physmem.perBankRdBursts::11 5101 # Per bank write bursts -system.physmem.perBankRdBursts::12 5267 # Per bank write bursts -system.physmem.perBankRdBursts::13 5451 # Per bank write bursts -system.physmem.perBankRdBursts::14 5288 # Per bank write bursts -system.physmem.perBankRdBursts::15 5315 # Per bank write bursts -system.physmem.perBankWrBursts::0 5413 # Per bank write bursts -system.physmem.perBankWrBursts::1 4989 # Per bank write bursts -system.physmem.perBankWrBursts::2 5365 # Per bank write bursts -system.physmem.perBankWrBursts::3 5927 # Per bank write bursts -system.physmem.perBankWrBursts::4 5380 # Per bank write bursts -system.physmem.perBankWrBursts::5 5714 # Per bank write bursts -system.physmem.perBankWrBursts::6 5766 # Per bank write bursts -system.physmem.perBankWrBursts::7 6373 # Per bank write bursts -system.physmem.perBankWrBursts::8 6011 # Per bank write bursts -system.physmem.perBankWrBursts::9 5951 # Per bank write bursts -system.physmem.perBankWrBursts::10 5678 # Per bank write bursts -system.physmem.perBankWrBursts::11 4910 # Per bank write bursts -system.physmem.perBankWrBursts::12 5493 # Per bank write bursts -system.physmem.perBankWrBursts::13 5839 # Per bank write bursts -system.physmem.perBankWrBursts::14 5189 # Per bank write bursts -system.physmem.perBankWrBursts::15 4979 # Per bank write bursts +system.physmem.bw_total::total 6827439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90406 # Number of read requests accepted +system.physmem.writeReqs 90720 # Number of write requests accepted +system.physmem.readBursts 90406 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 90720 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5783616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2368 # Total number of bytes read from write queue +system.physmem.bytesWritten 4983552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5785924 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5805960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 37 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 12831 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2411 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5941 # Per bank write bursts +system.physmem.perBankRdBursts::1 5711 # Per bank write bursts +system.physmem.perBankRdBursts::2 5475 # Per bank write bursts +system.physmem.perBankRdBursts::3 5399 # Per bank write bursts +system.physmem.perBankRdBursts::4 5366 # Per bank write bursts +system.physmem.perBankRdBursts::5 5838 # Per bank write bursts +system.physmem.perBankRdBursts::6 6281 # Per bank write bursts +system.physmem.perBankRdBursts::7 6483 # Per bank write bursts +system.physmem.perBankRdBursts::8 6268 # Per bank write bursts +system.physmem.perBankRdBursts::9 6346 # Per bank write bursts +system.physmem.perBankRdBursts::10 5330 # Per bank write bursts +system.physmem.perBankRdBursts::11 5015 # Per bank write bursts +system.physmem.perBankRdBursts::12 5399 # Per bank write bursts +system.physmem.perBankRdBursts::13 5276 # Per bank write bursts +system.physmem.perBankRdBursts::14 4950 # Per bank write bursts +system.physmem.perBankRdBursts::15 5291 # Per bank write bursts +system.physmem.perBankWrBursts::0 4893 # Per bank write bursts +system.physmem.perBankWrBursts::1 4429 # Per bank write bursts +system.physmem.perBankWrBursts::2 4791 # Per bank write bursts +system.physmem.perBankWrBursts::3 4794 # Per bank write bursts +system.physmem.perBankWrBursts::4 4700 # Per bank write bursts +system.physmem.perBankWrBursts::5 5367 # Per bank write bursts +system.physmem.perBankWrBursts::6 5289 # Per bank write bursts +system.physmem.perBankWrBursts::7 5346 # Per bank write bursts +system.physmem.perBankWrBursts::8 5326 # Per bank write bursts +system.physmem.perBankWrBursts::9 5240 # Per bank write bursts +system.physmem.perBankWrBursts::10 4672 # Per bank write bursts +system.physmem.perBankWrBursts::11 4285 # Per bank write bursts +system.physmem.perBankWrBursts::12 5029 # Per bank write bursts +system.physmem.perBankWrBursts::13 5084 # Per bank write bursts +system.physmem.perBankWrBursts::14 4218 # Per bank write bursts +system.physmem.perBankWrBursts::15 4405 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2816505052000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 2816211460500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 92279 # Read request sizes (log2) +system.physmem.readPktSize::6 90405 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 90309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 90718 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 59525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -175,194 +175,174 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.579050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.896082 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.051588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12589 37.08% 37.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7648 22.53% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3047 8.98% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1722 5.07% 73.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1227 3.61% 77.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 803 2.37% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 549 1.62% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 558 1.64% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5804 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33947 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3440 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.800581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 525.347088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3439 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3440 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3440 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.865407 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.895854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 25.306431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 5 0.15% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 4 0.12% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2693 78.28% 78.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 34 0.99% 79.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 21 0.61% 80.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 172 5.00% 85.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 62 1.80% 87.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 30 0.87% 87.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.49% 88.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.47% 88.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 84 2.44% 91.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.32% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.41% 92.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.29% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.58% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.17% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.17% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.73% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 46 1.34% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.12% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.12% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.26% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 47 1.37% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.09% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.17% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.06% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 16 0.47% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.03% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 7 0.20% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.06% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.09% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.17% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.09% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.09% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.09% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.12% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.09% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3440 # Writes before turning the bus around for reads -system.physmem.totQLat 1163516500 # Total ticks spent queuing -system.physmem.totMemAccLat 2892379000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 461030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12618.66 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 33321 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.130758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.789706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.993140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12624 37.89% 37.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7779 23.35% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3018 9.06% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1714 5.14% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1413 4.24% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 752 2.26% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 537 1.61% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 554 1.66% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4930 14.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33321 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2995 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.170618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 514.809638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 2993 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2995 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.999332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.796866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 47.448084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 17 0.57% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 2784 92.95% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 41 1.37% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 11 0.37% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 6 0.20% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 14 0.47% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 11 0.37% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 12 0.40% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.23% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.37% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 7 0.23% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 15 0.50% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.47% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 4 0.13% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.03% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.07% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.13% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.10% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.10% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.20% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.03% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.20% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 5 0.17% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2995 # Writes before turning the bus around for reads +system.physmem.totQLat 1193098984 # Total ticks spent queuing +system.physmem.totMemAccLat 2887517734 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 451845000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13202.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31368.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.09 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31952.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.25 # Average write queue length when enqueuing -system.physmem.readRowHits 76428 # Number of row buffer hits during reads -system.physmem.writeRowHits 70807 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.56 # Row buffer hit rate for writes -system.physmem.avgGap 15425212.92 # Average gap between requests -system.physmem.pageHitRate 81.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 134288280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 73012500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68919855390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860855224610 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.510956 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states -system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem.avgWrQLen 4.64 # Average write queue length when enqueuing +system.physmem.readRowHits 74590 # Number of row buffer hits during reads +system.physmem.writeRowHits 60325 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.45 # Row buffer hit rate for writes +system.physmem.avgGap 15548355.62 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 130667040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 71094375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.497599 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states +system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14405588500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14475823012 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 122351040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 66577500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 349884600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 285444000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68134185630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1610493455250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1858324146900 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.557325 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2634053636000 # Time in different power states -system.physmem_1.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem_1.actEnergy 121239720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 65934000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 342209400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 247918320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68215091715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1611413256750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1859258064945 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.496864 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2633620948492 # Time in different power states +system.physmem_1.memoryStateTime::REF 91437840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13230281250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13360607258 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -412,48 +392,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5757 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5757 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5757 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5757 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5757 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.475514 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 87128456868 52.45% 52.45% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 78993152250 47.55% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 166121609118 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3229 67.67% 67.67% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1543 32.33% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4772 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5757 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 5755 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5755 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5755 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5755 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5755 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.475663 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 87076283368 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 78993148500 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 166069431868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3189 67.65% 67.65% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1525 32.35% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4714 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5755 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5757 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5755 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4714 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4772 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10529 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4714 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10469 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14474153 # DTB read hits -system.cpu0.dtb.read_misses 4865 # DTB read misses -system.cpu0.dtb.write_hits 11054581 # DTB write hits -system.cpu0.dtb.write_misses 892 # DTB write misses -system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14452204 # DTB read hits +system.cpu0.dtb.read_misses 4833 # DTB read misses +system.cpu0.dtb.write_hits 11089888 # DTB write hits +system.cpu0.dtb.write_misses 922 # DTB write misses +system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3207 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3319 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 943 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 195 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14479018 # DTB read accesses -system.cpu0.dtb.write_accesses 11055473 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14457037 # DTB read accesses +system.cpu0.dtb.write_accesses 11090810 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25528734 # DTB hits -system.cpu0.dtb.misses 5757 # DTB misses -system.cpu0.dtb.accesses 25534491 # DTB accesses +system.cpu0.dtb.hits 25542092 # DTB hits +system.cpu0.dtb.misses 5755 # DTB misses +system.cpu0.dtb.accesses 25547847 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,387 +463,387 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2755 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2755 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2755 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2755 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2755 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.475515 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 87128348368 52.45% 52.45% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 78993260750 47.55% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 166121609118 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1528 75.53% 75.53% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 495 24.47% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2817 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2817 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2817 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2817 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2817 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.475664 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 87076165368 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 78993266500 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 166069431868 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1542 75.55% 75.55% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 499 24.45% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2041 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2755 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2755 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2817 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2817 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4778 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 67991390 # ITB inst hits -system.cpu0.itb.inst_misses 2755 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4858 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 67891248 # ITB inst hits +system.cpu0.itb.inst_misses 2817 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 188 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1966 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67994145 # ITB inst accesses -system.cpu0.itb.hits 67991390 # DTB hits -system.cpu0.itb.misses 2755 # DTB misses -system.cpu0.itb.accesses 67994145 # DTB accesses -system.cpu0.numCycles 82552372 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67894065 # ITB inst accesses +system.cpu0.itb.hits 67891248 # DTB hits +system.cpu0.itb.misses 2817 # DTB misses +system.cpu0.itb.accesses 67894065 # DTB accesses +system.cpu0.numCycles 82517225 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66182532 # Number of instructions committed -system.cpu0.committedOps 80633643 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70853114 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses -system.cpu0.num_func_calls 7266071 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8791663 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70853114 # number of integer instructions -system.cpu0.num_fp_insts 5470 # number of float instructions -system.cpu0.num_int_register_reads 131368884 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49289864 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245759484 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29458192 # number of times the CC registers were written -system.cpu0.num_mem_refs 26200850 # number of memory refs -system.cpu0.num_load_insts 14651277 # Number of load instructions -system.cpu0.num_store_insts 11549573 # Number of store instructions -system.cpu0.num_idle_cycles 77943726.541103 # Number of idle cycles -system.cpu0.num_busy_cycles 4608645.458897 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055827 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944173 # Percentage of idle cycles -system.cpu0.Branches 16455843 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55777669 67.99% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 58831 0.07% 68.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4520 0.01% 68.06% # Class of executed instruction +system.cpu0.committedInsts 66111161 # Number of instructions committed +system.cpu0.committedOps 80627134 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70885778 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5615 # Number of float alu accesses +system.cpu0.num_func_calls 7285085 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8754092 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70885778 # number of integer instructions +system.cpu0.num_fp_insts 5615 # number of float instructions +system.cpu0.num_int_register_reads 131498293 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49310474 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4327 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1292 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245812611 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29370316 # number of times the CC registers were written +system.cpu0.num_mem_refs 26208491 # number of memory refs +system.cpu0.num_load_insts 14628012 # Number of load instructions +system.cpu0.num_store_insts 11580479 # Number of store instructions +system.cpu0.num_idle_cycles 77919171.769514 # Number of idle cycles +system.cpu0.num_busy_cycles 4598053.230486 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055722 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944278 # Percentage of idle cycles +system.cpu0.Branches 16437108 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2194 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55772206 67.98% 67.98% # Class of executed instruction +system.cpu0.op_class::IntMult 58001 0.07% 68.05% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4497 0.01% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14651277 17.86% 85.92% # Class of executed instruction -system.cpu0.op_class::MemWrite 11549573 14.08% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14628012 17.83% 85.89% # Class of executed instruction +system.cpu0.op_class::MemWrite 11580479 14.11% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # 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Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 832376 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.530914 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.894462 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.632625 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.469713 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949013 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032486 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018496 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.861119 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.669659 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.466239 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948947 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032558 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018489 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198459549 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198459549 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13785736 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4396523 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8506631 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26688890 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10662175 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3165503 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5162158 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18989836 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190654 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60573 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130462 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381689 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80326 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134935 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451086 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237211 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82830 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139650 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459691 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24447911 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7562026 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13668789 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45678726 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24638565 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7622599 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13799251 # number of overall hits -system.cpu0.dcache.overall_hits::total 46060415 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191504 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 58959 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 314968 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 565431 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143878 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 35403 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 1532172 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1711453 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54012 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 21177 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65552 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 140741 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4456 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3300 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9701 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17457 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 198551178 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 198551178 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 13770345 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 4433242 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 8498402 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 26701989 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10695058 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3174725 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 5187481 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 19057264 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188196 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 61394 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 132351 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 381941 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234602 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80377 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 136196 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 451175 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82808 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140857 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459739 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 24465403 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 7607967 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 13685883 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 45759253 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 24653599 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 7669361 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 13818234 # number of overall hits +system.cpu0.dcache.overall_hits::total 46141194 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 187937 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 59498 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 318451 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 565886 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 147418 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 35026 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 1470502 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1652946 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54526 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20446 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 66281 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141253 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4541 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3227 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9714 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17482 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 16 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335382 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94362 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1847140 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2276884 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389394 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 115539 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1912692 # number of overall misses -system.cpu0.dcache.overall_misses::total 2417625 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 898816250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5241989350 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6140805600 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1325719411 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70529735198 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71855454609 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46466000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132057494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178523494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 259504 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 259504 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2224535661 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 75771724548 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 77996260209 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2224535661 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 75771724548 # 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number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196014 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 522430 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 240281 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83626 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 144636 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468543 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 237213 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82830 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 139666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459709 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 24783293 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 7656388 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 15515929 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 47955610 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 25027959 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 7738138 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 15711943 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 48478040 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013701 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013233 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035704 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020746 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013315 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011060 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228876 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.082674 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220758 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259046 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334425 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269397 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018545 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039461 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1319132500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098719500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1799034000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3016119000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4815153000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013205 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011060 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017927 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254373 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224004 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123850 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019843 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008998 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000115 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94437 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 277809 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372246 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1391922672 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5640631884 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7032554556 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 264066008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 576983002 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 841049010 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19999250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37322251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57321501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 309495 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 309495 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2215052922 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7795687242 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10010740164 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2479118930 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8372670244 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10851789174 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1043159500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1692820000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2735979500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 803109000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1311241000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2114350000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1846268500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3004061000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4850329500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018285 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008091 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010912 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017512 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007321 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245320 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.222603 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122886 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015430 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019964 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008968 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000114 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018055 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.007807 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014866 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020624 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.009057 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13221.802978 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13267.774790 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13255.421973 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35276.913567 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45203.707464 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42942.374463 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12789.180091 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14899.249795 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14221.091140 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15915.861813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12426.568293 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.560009 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14218.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14218.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21507.301340 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26949.033270 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25579.217590 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19931.303536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25316.281157 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23905.468212 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012261 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017952 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007759 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020546 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009001 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13854.845904 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13367.668800 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13498.858280 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.698281 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48377.991200 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46382.457285 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13152.662649 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13049.190384 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13081.502030 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15503.294574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12812.307243 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13638.234832 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 19343.437500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19343.437500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23455.350361 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28061.319979 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -874,142 +854,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1797406 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.544833 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100910374 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1797917 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.126269 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10928216250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.581873 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.468426 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.494533 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932777 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041931 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024403 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999111 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1799096 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 100909280 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1799607 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.072954 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10982089250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.173904 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.006307 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 13.353828 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931980 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041028 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.026082 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999090 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104556280 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104556280 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67125667 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21618827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 12165880 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100910374 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67125667 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21618827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 12165880 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100910374 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67125667 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21618827 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 12165880 # number of overall hits -system.cpu0.icache.overall_hits::total 100910374 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 867746 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 249012 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 731202 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1847960 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 867746 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 249012 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 731202 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1847960 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 867746 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 249012 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 731202 # number of overall misses -system.cpu0.icache.overall_misses::total 1847960 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3371834500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026972776 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13398807276 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 3371834500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 10026972776 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13398807276 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 3371834500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 10026972776 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13398807276 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67993413 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 21867839 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12897082 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102758334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67993413 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 21867839 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12897082 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102758334 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67993413 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 21867839 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12897082 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102758334 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012762 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011387 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056695 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 67893289 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 22031781 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 12835616 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 102760686 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67893289 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 22031781 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 12835616 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 102760686 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011358 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057480 # 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number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250227 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686028 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 936255 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 250227 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 686028 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 936255 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 250227 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 686028 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 936255 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3014176750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8498569729 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11512746479 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3014176750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8498569729 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11512746479 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3014176750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8498569729 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11512746479 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009111 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009111 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009111 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12296.592786 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1040,56 +1020,56 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1854 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1854 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 620 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1234 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1854 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1854 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1854 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1496 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9777.746658 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7722.280706 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6250.292235 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 511 34.16% 34.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 754 50.40% 84.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 15.37% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1496 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000015000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000015000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000015000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 885 59.16% 59.16% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 611 40.84% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1496 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 1874 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1874 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 637 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1237 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1874 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1874 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1874 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1601 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12056.839475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10248.777265 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6448.828751 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 390 24.36% 24.36% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 856 53.47% 77.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 354 22.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1601 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000015500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000015500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000015500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 972 60.71% 60.71% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 629 39.29% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1601 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1874 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1854 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1874 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1601 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1496 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3350 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1601 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3475 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4626652 # DTB read hits -system.cpu1.dtb.read_misses 1593 # DTB read misses -system.cpu1.dtb.write_hits 3288334 # DTB write hits -system.cpu1.dtb.write_misses 261 # DTB write misses -system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 4664064 # DTB read hits +system.cpu1.dtb.read_misses 1628 # DTB read misses +system.cpu1.dtb.write_hits 3297220 # DTB write hits +system.cpu1.dtb.write_misses 246 # DTB write misses +system.cpu1.dtb.flush_tlb 168 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1268 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1307 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4628245 # DTB read accesses -system.cpu1.dtb.write_accesses 3288595 # DTB write accesses +system.cpu1.dtb.perms_faults 60 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4665692 # DTB read accesses +system.cpu1.dtb.write_accesses 3297466 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7914986 # DTB hits -system.cpu1.dtb.misses 1854 # DTB misses -system.cpu1.dtb.accesses 7916840 # DTB accesses +system.cpu1.dtb.hits 7961284 # DTB hits +system.cpu1.dtb.misses 1874 # DTB misses +system.cpu1.dtb.accesses 7963158 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1119,129 +1099,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 832 # Table walker walks requested -system.cpu1.itb.walker.walksShort 832 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 221 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 611 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 832 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 612 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10456.699346 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8281.924765 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6395.528631 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 192 31.37% 31.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 1 0.16% 31.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 290 47.39% 78.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 12 1.96% 80.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 105 17.16% 98.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 12 1.96% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 876 # Table walker walks requested +system.cpu1.itb.walker.walksShort 876 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 230 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 646 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 876 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 876 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 876 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12877.167630 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11119.022104 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6272.001420 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 140 20.23% 20.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 230 33.24% 53.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 143 20.66% 74.13% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 156 22.54% 96.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 23 3.32% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 692 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 391 63.89% 63.89% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 221 36.11% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 612 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 462 66.76% 66.76% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 230 33.24% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 692 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 832 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 832 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 876 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 876 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 612 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 612 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1444 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 21867839 # ITB inst hits -system.cpu1.itb.inst_misses 832 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 692 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 692 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1568 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 22031781 # ITB inst hits +system.cpu1.itb.inst_misses 876 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 168 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 672 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 752 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21868671 # ITB inst accesses -system.cpu1.itb.hits 21867839 # DTB hits -system.cpu1.itb.misses 832 # DTB misses -system.cpu1.itb.accesses 21868671 # DTB accesses -system.cpu1.numCycles 158011786 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 22032657 # ITB inst accesses +system.cpu1.itb.hits 22031781 # DTB hits +system.cpu1.itb.misses 876 # DTB misses +system.cpu1.itb.accesses 22032657 # DTB accesses +system.cpu1.numCycles 158012603 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21167008 # Number of instructions committed -system.cpu1.committedOps 25384727 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22581810 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses -system.cpu1.num_func_calls 2402385 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2688390 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22581810 # number of integer instructions -system.cpu1.num_fp_insts 1738 # number of float instructions -system.cpu1.num_int_register_reads 41656503 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15851657 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92262793 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9324878 # number of times the CC registers were written -system.cpu1.num_mem_refs 8128633 # number of memory refs -system.cpu1.num_load_insts 4673659 # Number of load instructions -system.cpu1.num_store_insts 3454974 # Number of store instructions -system.cpu1.num_idle_cycles 151523982.353984 # Number of idle cycles -system.cpu1.num_busy_cycles 6487803.646016 # Number of busy cycles -system.cpu1.not_idle_fraction 0.041059 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.958941 # Percentage of idle cycles -system.cpu1.Branches 5241513 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17951469 68.78% 68.78% # Class of executed instruction -system.cpu1.op_class::IntMult 18860 0.07% 68.85% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1172 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::MemRead 4673659 17.91% 86.76% # Class of executed instruction -system.cpu1.op_class::MemWrite 3454974 13.24% 100.00% # Class of executed instruction +system.cpu1.committedInsts 21317281 # Number of instructions committed +system.cpu1.committedOps 25549926 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22701009 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1608 # Number of float alu accesses +system.cpu1.num_func_calls 2410952 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2737582 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22701009 # number of integer instructions +system.cpu1.num_fp_insts 1608 # number of float instructions +system.cpu1.num_int_register_reads 41843043 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15920660 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1288 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 92840963 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9448697 # number of times the CC registers were written +system.cpu1.num_mem_refs 8172131 # number of memory refs +system.cpu1.num_load_insts 4710232 # Number of load instructions +system.cpu1.num_store_insts 3461899 # Number of store instructions +system.cpu1.num_idle_cycles 151539718.287508 # Number of idle cycles +system.cpu1.num_busy_cycles 6472884.712492 # Number of busy cycles +system.cpu1.not_idle_fraction 0.040964 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.959036 # Percentage of idle cycles +system.cpu1.Branches 5298424 # Number of branches fetched +system.cpu1.op_class::No_OpClass 41 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 18071289 68.81% 68.81% # Class of executed instruction +system.cpu1.op_class::IntMult 19339 0.07% 68.88% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1186 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::MemRead 4710232 17.93% 86.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 3461899 13.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26100168 # Class of executed instruction +system.cpu1.op_class::total 26263986 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17449157 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9464735 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 398390 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10718645 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8165775 # Number of BTB hits +system.cpu2.branchPred.lookups 17390044 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9451928 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 400737 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10830418 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8125283 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 76.182904 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4093661 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 20704 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 75.022802 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4068079 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21097 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1271,92 +1250,88 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 43517 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 43517 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13970 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11118 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 18429 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 25088 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 493.961256 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 3141.545513 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-8191 24512 97.70% 97.70% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::8192-16383 373 1.49% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::16384-24575 135 0.54% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::24576-32767 33 0.13% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::32768-40959 15 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::40960-49151 7 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 25088 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 9234 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 11931.507147 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 9422.312939 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 7440.393288 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 2697 29.21% 29.21% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 4034 43.69% 72.89% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2262 24.50% 97.39% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 120 1.30% 98.69% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-40959 50 0.54% 99.23% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::40960-49151 64 0.69% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::49152-57343 4 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 9234 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 52111304876 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.433489 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.514696 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-1 52056176876 99.89% 99.89% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::2-3 40469500 0.08% 99.97% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-5 8303000 0.02% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::6-7 2155500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-9 1410500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::10-11 753500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-13 454000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::14-15 1056000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-17 83500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::18-19 122000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-21 61500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::22-23 86000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-25 164500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::26-27 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-29 4500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 52111304876 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 2902 72.88% 72.88% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 1080 27.12% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 3982 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43517 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 43271 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 43271 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13795 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11030 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 18446 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 24825 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 526.888218 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 3382.784717 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-16383 24602 99.10% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::16384-32767 180 0.73% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::32768-49151 23 0.09% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::49152-65535 14 0.06% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 24825 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 9018 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12445.276336 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10074.043051 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 7598.717395 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 2712 30.07% 30.07% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3866 42.87% 72.94% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2205 24.45% 97.39% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 103 1.14% 98.54% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-40959 58 0.64% 99.18% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::40960-49151 71 0.79% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 9018 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 60407494468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.614556 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.505382 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-1 60349981968 99.90% 99.90% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::2-3 42488500 0.07% 99.98% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-5 7802000 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::6-7 2924500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-9 1368500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-13 331000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::14-15 1040000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-17 124500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::18-19 121000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-21 186000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::22-23 81500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-25 109000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::26-27 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::30-31 75000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 60407494468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 2796 73.35% 73.35% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 1016 26.65% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 3812 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43271 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43517 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3982 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43271 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3812 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3982 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 47499 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3812 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 47083 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9677625 # DTB read hits -system.cpu2.dtb.read_misses 37716 # DTB read misses -system.cpu2.dtb.write_hits 7160348 # DTB write hits -system.cpu2.dtb.write_misses 5801 # DTB write misses -system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 9630626 # DTB read hits +system.cpu2.dtb.read_misses 37535 # DTB read misses +system.cpu2.dtb.write_hits 7130235 # DTB write hits +system.cpu2.dtb.write_misses 5736 # DTB write misses +system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2469 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 945 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 520 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 418 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9715341 # DTB read accesses -system.cpu2.dtb.write_accesses 7166149 # DTB write accesses +system.cpu2.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9668161 # DTB read accesses +system.cpu2.dtb.write_accesses 7135971 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16837973 # DTB hits -system.cpu2.dtb.misses 43517 # DTB misses -system.cpu2.dtb.accesses 16881490 # DTB accesses +system.cpu2.dtb.hits 16760861 # DTB hits +system.cpu2.dtb.misses 43271 # DTB misses +system.cpu2.dtb.accesses 16804132 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1386,387 +1361,396 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 6476 # Table walker walks requested -system.cpu2.itb.walker.walksShort 6476 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2218 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4151 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1246.035484 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 5374.992147 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-8191 6033 94.72% 94.72% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::8192-16383 153 2.40% 97.13% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::16384-24575 113 1.77% 98.90% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::24576-32767 28 0.44% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.30% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.13% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::49152-57343 9 0.14% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 1962 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12125.644750 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 9197.080965 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 8421.034460 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-8191 606 30.89% 30.89% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::8192-16383 818 41.69% 72.58% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::16384-24575 463 23.60% 96.18% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-32767 28 1.43% 97.60% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-40959 29 1.48% 99.08% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::40960-49151 11 0.56% 99.64% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::49152-57343 5 0.25% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::57344-65535 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::73728-81919 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 1962 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 4866645120 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.377306 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.486503 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 3033838520 62.34% 62.34% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 1830102100 37.61% 99.94% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 2122000 0.04% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 461500 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 4866645120 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 1443 77.79% 77.79% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 412 22.21% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 1855 # Table walker page sizes translated +system.cpu2.itb.walker.walks 6235 # Table walker walks requested +system.cpu2.itb.walker.walksShort 6235 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2044 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4088 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 6132 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1114.562948 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 4869.153513 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-8191 5831 95.09% 95.09% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::8192-16383 152 2.48% 97.57% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::16384-24575 99 1.61% 99.18% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::24576-32767 29 0.47% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-40959 9 0.15% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::40960-49151 4 0.07% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::49152-57343 3 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 6132 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 1857 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12539.311255 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10038.361952 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 8040.211817 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-4095 547 29.46% 29.46% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-8191 43 2.32% 31.77% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::8192-12287 410 22.08% 53.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-16383 373 20.09% 73.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-20479 9 0.48% 74.42% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::20480-24575 413 22.24% 96.66% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-28671 14 0.75% 97.42% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::28672-32767 13 0.70% 98.12% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-36863 11 0.59% 98.71% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::36864-40959 8 0.43% 99.14% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::40960-45055 10 0.54% 99.68% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::45056-49151 1 0.05% 99.73% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::53248-57343 2 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::57344-61439 1 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::61440-65535 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 1857 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 13162833212 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.828087 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.377922 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2265327000 17.21% 17.21% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 10895443212 82.77% 99.98% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 1802500 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 162000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 51500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 47000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 13162833212 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 1358 77.42% 77.42% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 396 22.58% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 1754 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6476 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6476 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6235 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6235 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1855 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1855 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 8331 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 12898498 # ITB inst hits -system.cpu2.itb.inst_misses 6476 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1754 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1754 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 7989 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 12837123 # ITB inst hits +system.cpu2.itb.inst_misses 6235 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1789 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1683 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1125 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12904974 # ITB inst accesses -system.cpu2.itb.hits 12898498 # DTB hits -system.cpu2.itb.misses 6476 # DTB misses -system.cpu2.itb.accesses 12904974 # DTB accesses -system.cpu2.numCycles 69896550 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12843358 # ITB inst accesses +system.cpu2.itb.hits 12837123 # DTB hits +system.cpu2.itb.misses 6235 # DTB misses +system.cpu2.itb.accesses 12843358 # DTB accesses +system.cpu2.numCycles 69616646 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26772867 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69167442 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17449157 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12259436 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39647350 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2075847 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 94572 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 925 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 261 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 361977 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 99094 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 575 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12897087 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269205 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2824 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 68015518 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.222532 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.345771 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26594039 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69071466 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17390044 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12193362 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39655163 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2070826 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 93322 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 302 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 323029 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 106475 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 727 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12835626 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269064 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67809362 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.223662 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.348600 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49396866 72.63% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2407853 3.54% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1558370 2.29% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4909650 7.22% 85.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1103212 1.62% 87.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 700919 1.03% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3889597 5.72% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 749830 1.10% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3299221 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49260090 72.64% 72.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2390617 3.53% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1561768 2.30% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4865604 7.18% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1097205 1.62% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 701816 1.03% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3870082 5.71% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 751059 1.11% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3311121 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 68015518 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249643 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.989569 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18660323 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36954486 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10395816 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1074729 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 929937 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1306815 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 109505 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59278443 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 354551 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 929937 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19281301 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4387069 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27167714 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10836297 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5412952 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56807794 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2395 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 934627 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 156415 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 3819110 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58701003 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260943920 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63689416 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4317 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48649356 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10051631 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 957722 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 893887 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6244990 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10262812 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7930622 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1370921 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1928187 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54587761 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 670112 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51973443 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68390 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7260181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18315253 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 68730 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 68015518 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.466174 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67809362 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249797 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.992169 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18546973 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36871218 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10413141 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1051163 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 926599 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1313756 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 110434 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59271705 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 356279 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 926599 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19159512 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 3828211 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27033628 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10840093 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 6021054 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56800254 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 1622 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 892733 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 160451 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4475802 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58727822 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260839498 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63695069 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4195 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48596346 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10131460 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 953771 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 889969 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6004915 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10275852 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7909386 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1396867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1932490 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54546075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 673336 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51866821 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68048 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7293157 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18430167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68913 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67809362 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.764892 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.469149 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47556774 69.92% 69.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6833375 10.05% 79.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5102327 7.50% 87.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4195165 6.17% 93.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1616653 2.38% 96.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1064575 1.57% 97.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1125788 1.66% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 361184 0.53% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 159677 0.23% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47470041 70.01% 70.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6738750 9.94% 79.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5086869 7.50% 87.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4143776 6.11% 93.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1653610 2.44% 95.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1071590 1.58% 97.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1124885 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 357423 0.53% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 162418 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 68015518 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67809362 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78584 9.71% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 374915 46.33% 56.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 355764 43.96% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 76711 9.73% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 2 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 365050 46.29% 56.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 346827 43.98% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34433275 66.25% 66.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39265 0.08% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2873 0.01% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9958899 19.16% 85.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7539012 14.51% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 102 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34390478 66.31% 66.31% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39542 0.08% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2888 0.01% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9917724 19.12% 85.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7516080 14.49% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51973443 # Type of FU issued -system.cpu2.iq.rate 0.743577 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 809264 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015571 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172830468 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 62550700 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50376095 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9590 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 5049 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4207 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52777410 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5187 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 265138 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51866821 # Type of FU issued +system.cpu2.iq.rate 0.745035 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 788590 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015204 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172390251 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62545050 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50322136 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9391 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4963 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4144 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52650258 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5051 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 268895 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1600472 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1933 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38461 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 793125 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1610409 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1859 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38198 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 800698 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 131320 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 120276 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 130635 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 68542 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 929937 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3246832 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 971285 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55360766 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 91934 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10262812 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7930622 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 358706 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 34253 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 928134 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38461 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 182765 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 162631 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 345396 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51539725 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9783295 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 390308 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 926599 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3277236 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 403345 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55328961 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 92252 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10275852 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7909386 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 360332 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 33301 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 361214 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38198 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 183568 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164696 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 348264 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51429187 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9738477 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 394455 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 102893 # number of nop insts executed -system.cpu2.iew.exec_refs 17248466 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9490874 # Number of branches executed -system.cpu2.iew.exec_stores 7465171 # Number of stores executed -system.cpu2.iew.exec_rate 0.737372 # Inst execution rate -system.cpu2.iew.wb_sent 51085657 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50380302 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26454346 # num instructions producing a value -system.cpu2.iew.wb_consumers 45953910 # num instructions consuming a value +system.cpu2.iew.exec_nop 109550 # number of nop insts executed +system.cpu2.iew.exec_refs 17180160 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9476518 # Number of branches executed +system.cpu2.iew.exec_stores 7441683 # Number of stores executed +system.cpu2.iew.exec_rate 0.738748 # Inst execution rate +system.cpu2.iew.wb_sent 51031347 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50326280 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26469079 # num instructions producing a value +system.cpu2.iew.wb_consumers 46041332 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.720784 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575671 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.722906 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.574898 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8107084 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 601382 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 290377 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66292417 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.712682 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.616986 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8143906 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 604423 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 291897 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66086949 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713825 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.622364 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48208105 72.72% 72.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8091600 12.21% 84.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3999207 6.03% 90.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1724132 2.60% 93.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 877027 1.32% 94.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 615427 0.93% 95.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1259890 1.90% 97.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 297840 0.45% 98.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1219189 1.84% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48131767 72.83% 72.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 7989880 12.09% 84.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3968576 6.01% 90.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1690353 2.56% 93.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 906489 1.37% 94.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 608385 0.92% 95.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1262051 1.91% 97.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 299318 0.45% 98.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1230130 1.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66292417 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38883433 # Number of instructions committed -system.cpu2.commit.committedOps 47245385 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66086949 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38874571 # Number of instructions committed +system.cpu2.commit.committedOps 47174544 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15799837 # Number of memory references committed -system.cpu2.commit.loads 8662340 # Number of loads committed -system.cpu2.commit.membars 225899 # Number of memory barriers committed -system.cpu2.commit.branches 8915887 # Number of branches committed -system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41357490 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1642928 # Number of function calls committed. +system.cpu2.commit.refs 15774131 # Number of memory references committed +system.cpu2.commit.loads 8665443 # Number of loads committed +system.cpu2.commit.membars 227144 # Number of memory barriers committed +system.cpu2.commit.branches 8900555 # Number of branches committed +system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41283041 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1636102 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31404754 66.47% 66.47% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 37921 0.08% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2873 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31359241 66.47% 66.47% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 38284 0.08% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2888 0.01% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8662340 18.33% 84.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7137497 15.11% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8665443 18.37% 84.93% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7108688 15.07% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47245385 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1219189 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 113003070 # The number of ROB reads -system.cpu2.rob.rob_writes 112431430 # The number of ROB writes -system.cpu2.timesIdled 280451 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1881032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5250223632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38822148 # Number of Instructions Simulated -system.cpu2.committedOps 47184100 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.800430 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.800430 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.555423 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.555423 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56420474 # number of integer regfile reads -system.cpu2.int_regfile_writes 31939226 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15888 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13694 # number of floating regfile writes -system.cpu2.cc_regfile_reads 182315650 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19227541 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124375401 # number of misc regfile reads -system.cpu2.misc_regfile_writes 481787 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30188 # Transaction distribution -system.iobus.trans_dist::ReadResp 30188 # Transaction distribution -system.iobus.trans_dist::WriteReq 59019 # Transaction distribution -system.iobus.trans_dist::WriteResp 22795 # Transaction distribution +system.cpu2.rob.rob_reads 112818862 # The number of ROB reads +system.cpu2.rob.rob_writes 112362949 # The number of ROB writes +system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1807284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5249914577 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38809335 # Number of Instructions Simulated +system.cpu2.committedOps 47109308 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.793812 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.793812 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.557472 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.557472 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56301107 # number of integer regfile reads +system.cpu2.int_regfile_writes 31916155 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15723 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13758 # number of floating regfile writes +system.cpu2.cc_regfile_reads 181999487 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19225356 # number of cc regfile writes +system.cpu2.misc_regfile_reads 123907195 # number of misc regfile reads +system.cpu2.misc_regfile_writes 485009 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30180 # Transaction distribution +system.iobus.trans_dist::ReadResp 30180 # Transaction distribution +system.iobus.trans_dist::WriteReq 59003 # Transaction distribution +system.iobus.trans_dist::WriteResp 22779 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54126 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1787,11 +1771,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105414 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67843 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1812,10 +1796,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159071 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480319 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) @@ -1838,29 +1822,29 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2807000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2714000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15727000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15729000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 217868633 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 124959118 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39885000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39808000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 22990014 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 23061006 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.993331 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.992064 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 245002453509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.993331 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062083 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062083 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 244950709509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.992064 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062004 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062004 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1874,14 +1858,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6024842691 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6024842691 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14419928 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 14858930 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14858930 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 4185043182 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 4185043182 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14858930 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14858930 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14858930 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14858930 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1898,347 +1882,347 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166321.849906 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 166321.849906 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34568 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 58964.007937 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 58964.007937 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 115532.331659 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 115532.331659 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 58964.007937 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 58964.007937 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 14316 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4486 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2165 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.705751 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.612471 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # 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number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4842542719 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627650 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627650 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # 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average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17738.895717 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17755.916242 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18167.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18167.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65686.761436 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69160.723564 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 68483.846284 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66339.060884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66339.060884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2393,55 +2377,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74222 # Transaction distribution -system.membus.trans_dist::ReadResp 74221 # Transaction distribution -system.membus.trans_dist::WriteReq 27571 # Transaction distribution -system.membus.trans_dist::WriteResp 27571 # Transaction distribution -system.membus.trans_dist::Writeback 129099 # Transaction distribution +system.membus.trans_dist::ReadReq 74250 # Transaction distribution +system.membus.trans_dist::ReadResp 74249 # Transaction distribution +system.membus.trans_dist::WriteReq 27555 # Transaction distribution +system.membus.trans_dist::WriteResp 27555 # Transaction distribution +system.membus.trans_dist::Writeback 129076 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4556 # Transaction distribution -system.membus.trans_dist::ReadExReq 137047 # Transaction distribution -system.membus.trans_dist::ReadExResp 137047 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4561 # Transaction distribution +system.membus.trans_dist::ReadExReq 137020 # Transaction distribution +system.membus.trans_dist::ReadExResp 137020 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105414 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 688049 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 578995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109017 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109017 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 688012 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159071 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16929468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17092587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21735083 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 289 # Total snoops (count) -system.membus.snoop_fanout::samples 341035 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17091899 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 283 # Total snoops (count) +system.membus.snoop_fanout::samples 341064 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 341035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 341064 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 341035 # Request fanout histogram -system.membus.reqLayer0.occupancy 40827000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 341064 # Request fanout histogram +system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 469500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 937138500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 565034415 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 904275509 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 525270598 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23892986 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 23441994 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2474,54 +2458,52 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2442249 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2442245 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 692729 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22736 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2441800 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2441792 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27555 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27555 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 690587 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22777 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296542 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296542 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3613854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484499 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29280 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87986 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6215619 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115099320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97925875 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213229367 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51973 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3430536 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102566 # Request fanout histogram +system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3617238 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29055 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6212277 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115207096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97661699 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51752 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3427725 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010649 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102642 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3394060 98.94% 98.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3391224 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36501 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3430536 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2377189197 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3427725 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4188720502 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2021336108 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12001413 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1406471499 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 694961258 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 11749485 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39606873 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39124219 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 355e87caf..ec623239f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.814515 # Number of seconds simulated -sim_ticks 2814515403000 # Number of ticks simulated -final_tick 2814515403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804323 # Number of seconds simulated +sim_ticks 2804323403500 # Number of ticks simulated +final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109456 # Simulator instruction rate (inst/s) -host_op_rate 132849 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2632808896 # Simulator tick rate (ticks/s) -host_mem_usage 624704 # Number of bytes of host memory used -host_seconds 1069.02 # Real time elapsed on the host -sim_insts 117010217 # Number of instructions simulated -sim_ops 142017883 # Number of ops (including micro ops) simulated +host_inst_rate 111168 # Simulator instruction rate (inst/s) +host_op_rate 134929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2664755466 # Simulator tick rate (ticks/s) +host_mem_usage 625128 # Number of bytes of host memory used +host_seconds 1052.38 # Real time elapsed on the host +sim_insts 116990114 # Number of instructions simulated +sim_ops 141995948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 4416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 748224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5094496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 629568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4721220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 690752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4838852 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11203044 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 748224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 629568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1377792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8429952 # Number of bytes written to this memory +system.physmem.bytes_read::total 11215652 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8426048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8447476 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 69 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8443572 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11691 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 64 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 73770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75608 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131718 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175764 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1569 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136038 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 265845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1810079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 223686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1677454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3980452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 223686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2995170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6223 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 246317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1725497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3999415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3004663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3001396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2995170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3010912 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3004663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1816303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 223686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1677457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6981848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175568 # Number of read requests accepted -system.physmem.writeReqs 172295 # Number of write requests accepted -system.physmem.readBursts 175568 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 172295 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11229120 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 10657088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11203108 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10764020 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5755 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4657 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11278 # Per bank write bursts -system.physmem.perBankRdBursts::1 11187 # Per bank write bursts -system.physmem.perBankRdBursts::2 11389 # Per bank write bursts -system.physmem.perBankRdBursts::3 10916 # Per bank write bursts -system.physmem.perBankRdBursts::4 11527 # Per bank write bursts -system.physmem.perBankRdBursts::5 11542 # Per bank write bursts -system.physmem.perBankRdBursts::6 11806 # Per bank write bursts -system.physmem.perBankRdBursts::7 11898 # Per bank write bursts -system.physmem.perBankRdBursts::8 10235 # Per bank write bursts -system.physmem.perBankRdBursts::9 10554 # Per bank write bursts -system.physmem.perBankRdBursts::10 10596 # Per bank write bursts -system.physmem.perBankRdBursts::11 9816 # Per bank write bursts -system.physmem.perBankRdBursts::12 10461 # Per bank write bursts -system.physmem.perBankRdBursts::13 11360 # Per bank write bursts -system.physmem.perBankRdBursts::14 10541 # Per bank write bursts -system.physmem.perBankRdBursts::15 10349 # Per bank write bursts -system.physmem.perBankWrBursts::0 10520 # Per bank write bursts -system.physmem.perBankWrBursts::1 10540 # Per bank write bursts -system.physmem.perBankWrBursts::2 10805 # Per bank write bursts -system.physmem.perBankWrBursts::3 10377 # Per bank write bursts -system.physmem.perBankWrBursts::4 10808 # Per bank write bursts -system.physmem.perBankWrBursts::5 10825 # Per bank write bursts -system.physmem.perBankWrBursts::6 10943 # Per bank write bursts -system.physmem.perBankWrBursts::7 10998 # Per bank write bursts -system.physmem.perBankWrBursts::8 9971 # Per bank write bursts -system.physmem.perBankWrBursts::9 10108 # Per bank write bursts -system.physmem.perBankWrBursts::10 9937 # Per bank write bursts -system.physmem.perBankWrBursts::11 9693 # Per bank write bursts -system.physmem.perBankWrBursts::12 10233 # Per bank write bursts -system.physmem.perBankWrBursts::13 10896 # Per bank write bursts -system.physmem.perBankWrBursts::14 10053 # Per bank write bursts -system.physmem.perBankWrBursts::15 9810 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 246317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1725500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7010327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175765 # Number of read requests accepted +system.physmem.writeReqs 172232 # Number of write requests accepted +system.physmem.readBursts 175765 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11215716 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11568 # Per bank write bursts +system.physmem.perBankRdBursts::1 11615 # Per bank write bursts +system.physmem.perBankRdBursts::2 11475 # Per bank write bursts +system.physmem.perBankRdBursts::3 10984 # Per bank write bursts +system.physmem.perBankRdBursts::4 11566 # Per bank write bursts +system.physmem.perBankRdBursts::5 11265 # Per bank write bursts +system.physmem.perBankRdBursts::6 12051 # Per bank write bursts +system.physmem.perBankRdBursts::7 11828 # Per bank write bursts +system.physmem.perBankRdBursts::8 10136 # Per bank write bursts +system.physmem.perBankRdBursts::9 10546 # Per bank write bursts +system.physmem.perBankRdBursts::10 10466 # Per bank write bursts +system.physmem.perBankRdBursts::11 9460 # Per bank write bursts +system.physmem.perBankRdBursts::12 10169 # Per bank write bursts +system.physmem.perBankRdBursts::13 11261 # Per bank write bursts +system.physmem.perBankRdBursts::14 10850 # Per bank write bursts +system.physmem.perBankRdBursts::15 10383 # Per bank write bursts +system.physmem.perBankWrBursts::0 9594 # Per bank write bursts +system.physmem.perBankWrBursts::1 9874 # Per bank write bursts +system.physmem.perBankWrBursts::2 9855 # Per bank write bursts +system.physmem.perBankWrBursts::3 9284 # Per bank write bursts +system.physmem.perBankWrBursts::4 9607 # Per bank write bursts +system.physmem.perBankWrBursts::5 9407 # Per bank write bursts +system.physmem.perBankWrBursts::6 10082 # Per bank write bursts +system.physmem.perBankWrBursts::7 9751 # Per bank write bursts +system.physmem.perBankWrBursts::8 8758 # Per bank write bursts +system.physmem.perBankWrBursts::9 9037 # Per bank write bursts +system.physmem.perBankWrBursts::10 8724 # Per bank write bursts +system.physmem.perBankWrBursts::11 8208 # Per bank write bursts +system.physmem.perBankWrBursts::12 8857 # Per bank write bursts +system.physmem.perBankWrBursts::13 9711 # Per bank write bursts +system.physmem.perBankWrBursts::14 9203 # Per bank write bursts +system.physmem.perBankWrBursts::15 8690 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2814515217000 # Total gap between requests +system.physmem.numWrRetry 53 # Number of times write queue was full causing retry +system.physmem.totGap 2804323239500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175013 # Read request sizes (log2) +system.physmem.readPktSize::6 175210 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167914 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167851 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -161,198 +161,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.722260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.177109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 345.277059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24335 36.33% 36.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15823 23.62% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6599 9.85% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3701 5.52% 75.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2840 4.24% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1617 2.41% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1134 1.69% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1090 1.63% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9848 14.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66987 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.589488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 462.801411 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7132 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.338052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.587494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.995044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 12 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.08% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 5 0.07% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.08% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5911 82.85% 83.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 110 1.54% 84.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 53 0.74% 85.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 225 3.15% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 144 2.02% 90.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.70% 91.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.50% 91.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 29 0.41% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 105 1.47% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.24% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.14% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.20% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.43% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 18 0.25% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.13% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 33 0.46% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 56 0.78% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.20% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.08% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 11 0.15% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 75 1.05% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.11% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 14 0.20% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 17 0.24% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.07% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.08% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 32 0.45% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.10% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.07% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 7 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads -system.physmem.totQLat 2670855500 # Total ticks spent queuing -system.physmem.totMemAccLat 5960636750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15222.45 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 112 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.556969 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.654540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.497717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24476 37.10% 37.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15740 23.86% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6623 10.04% 71.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3719 5.64% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2901 4.40% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1575 2.39% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1142 1.73% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1107 1.68% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8692 13.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.843324 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 438.660877 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6303 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6306 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6306 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.571519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.321112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 39.451011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 32 0.51% 0.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5917 93.83% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 88 1.40% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 21 0.33% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.25% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 33 0.52% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 35 0.56% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 27 0.43% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.21% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 20 0.32% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 8 0.13% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.08% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.14% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.10% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 11 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads +system.physmem.totQLat 2686689750 # Total ticks spent queuing +system.physmem.totMemAccLat 5979621000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15298.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33972.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.79 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34048.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.20 # Average write queue length when enqueuing -system.physmem.readRowHits 145151 # Number of row buffer hits during reads -system.physmem.writeRowHits 129833 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing +system.physmem.readRowHits 145297 # Number of row buffer hits during reads +system.physmem.writeRowHits 112992 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes -system.physmem.avgGap 8090872.61 # Average gap between requests -system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 265386240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 144804000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 714027600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 556087680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183830200320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 77881590900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1620389778750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1883781875490 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.310395 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2695567326750 # Time in different power states -system.physmem_0.memoryStateTime::REF 93982720000 # Time in different power states +system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes +system.physmem.avgGap 8058469.58 # Average gap between requests +system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 720337800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 501901920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183164495280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 78122450385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614063177750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876980625350 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.317704 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685041541216 # Time in different power states +system.physmem_0.memoryStateTime::REF 93642380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24965345250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25639471784 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241035480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131517375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654513600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 522942480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183830200320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 77208822180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1620979926750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1883568958185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.234745 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2696551299250 # Time in different power states -system.physmem_1.memoryStateTime::REF 93982720000 # Time in different power states +system.physmem_1.actEnergy 234632160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128023500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 649513800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 461298240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183164495280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 76868306460 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615163304000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876669573440 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.206785 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2686874826210 # Time in different power states +system.physmem_1.memoryStateTime::REF 93642380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23977600750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23802212540 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory @@ -360,27 +335,27 @@ system.realview.nvmem.bytes_inst_read::cpu0.inst 640 system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 227 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 227 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 227 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 227 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 227 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 227 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 27466718 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14314218 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 559197 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 17107445 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12928393 # Number of BTB hits +system.cpu0.branchPred.lookups 26894348 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13975310 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 545296 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16832825 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12628735 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.571735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6777363 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30194 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.024454 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6673545 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29900 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,96 +386,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 58720 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58720 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19962 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14154 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24604 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 34116 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 475.187595 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3075.067201 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 33369 97.81% 97.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 426 1.25% 99.06% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 228 0.67% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 49 0.14% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 15 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 34116 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12972 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12168.830173 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9642.893366 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7992.253434 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 3564 27.47% 27.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 6077 46.85% 74.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2864 22.08% 96.40% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 230 1.77% 98.17% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 90 0.69% 98.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 115 0.89% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 10 0.08% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::73728-81919 10 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 4 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 2 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-106495 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12972 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 78620736948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.741175 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.458010 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 78549397948 99.91% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 52259000 0.07% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 9664500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3325500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2093000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1088000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 676500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1423500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 291000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 117500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 73500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 71500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 138500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 78620736948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3790 68.96% 68.96% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1706 31.04% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5496 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58720 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 59638 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 59638 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19278 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14808 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 25552 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 34086 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 541.028575 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3545.315816 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 33770 99.07% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 252 0.74% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 35 0.10% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 20 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-147455 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 34086 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 11896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11442.270763 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9167.474880 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7450.500727 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 3982 33.47% 33.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5461 45.91% 79.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2160 18.16% 97.54% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 140 1.18% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-40959 47 0.40% 99.11% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::40960-49151 93 0.78% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-57343 3 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-73727 4 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 11896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 76466975540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.696036 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.478552 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 76445440540 99.97% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 15483000 0.02% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 3531500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 1916000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 394500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 120500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 34000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 54000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 76466975540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3544 69.19% 69.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1578 30.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5122 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 59638 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58720 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 59638 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5122 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5496 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 64216 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5122 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 64760 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14377700 # DTB read hits -system.cpu0.dtb.read_misses 50689 # DTB read misses -system.cpu0.dtb.write_hits 10391095 # DTB write hits -system.cpu0.dtb.write_misses 8031 # DTB write misses +system.cpu0.dtb.read_hits 13978309 # DTB read hits +system.cpu0.dtb.read_misses 51149 # DTB read misses +system.cpu0.dtb.write_hits 10338750 # DTB write hits +system.cpu0.dtb.write_misses 8489 # DTB write misses system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1016 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1359 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3463 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 922 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1428 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 592 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14428389 # DTB read accesses -system.cpu0.dtb.write_accesses 10399126 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14029458 # DTB read accesses +system.cpu0.dtb.write_accesses 10347239 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24768795 # DTB hits -system.cpu0.dtb.misses 58720 # DTB misses -system.cpu0.dtb.accesses 24827515 # DTB accesses +system.cpu0.dtb.hits 24317059 # DTB hits +system.cpu0.dtb.misses 59638 # DTB misses +system.cpu0.dtb.accesses 24376697 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -530,636 +493,640 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 8876 # Table walker walks requested -system.cpu0.itb.walker.walksShort 8876 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3394 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5333 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 149 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 8727 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1034.949009 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 4440.773831 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 8334 95.50% 95.50% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 202 2.31% 97.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 114 1.31% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 44 0.50% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 18 0.21% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 9 0.10% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 8727 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2584 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12070.828560 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9384.773588 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7691.454372 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 754 29.18% 29.18% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1107 42.84% 72.02% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 648 25.08% 97.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 49 1.90% 98.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 17 0.66% 99.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 4 0.15% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 8503 # Table walker walks requested +system.cpu0.itb.walker.walksShort 8503 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5069 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 128 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 8375 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1173.014925 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 5467.905811 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 7973 95.20% 95.20% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 197 2.35% 97.55% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 109 1.30% 98.85% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 49 0.59% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 12 0.14% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 14 0.17% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 5 0.06% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 7 0.08% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 4 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::90112-98303 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 8375 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2444 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12500.308511 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9992.698413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7939.202624 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 801 32.77% 32.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 949 38.83% 71.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 632 25.86% 97.46% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 25 1.02% 98.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 0.98% 99.47% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 9 0.37% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2584 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 31375770192 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.875900 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.330034 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3896845928 12.42% 12.42% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 27476174764 87.57% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2435000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 275000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 39500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 31375770192 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1855 76.18% 76.18% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 580 23.82% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2435 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2444 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 29185295284 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.914937 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.279656 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 2486739500 8.52% 8.52% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 26695454284 91.47% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2358500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 523000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 145500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 74500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 29185295284 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1760 75.99% 75.99% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 556 24.01% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2316 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8876 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8503 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8503 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2435 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2435 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 11311 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20634228 # ITB inst hits -system.cpu0.itb.inst_misses 8876 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2316 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2316 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10819 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20234859 # ITB inst hits +system.cpu0.itb.inst_misses 8503 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2373 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2268 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1477 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1416 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20643104 # ITB inst accesses -system.cpu0.itb.hits 20634228 # DTB hits -system.cpu0.itb.misses 8876 # DTB misses -system.cpu0.itb.accesses 20643104 # DTB accesses -system.cpu0.numCycles 108167671 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20243362 # ITB inst accesses +system.cpu0.itb.hits 20234859 # DTB hits +system.cpu0.itb.misses 8503 # DTB misses +system.cpu0.itb.accesses 20243362 # DTB accesses +system.cpu0.numCycles 106376136 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40851007 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106236775 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 27466718 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19705756 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62062972 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3267693 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 153669 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 7048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 432 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 489783 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 144519 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20632894 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 382391 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3679 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105343442 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.211364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.309053 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39965142 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 103919162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26894348 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19302280 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61475471 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3204102 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133084 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4359 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 386 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 482542 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 142714 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20233629 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 371892 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3629 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103806101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.204244 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.303663 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 76103279 72.24% 72.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3910098 3.71% 75.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2412212 2.29% 78.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8199484 7.78% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1671331 1.59% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1069053 1.01% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6251821 5.93% 94.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1074556 1.02% 95.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4651608 4.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75119256 72.36% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3853264 3.71% 76.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2394905 2.31% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8055629 7.76% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1633408 1.57% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1025690 0.99% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6108914 5.88% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1037923 1.00% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4577112 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105343442 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.253927 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.982149 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28225112 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58231710 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15904811 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1498973 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1482577 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1930879 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 153387 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 88028064 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 497001 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1482577 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 29091969 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7814173 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44573853 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16523893 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5856699 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 84168015 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2790 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1211369 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 234681 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3674238 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86834114 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 387462225 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93765985 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6215 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72808994 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14025104 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1551576 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1456348 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8924255 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15135142 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11528605 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1955130 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2746979 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80972727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1061733 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77600115 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 93477 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10225467 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 25113988 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116264 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105343442 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.736639 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.430545 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103806101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.252823 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.976903 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27584011 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 57734540 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15584006 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1449686 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1453608 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1869283 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 150514 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 86108463 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 484067 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1453608 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28423517 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6508141 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43695790 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16185317 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7539460 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 82326363 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3052 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1072870 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 278724 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5472953 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 84763927 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 379438570 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 91864230 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6406 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 71037693 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13726234 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1533064 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1439152 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8446360 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14835811 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11457004 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1997727 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2772041 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 79153572 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1058697 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 75784801 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96696 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10015024 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24599963 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 115562 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103806101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.730061 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.422275 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74430085 70.65% 70.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10248464 9.73% 80.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7900647 7.50% 87.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6607763 6.27% 94.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2341378 2.22% 96.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1506364 1.43% 97.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1572871 1.49% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 494450 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 241420 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73542195 70.85% 70.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10050115 9.68% 80.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7748986 7.46% 87.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6432670 6.20% 94.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2352911 2.27% 96.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1476701 1.42% 97.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1498599 1.44% 99.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 479431 0.46% 99.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 224493 0.22% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105343442 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103806101 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 114775 10.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 538516 46.90% 56.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 494955 43.11% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 98458 8.93% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 516893 46.87% 55.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 487368 44.20% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2213 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51768146 66.71% 66.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57542 0.07% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4481 0.01% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14787493 19.06% 85.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10980227 14.15% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2186 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 50425393 66.54% 66.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57237 0.08% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4320 0.01% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14387296 18.98% 85.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10908366 14.39% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77600115 # Type of FU issued -system.cpu0.iq.rate 0.717406 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1148249 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014797 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 261771758 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 92305365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 75123288 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 13640 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7254 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5910 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78738792 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7359 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 349889 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 75784801 # Type of FU issued +system.cpu0.iq.rate 0.712423 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1102720 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014551 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 256560915 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 90272679 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 73457837 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14204 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7628 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6340 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 76877738 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7597 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 359549 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2246274 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2500 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53675 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1142950 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2204717 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2719 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54058 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1152347 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 210780 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 206750 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 205467 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94593 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1482577 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5380945 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2158862 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 82157406 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 132522 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15135142 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11528605 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 554173 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44324 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2102450 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53675 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 259338 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 224546 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 483884 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76981591 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14546003 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 559940 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1453608 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5664191 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 635354 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80356167 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 128884 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14835811 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11457004 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 551529 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43992 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 579512 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54058 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 250397 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 220538 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 470935 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 75169409 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14142783 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 555867 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 122946 # number of nop insts executed -system.cpu0.iew.exec_refs 25419191 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14512373 # Number of branches executed -system.cpu0.iew.exec_stores 10873188 # Number of stores executed -system.cpu0.iew.exec_rate 0.711688 # Inst execution rate -system.cpu0.iew.wb_sent 76311316 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 75129198 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 39246313 # num instructions producing a value -system.cpu0.iew.wb_consumers 68010606 # num instructions consuming a value +system.cpu0.iew.exec_nop 143898 # number of nop insts executed +system.cpu0.iew.exec_refs 24942986 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14187310 # Number of branches executed +system.cpu0.iew.exec_stores 10800203 # Number of stores executed +system.cpu0.iew.exec_rate 0.706638 # Inst execution rate +system.cpu0.iew.wb_sent 74627910 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 73464177 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38231116 # num instructions producing a value +system.cpu0.iew.wb_consumers 66477839 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.694562 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.577062 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.690608 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575096 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11503261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 945469 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 407891 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102758261 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686747 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.577053 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11279021 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 943135 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 396816 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101272480 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681216 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.570732 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75291319 73.27% 73.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12321005 11.99% 85.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6288153 6.12% 91.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2655881 2.58% 93.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1298740 1.26% 95.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 839233 0.82% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1891164 1.84% 97.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 416236 0.41% 98.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1756530 1.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74367990 73.43% 73.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12119249 11.97% 85.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6128079 6.05% 91.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2581969 2.55% 94.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1298466 1.28% 95.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 821679 0.81% 96.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1839446 1.82% 97.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 396658 0.39% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1718944 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102758261 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 58183568 # Number of instructions committed -system.cpu0.commit.committedOps 70568955 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101272480 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56718354 # Number of instructions committed +system.cpu0.commit.committedOps 68988407 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23274523 # Number of memory references committed -system.cpu0.commit.loads 12888868 # Number of loads committed -system.cpu0.commit.membars 375842 # Number of memory barriers committed -system.cpu0.commit.branches 13706650 # Number of branches committed -system.cpu0.commit.fp_insts 5838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61788721 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2663542 # Number of function calls committed. +system.cpu0.commit.refs 22935751 # Number of memory references committed +system.cpu0.commit.loads 12631094 # Number of loads committed +system.cpu0.commit.membars 378784 # Number of memory barriers committed +system.cpu0.commit.branches 13402892 # Number of branches committed +system.cpu0.commit.fp_insts 6286 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 60396974 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2623511 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 47234123 66.93% 66.93% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55828 0.08% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4481 0.01% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12888868 18.26% 85.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10385655 14.72% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 45992810 66.67% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55529 0.08% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4317 0.01% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12631094 18.31% 85.06% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10304657 14.94% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70568955 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1756530 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 68988407 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1718944 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 170410924 # The number of ROB reads -system.cpu0.rob.rob_writes 166734025 # The number of ROB writes -system.cpu0.timesIdled 403289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2824229 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2462180705 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 58113002 # Number of Instructions Simulated -system.cpu0.committedOps 70498389 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.861333 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.861333 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.537249 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.537249 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83710036 # number of integer regfile reads -system.cpu0.int_regfile_writes 47877732 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16593 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13071 # number of floating regfile writes -system.cpu0.cc_regfile_reads 272135235 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28380305 # number of cc regfile writes -system.cpu0.misc_regfile_reads 192072102 # number of misc regfile reads -system.cpu0.misc_regfile_writes 725098 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 853107 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984634 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42535549 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853619 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.829665 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 327.353563 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 184.631071 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.639362 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.360608 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 167372763 # The number of ROB reads +system.cpu0.rob.rob_writes 163072923 # The number of ROB writes +system.cpu0.timesIdled 393865 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2570035 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956119679 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56633353 # Number of Instructions Simulated +system.cpu0.committedOps 68903406 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.878330 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.878330 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.532388 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.532388 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 81817364 # number of integer regfile reads +system.cpu0.int_regfile_writes 46775146 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16878 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13235 # number of floating regfile writes +system.cpu0.cc_regfile_reads 265909763 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27649979 # number of cc regfile writes +system.cpu0.misc_regfile_reads 189136920 # number of misc regfile reads +system.cpu0.misc_regfile_writes 724107 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 853909 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.982202 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42514992 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 854421 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.758833 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105520250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.898512 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.083689 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.361130 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189955198 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189955198 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12681674 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12667533 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25349207 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7766233 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8148068 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15914301 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180331 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362063 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209455 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237675 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 447130 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 215313 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 244405 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459718 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20447907 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20815601 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41263508 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20629639 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 20995932 # number of overall hits -system.cpu0.dcache.overall_hits::total 41625571 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 429725 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 402525 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 832250 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1921923 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1778424 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3700347 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 98138 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84449 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 182587 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14201 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27709 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 30 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 48 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 78 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2351648 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2180949 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4532597 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2449786 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2265398 # number of overall misses -system.cpu0.dcache.overall_misses::total 4715184 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7060794359 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6694788448 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13755582807 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 83430874942 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 75332466558 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 158763341500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 183117244 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 210458494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 393575738 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 643510 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 802514 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1446024 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90491669301 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 82027255006 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 172518924307 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90491669301 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 82027255006 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 172518924307 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13111399 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13070058 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26181457 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9688156 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9926492 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19614648 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 279870 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 264780 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 544650 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 222963 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 251876 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474839 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 215343 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 244453 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459796 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22799555 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 22996550 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45796105 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 23079425 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23261330 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46340755 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032775 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030797 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031788 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198379 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.179159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188652 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.350656 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318940 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335237 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060584 # 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average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16719.041667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38480.108120 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37610.808417 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 38061.827316 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36938.601699 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36208.761112 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36587.951670 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1102752 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 157342 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 69674 # 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average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14831.790014 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14027.664046 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22190.761905 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15691.205882 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18172.854545 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39035.625781 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39640.830200 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39325.589273 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37691.408957 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37911.739516 # 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number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10014883855 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20569700359 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3162299001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2622267000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784566001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2409236377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2026898500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436134877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5571535378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4649165500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220700878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016314 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016231 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016273 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015916 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014619 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015259 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228971 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.217977 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223626 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020800 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019653 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000139 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000196 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000170 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016145 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015535 # mshr miss rate for demand accesses +system.cpu0.dcache.writebacks::writebacks 704443 # number of writebacks +system.cpu0.dcache.writebacks::total 704443 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195410 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211050 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 406460 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1794100 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1602957 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3397057 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9538 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8888 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18426 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1989510 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1814007 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3803517 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1989510 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1814007 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3803517 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212943 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 212430 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 425373 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156357 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143233 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299590 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 58111 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64761 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 122872 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4275 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5151 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9426 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 34 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 55 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369300 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 355663 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 724963 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7110951020 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6670158760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13781109780 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 777722500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 894500250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672222750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53569251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82009500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 135578751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434494 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 482499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 916993 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10022603680 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9616681406 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 19639285086 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10800326180 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733312000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840493500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870048500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351685377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016241 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.221327 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.229006 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225309 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019122 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020518 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019860 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000097 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000120 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016444 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015255 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.015839 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018726 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017839 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018281 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13459.810248 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13814.398698 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13636.369151 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43455.547807 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42615.796337 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43048.411223 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15217.292063 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15598.127140 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15397.757073 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11710.603714 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15295.572056 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13723.210780 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19449.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14718.458333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26024.759694 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25513.288591 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25772.848816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24422.269665 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24134.227515 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24281.175097 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018812 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017817 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018305 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13673.389874 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13870.558047 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13771.855068 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45478.942548 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46568.589361 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45999.899129 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13383.395571 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13812.329180 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13609.469611 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12530.818947 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15921.083285 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14383.487269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20690.190476 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14191.147059 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16672.600000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27139.462984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27038.745683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1170,150 +1137,150 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1946899 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.580862 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39112552 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1947411 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.084385 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9482142250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.928996 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 235.651865 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.538924 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.460258 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1944350 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39122099 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1944862 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.115617 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9678062250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 228.929190 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 282.638021 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.447127 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.552027 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999155 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43147534 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43147534 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19581661 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19530891 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39112552 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19581661 # 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mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047195 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.980837 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27252662 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14161158 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 545075 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17238794 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12795126 # Number of BTB hits +system.cpu1.branchPred.lookups 27831531 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 557776 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17618092 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 13095982 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.222860 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6755804 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29339 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.332578 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6872630 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 30030 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1343,94 +1310,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 58706 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58706 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19477 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14176 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25053 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33653 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 557.840311 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3475.112155 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-8191 32827 97.55% 97.55% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-16383 501 1.49% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-24575 206 0.61% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-32767 52 0.15% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-40959 23 0.07% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-49151 18 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-57343 14 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-73727 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::81920-90111 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::90112-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-106495 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33653 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 11554 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10457.034101 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8151.140813 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7042.402736 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4078 35.30% 35.30% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5524 47.81% 83.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1648 14.26% 97.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 166 1.44% 98.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 76 0.66% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 59 0.51% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 11554 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 82024244244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.681515 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.487291 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 81955384244 99.92% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 50513000 0.06% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 9145000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 3183000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 1958500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1084000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 660000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 995500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 376500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 124000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 98500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 69500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 91500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 76000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 274000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 211000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 82024244244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3372 68.52% 68.52% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1549 31.48% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 4921 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 58148 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58148 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20423 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13441 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 24284 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33864 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 507.057642 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3287.460249 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 33558 99.10% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 245 0.72% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 40 0.12% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 33864 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 11833 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12004.944308 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9742.881321 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7470.572043 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3519 29.74% 29.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5647 47.72% 77.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2322 19.62% 97.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 174 1.47% 98.55% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 60 0.51% 99.06% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 104 0.88% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 11833 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 89903617428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.686126 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.480378 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 89833985928 99.92% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 50516000 0.06% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 9974500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 3130500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 1885500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1212500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 715000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1356000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 345000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 227000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 44000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 32500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 52500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 95000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 89903617428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3585 68.60% 68.60% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1641 31.40% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5226 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58148 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58706 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4921 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5226 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4921 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 63627 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5226 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14299827 # DTB read hits -system.cpu1.dtb.read_misses 48713 # DTB read misses -system.cpu1.dtb.write_hits 10649623 # DTB write hits -system.cpu1.dtb.write_misses 9993 # DTB write misses -system.cpu1.dtb.flush_tlb 175 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14522718 # DTB read hits +system.cpu1.dtb.read_misses 49745 # DTB read misses +system.cpu1.dtb.write_hits 10695995 # DTB write hits +system.cpu1.dtb.write_misses 8403 # DTB write misses +system.cpu1.dtb.flush_tlb 177 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3345 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 749 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 922 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14348540 # DTB read accesses -system.cpu1.dtb.write_accesses 10659616 # DTB write accesses +system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14572463 # DTB read accesses +system.cpu1.dtb.write_accesses 10704398 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 24949450 # DTB hits -system.cpu1.dtb.misses 58706 # DTB misses -system.cpu1.dtb.accesses 25008156 # DTB accesses +system.cpu1.dtb.hits 25218713 # DTB hits +system.cpu1.dtb.misses 58148 # DTB misses +system.cpu1.dtb.accesses 25276861 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1460,392 +1421,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7607 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7607 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2551 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4918 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 138 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7469 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1253.983130 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 5505.331618 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 7086 94.87% 94.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 200 2.68% 97.55% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 109 1.46% 99.01% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 32 0.43% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 14 0.19% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 11 0.15% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7469 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2377 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11683.850652 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8982.900240 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7620.243918 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 698 29.36% 29.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 50 2.10% 31.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 916 38.54% 70.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 82 3.45% 73.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 34 1.43% 74.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 536 22.55% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 1.09% 98.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.17% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 7 0.29% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 0.72% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 6 0.25% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2377 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 26182117896 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.680154 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.466824 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 8377919500 32.00% 32.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 17801455396 67.99% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2155000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 325500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 194500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 68000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 26182117896 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1688 75.39% 75.39% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 551 24.61% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2239 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7828 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7828 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2631 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5055 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 142 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7686 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1468.839448 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6467.961047 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7241 94.21% 94.21% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 210 2.73% 96.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 113 1.47% 98.41% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 52 0.68% 99.09% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 17 0.22% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 18 0.23% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 9 0.12% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 10 0.13% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 7 0.09% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 6 0.08% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7686 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2491 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12581.694099 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10170.903635 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7854.515527 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 763 30.63% 30.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1045 41.95% 72.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 622 24.97% 97.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 29 1.16% 98.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 22 0.88% 99.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.24% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2491 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 25478819488 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.779989 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.414945 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 5610872428 22.02% 22.02% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 19864341560 77.96% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2357000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 850000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 398500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 25478819488 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1770 75.35% 75.35% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 579 24.65% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7607 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7607 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7828 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7828 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2239 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2239 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 9846 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20569517 # ITB inst hits -system.cpu1.itb.inst_misses 7607 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10177 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20979938 # ITB inst hits +system.cpu1.itb.inst_misses 7828 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 175 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 177 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2207 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2294 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1289 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1372 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20577124 # ITB inst accesses -system.cpu1.itb.hits 20569517 # DTB hits -system.cpu1.itb.misses 7607 # DTB misses -system.cpu1.itb.accesses 20577124 # DTB accesses -system.cpu1.numCycles 107002102 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20987766 # ITB inst accesses +system.cpu1.itb.hits 20979938 # DTB hits +system.cpu1.itb.misses 7828 # DTB misses +system.cpu1.itb.accesses 20987766 # DTB accesses +system.cpu1.numCycles 108755615 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40500350 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106310459 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27252662 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19550930 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61683449 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3213099 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 111780 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 3981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 347701 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 135656 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20567798 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 376508 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3292 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104390100 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.225611 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.323253 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40802320 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 63156516 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 413 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 335058 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 133595 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 290 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106194794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75144035 71.98% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3907124 3.74% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2485008 2.38% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8099840 7.76% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1578542 1.51% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1169165 1.12% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6151960 5.89% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1142182 1.09% 95.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4712244 4.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 76382369 71.93% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1616537 1.52% 87.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1210559 1.14% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6288171 5.92% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1186864 1.12% 95.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4785005 4.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104390100 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.254693 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.993536 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27682693 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57882458 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15650277 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1716894 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1457466 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1955529 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 151159 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 88694873 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 489106 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1457466 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28625802 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6604433 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45361321 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16416425 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5924344 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 84834346 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2307 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1574765 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 278233 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3285499 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 87641847 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 391276070 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 94803920 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5749 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 73988395 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13653452 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1589936 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1488982 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10049361 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15102779 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11808907 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2150791 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2768917 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 81595404 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1156818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78284353 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93210 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9952134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25073057 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106330 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104390100 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.749921 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.429238 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106194794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 59086639 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 2014125 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 153633 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90617334 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 499096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46364709 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1758 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1681489 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 204965 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5046479 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89687558 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 399294691 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96716693 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5355 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 75738735 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13948807 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1608168 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1506785 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10100252 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15391291 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11882778 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2188376 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79910900 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10129412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106194794 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72870740 69.81% 69.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10640655 10.19% 80.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8029126 7.69% 87.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6654786 6.37% 94.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2478739 2.37% 96.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1537519 1.47% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1459463 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 490817 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 228255 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74167078 69.84% 69.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10703730 10.08% 79.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1570037 1.48% 97.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1528184 1.44% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 489750 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 243435 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104390100 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106194794 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 100798 8.75% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 535574 46.51% 55.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 515204 44.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 521312 45.77% 55.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 507746 44.58% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 124 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52262651 66.76% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59116 0.08% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4115 0.01% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14698419 18.78% 85.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11259924 14.38% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 151 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53586361 67.06% 67.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59349 0.07% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4262 0.01% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14931901 18.69% 85.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78284353 # Type of FU issued -system.cpu1.iq.rate 0.731615 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1151580 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014710 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 262190696 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 92748647 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 75915598 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12900 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6883 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5649 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79428849 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6960 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 366149 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79910900 # Type of FU issued +system.cpu1.iq.rate 0.734775 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 267236211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94707265 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6289 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 81043378 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2166601 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2614 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 52391 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1139774 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2202451 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2360 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51509 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 191651 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 153600 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 192559 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1457466 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4280991 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2091777 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 82896193 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132170 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15102779 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11808907 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 583505 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 47325 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2032029 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 52391 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 250395 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 218336 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 468731 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 77684491 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14461832 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 541313 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4086013 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 663456 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84657415 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 129656 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15391291 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11882778 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585252 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 260306 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 483548 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79294807 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14687603 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 143971 # number of nop insts executed -system.cpu1.iew.exec_refs 25613639 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14454387 # Number of branches executed -system.cpu1.iew.exec_stores 11151807 # Number of stores executed -system.cpu1.iew.exec_rate 0.726009 # Inst execution rate -system.cpu1.iew.wb_sent 77065601 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 75921247 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39733715 # num instructions producing a value -system.cpu1.iew.wb_consumers 69689049 # num instructions consuming a value +system.cpu1.iew.exec_nop 123637 # number of nop insts executed +system.cpu1.iew.exec_refs 25906138 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14775343 # Number of branches executed +system.cpu1.iew.exec_stores 11218535 # Number of stores executed +system.cpu1.iew.exec_rate 0.729110 # Inst execution rate +system.cpu1.iew.wb_sent 78721985 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 40818570 # num instructions producing a value +system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.709530 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570157 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.713056 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570488 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11280608 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050488 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 395955 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 101852201 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703017 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.586598 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103612513 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.706116 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.593552 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73888394 72.54% 72.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12531229 12.30% 84.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6432271 6.32% 91.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2665520 2.62% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1405579 1.38% 95.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 922819 0.91% 96.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1826114 1.79% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 423793 0.42% 98.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1756482 1.72% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 75208985 72.59% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1429301 1.38% 95.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 940289 0.91% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1888025 1.82% 97.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 437231 0.42% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1807529 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 101852201 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 58981554 # Number of instructions committed -system.cpu1.commit.committedOps 71603833 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103612513 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60426665 # Number of instructions committed +system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23605311 # Number of memory references committed -system.cpu1.commit.loads 12936178 # Number of loads committed -system.cpu1.commit.membars 439363 # Number of memory barriers committed -system.cpu1.commit.branches 13694258 # Number of branches committed -system.cpu1.commit.fp_insts 5590 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 62751370 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2679190 # Number of function calls committed. +system.cpu1.commit.refs 23932641 # Number of memory references committed +system.cpu1.commit.loads 13188840 # Number of loads committed +system.cpu1.commit.membars 435550 # Number of memory barriers committed +system.cpu1.commit.branches 14000562 # Number of branches committed +system.cpu1.commit.fp_insts 5142 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 64124542 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2721670 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 47937101 66.95% 66.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57311 0.08% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4110 0.01% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12936178 18.07% 85.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10669133 14.90% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49168040 67.20% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57503 0.08% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4262 0.01% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13188840 18.03% 85.32% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10743801 14.68% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71603833 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1756482 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170496195 # The number of ROB reads -system.cpu1.rob.rob_writes 168311101 # The number of ROB writes -system.cpu1.timesIdled 389572 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2612002 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951648369 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 58897215 # Number of Instructions Simulated -system.cpu1.committedOps 71519494 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.816760 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816760 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550430 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550430 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84567520 # number of integer regfile reads -system.cpu1.int_regfile_writes 48323955 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16256 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13038 # number of floating regfile writes -system.cpu1.cc_regfile_reads 274360839 # number of cc regfile reads -system.cpu1.cc_regfile_writes 28850413 # number of cc regfile writes -system.cpu1.misc_regfile_reads 191580382 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795927 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30210 # Transaction distribution -system.iobus.trans_dist::ReadResp 30210 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.cpu1.rob.rob_reads 173729023 # The number of ROB reads +system.cpu1.rob.rob_writes 171875858 # The number of ROB writes +system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2560821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60356761 # Number of Instructions Simulated +system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.801880 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 86251315 # number of integer regfile reads +system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes +system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes +system.cpu1.cc_regfile_reads 279979129 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes +system.cpu1.misc_regfile_reads 195055078 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30198 # Transaction distribution +system.iobus.trans_dist::ReadResp 30198 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1866,11 +1824,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1891,11 +1849,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1935,46 +1893,46 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347059161 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198975032 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36834571 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36852019 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36411 # number of replacements -system.iocache.tags.tagsinuse 1.036460 # Cycle average of tags in use -system.iocache.tags.total_refs 28 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36427 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000769 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234008190000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036460 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064779 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064779 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 0.981278 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234149213000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.981278 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061330 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061330 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328229 # Number of tag accesses -system.iocache.tags.data_accesses 328229 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 27 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 27 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 29 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 29 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36197 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36197 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36195 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36195 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29657377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29657377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617288213 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617288213 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29657377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29657377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29657377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29657377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30962377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30962377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6648903636 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6648903636 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30962377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30962377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30962377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30962377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1985,306 +1943,306 @@ system.iocache.overall_accesses::realview.ide 249 system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999255 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.999255 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999199 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.999199 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119105.931727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119105.931727 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265692.963864 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265692.963864 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119105.931727 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119105.931727 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119105.931727 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119105.931727 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56457 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124346.895582 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124346.895582 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183696.743639 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183696.743639 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124346.895582 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124346.895582 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124346.895582 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124346.895582 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22802 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7214 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3472 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.826033 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.567396 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36162 # number of writebacks -system.iocache.writebacks::total 36162 # number of writebacks +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36197 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36197 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36195 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36195 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16708377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16708377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7734902355 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7734902355 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16708377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16708377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16708377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16708377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17850377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17850377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766725674 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766725674 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17850377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17850377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17850377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17850377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999255 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999255 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67101.915663 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67101.915663 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213689.044810 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213689.044810 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67101.915663 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67101.915663 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67101.915663 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67101.915663 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 71688.261044 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71688.261044 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131695.694820 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131695.694820 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 71688.261044 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 71688.261044 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 71688.261044 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 71688.261044 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104467 # number of replacements -system.l2c.tags.tagsinuse 65129.957708 # Cycle average of tags in use -system.l2c.tags.total_refs 3116952 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169707 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.366667 # Average number of references to valid blocks. +system.l2c.tags.replacements 104656 # number of replacements +system.l2c.tags.tagsinuse 65129.158587 # Cycle average of tags in use +system.l2c.tags.total_refs 3113742 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169901 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.326802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48713.108693 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.622899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5546.203044 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2803.513756 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 43.406508 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4962.784204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3012.318369 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.743303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000742 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48669.329761 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 43.033999 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4678.591805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2387.812073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.916630 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5867.753400 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3437.720673 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000657 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.084628 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000662 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.075726 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993804 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 90 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.071390 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.036435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000685 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.089535 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993792 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 70 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9019 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52534 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001373 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 29257096 # Number of tag accesses -system.l2c.tags.data_accesses 29257096 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 37572 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 9067 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 969052 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 275148 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36337 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7588 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 957278 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 266835 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2558877 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 703765 # number of Writeback hits -system.l2c.Writeback_hits::total 703765 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 106 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 34 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 52 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 78975 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 77026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156001 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 37572 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 9067 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 969052 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 354123 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7588 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 957278 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 343861 # number of demand (read+write) hits -system.l2c.demand_hits::total 2714878 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 37572 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.458837 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24786.571429 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 43250.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28889.666667 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71227.631279 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70738.996196 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70989.225333 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -2465,57 +2423,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68075 # Transaction distribution -system.membus.trans_dist::ReadResp 68074 # Transaction distribution -system.membus.trans_dist::WriteReq 27609 # Transaction distribution -system.membus.trans_dist::WriteResp 27609 # Transaction distribution -system.membus.trans_dist::Writeback 131718 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36196 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4659 # Transaction distribution -system.membus.trans_dist::ReadExReq 138608 # Transaction distribution -system.membus.trans_dist::ReadExResp 138608 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 68117 # Transaction distribution +system.membus.trans_dist::ReadResp 68116 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131657 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36194 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36194 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution +system.membus.trans_dist::ReadExReq 138750 # Transaction distribution +system.membus.trans_dist::ReadExResp 138750 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681489 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572879 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681693 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17335192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17499181 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4631872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22131053 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 522 # Total snoops (count) -system.membus.snoop_fanout::samples 347455 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17507929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22139545 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 523 # Total snoops (count) +system.membus.snoop_fanout::samples 347614 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 347455 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 347614 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 347455 # Request fanout histogram -system.membus.reqLayer0.occupancy 81552000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 347614 # Request fanout histogram +system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1759525499 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1732085345 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38509429 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1067095796 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1022748121 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2548,57 +2506,55 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2659236 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2659139 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27609 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27609 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 703765 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2841 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 78 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2918 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296507 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296507 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3896051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2534528 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 170141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6643823 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124664384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99866733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 296168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224893909 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 68735 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3666824 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009939 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099200 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2657013 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2656927 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2822 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 55 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2876 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536659 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6639094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962073 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224822789 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 70210 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3665576 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.009952 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099262 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3630378 99.01% 99.01% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36446 0.99% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3629096 99.00% 99.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36480 1.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3666824 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4674174231 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 688500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3665576 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2562503934 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8773601584 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3912223359 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26520841 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1353662761 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96916821 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96601513 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3042 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 15d0bc0bd..7478799f2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.904914 # Number of seconds simulated -sim_ticks 2904913754500 # Number of ticks simulated -final_tick 2904913754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903641 # Number of seconds simulated +sim_ticks 2903640922500 # Number of ticks simulated +final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 719084 # Simulator instruction rate (inst/s) -host_op_rate 866994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18567568294 # Simulator tick rate (ticks/s) -host_mem_usage 616260 # Number of bytes of host memory used -host_seconds 156.45 # Real time elapsed on the host -sim_insts 112501381 # Number of instructions simulated -sim_ops 135642071 # Number of ops (including micro ops) simulated +host_inst_rate 705602 # Simulator instruction rate (inst/s) +host_op_rate 850741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18218787173 # Simulator tick rate (ticks/s) +host_mem_usage 616688 # Number of bytes of host memory used +host_seconds 159.38 # Real time elapsed on the host +sim_insts 112456119 # Number of instructions simulated +sim_ops 135587804 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 553252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4270880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4758596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10219848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 553252 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1188836 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7620224 # Number of bytes written to this memory +system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7637748 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17098 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67251 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74354 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119066 # Number of write requests responded to by this memory +system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123447 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1470226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 218796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1638120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3518124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 218796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2623219 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2629251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2623219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1476256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 218796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1638122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6147376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168658 # Number of read requests accepted -system.physmem.writeReqs 159671 # Number of write requests accepted -system.physmem.readBursts 168658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159671 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10788160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 9869632 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10219848 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9956084 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5450 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4495 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9771 # Per bank write bursts -system.physmem.perBankRdBursts::1 9508 # Per bank write bursts -system.physmem.perBankRdBursts::2 10210 # Per bank write bursts -system.physmem.perBankRdBursts::3 9949 # Per bank write bursts -system.physmem.perBankRdBursts::4 18798 # Per bank write bursts -system.physmem.perBankRdBursts::5 10140 # Per bank write bursts -system.physmem.perBankRdBursts::6 10351 # Per bank write bursts -system.physmem.perBankRdBursts::7 10416 # Per bank write bursts -system.physmem.perBankRdBursts::8 9932 # Per bank write bursts -system.physmem.perBankRdBursts::9 10416 # Per bank write bursts -system.physmem.perBankRdBursts::10 9794 # Per bank write bursts -system.physmem.perBankRdBursts::11 9556 # Per bank write bursts -system.physmem.perBankRdBursts::12 10053 # Per bank write bursts -system.physmem.perBankRdBursts::13 9934 # Per bank write bursts -system.physmem.perBankRdBursts::14 9961 # Per bank write bursts -system.physmem.perBankRdBursts::15 9776 # Per bank write bursts -system.physmem.perBankWrBursts::0 9468 # Per bank write bursts -system.physmem.perBankWrBursts::1 9241 # Per bank write bursts -system.physmem.perBankWrBursts::2 10223 # Per bank write bursts -system.physmem.perBankWrBursts::3 9791 # Per bank write bursts -system.physmem.perBankWrBursts::4 9126 # Per bank write bursts -system.physmem.perBankWrBursts::5 9458 # Per bank write bursts -system.physmem.perBankWrBursts::6 9597 # Per bank write bursts -system.physmem.perBankWrBursts::7 9810 # Per bank write bursts -system.physmem.perBankWrBursts::8 9882 # Per bank write bursts -system.physmem.perBankWrBursts::9 10274 # Per bank write bursts -system.physmem.perBankWrBursts::10 9701 # Per bank write bursts -system.physmem.perBankWrBursts::11 9802 # Per bank write bursts -system.physmem.perBankWrBursts::12 9921 # Per bank write bursts -system.physmem.perBankWrBursts::13 9488 # Per bank write bursts -system.physmem.perBankWrBursts::14 9342 # Per bank write bursts -system.physmem.perBankWrBursts::15 9089 # Per bank write bursts +system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165551 # Number of read requests accepted +system.physmem.writeReqs 156772 # Number of write requests accepted +system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9899 # Per bank write bursts +system.physmem.perBankRdBursts::1 9526 # Per bank write bursts +system.physmem.perBankRdBursts::2 9759 # Per bank write bursts +system.physmem.perBankRdBursts::3 9793 # Per bank write bursts +system.physmem.perBankRdBursts::4 18999 # Per bank write bursts +system.physmem.perBankRdBursts::5 10033 # Per bank write bursts +system.physmem.perBankRdBursts::6 10462 # Per bank write bursts +system.physmem.perBankRdBursts::7 10803 # Per bank write bursts +system.physmem.perBankRdBursts::8 9925 # Per bank write bursts +system.physmem.perBankRdBursts::9 10243 # Per bank write bursts +system.physmem.perBankRdBursts::10 9858 # Per bank write bursts +system.physmem.perBankRdBursts::11 9250 # Per bank write bursts +system.physmem.perBankRdBursts::12 9247 # Per bank write bursts +system.physmem.perBankRdBursts::13 9475 # Per bank write bursts +system.physmem.perBankRdBursts::14 9028 # Per bank write bursts +system.physmem.perBankRdBursts::15 9149 # Per bank write bursts +system.physmem.perBankWrBursts::0 8258 # Per bank write bursts +system.physmem.perBankWrBursts::1 8244 # Per bank write bursts +system.physmem.perBankWrBursts::2 8572 # Per bank write bursts +system.physmem.perBankWrBursts::3 8149 # Per bank write bursts +system.physmem.perBankWrBursts::4 8563 # Per bank write bursts +system.physmem.perBankWrBursts::5 8536 # Per bank write bursts +system.physmem.perBankWrBursts::6 8718 # Per bank write bursts +system.physmem.perBankWrBursts::7 9117 # Per bank write bursts +system.physmem.perBankWrBursts::8 8657 # Per bank write bursts +system.physmem.perBankWrBursts::9 8771 # Per bank write bursts +system.physmem.perBankWrBursts::10 8610 # Per bank write bursts +system.physmem.perBankWrBursts::11 7990 # Per bank write bursts +system.physmem.perBankWrBursts::12 7949 # Per bank write bursts +system.physmem.perBankWrBursts::13 7964 # Per bank write bursts +system.physmem.perBankWrBursts::14 7531 # Per bank write bursts +system.physmem.perBankWrBursts::15 7537 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2904913375000 # Total gap between requests +system.physmem.numWrRetry 32 # Number of times write queue was full causing retry +system.physmem.totGap 2903640597500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159086 # Read request sizes (log2) +system.physmem.readPktSize::6 155979 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 155290 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167768 # What read queue length does an incoming req see +system.physmem.writePktSize::6 152391 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,196 +161,183 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.100889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.092266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.277091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21340 35.13% 35.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14718 24.23% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5632 9.27% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3268 5.38% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2341 3.85% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1599 2.63% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1029 1.69% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1125 1.85% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9688 15.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60740 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.064066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.583235 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6227 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6228 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.761240 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.356568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.463142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 15 0.24% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 11 0.18% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.13% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 13 0.21% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4938 79.29% 80.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 76 1.22% 81.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 62 1.00% 82.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 242 3.89% 86.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.23% 88.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.80% 89.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.50% 89.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 38 0.61% 90.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 131 2.10% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.37% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.18% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 18 0.29% 93.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.53% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 12 0.19% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.14% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.47% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 74 1.19% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 10 0.16% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.10% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 12 0.19% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 105 1.69% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 8 0.13% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.08% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 14 0.22% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.08% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.16% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.58% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.08% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.05% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6228 # Writes before turning the bus around for reads -system.physmem.totQLat 1469432250 # Total ticks spent queuing -system.physmem.totMemAccLat 4630026000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 842825000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8717.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads +system.physmem.totQLat 1437662314 # Total ticks spent queuing +system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27467.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.43 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.21 # Average write queue length when enqueuing -system.physmem.readRowHits 138952 # Number of row buffer hits during reads -system.physmem.writeRowHits 123085 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes -system.physmem.avgGap 8847568.67 # Average gap between requests -system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232530480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126876750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 695315400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 497106720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86967425385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666658766000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944912602655 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.525949 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772474399000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing +system.physmem.readRowHits 136363 # Number of row buffer hits during reads +system.physmem.writeRowHits 104375 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes +system.physmem.avgGap 9008480.93 # Average gap between requests +system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.506799 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states +system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35434263500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 226663920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123675750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 619483800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 502193520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86205812760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667326855500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1944739267170 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466276 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2773597933750 # Time in different power states -system.physmem_1.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.365444 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states +system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34314407250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -400,60 +387,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7245 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7245 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2256 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4989 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7245 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7245 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7245 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6163 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11073.588350 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8976.658748 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6262.578720 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-2047 6 0.10% 0.10% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::2048-4095 1618 26.25% 26.35% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::4096-6143 2 0.03% 26.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::10240-12287 3154 51.18% 77.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::12288-14335 39 0.63% 78.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::14336-16383 18 0.29% 78.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::20480-22527 1281 20.79% 99.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::22528-24575 45 0.73% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6163 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 809116500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 809116500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 809116500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3931 63.78% 63.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2232 36.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6163 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6899 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7245 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6163 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6163 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 13408 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12308192 # DTB read hits -system.cpu0.dtb.read_misses 6208 # DTB read misses -system.cpu0.dtb.write_hits 9797532 # DTB write hits -system.cpu0.dtb.write_misses 1037 # DTB write misses -system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12462635 # DTB read hits +system.cpu0.dtb.read_misses 5988 # DTB read misses +system.cpu0.dtb.write_hits 9832923 # DTB write hits +system.cpu0.dtb.write_misses 911 # DTB write misses +system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4666 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12314400 # DTB read accesses -system.cpu0.dtb.write_accesses 9798569 # DTB write accesses +system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12468623 # DTB read accesses +system.cpu0.dtb.write_accesses 9833834 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22105724 # DTB hits -system.cpu0.dtb.misses 7245 # DTB misses -system.cpu0.dtb.accesses 22112969 # DTB accesses +system.cpu0.dtb.hits 22295558 # DTB hits +system.cpu0.dtb.misses 6899 # DTB misses +system.cpu0.dtb.accesses 22302457 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,372 +466,364 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3600 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3600 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2760 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3600 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2772 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11755.230880 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9457.284814 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6774.641568 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 701 25.29% 25.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1365 49.24% 74.53% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 705 25.43% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2772 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1932 69.70% 69.70% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 840 30.30% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2772 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3577 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3600 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2772 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2772 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6372 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58198432 # ITB inst hits -system.cpu0.itb.inst_misses 3600 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58414032 # ITB inst hits +system.cpu0.itb.inst_misses 3577 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2765 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58202032 # ITB inst accesses -system.cpu0.itb.hits 58198432 # DTB hits -system.cpu0.itb.misses 3600 # DTB misses -system.cpu0.itb.accesses 58202032 # DTB accesses -system.cpu0.numCycles 2905779233 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses +system.cpu0.itb.hits 58414032 # DTB hits +system.cpu0.itb.misses 3577 # DTB misses +system.cpu0.itb.accesses 58417609 # DTB accesses +system.cpu0.numCycles 2904051621 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56657023 # Number of instructions committed -system.cpu0.committedOps 68159505 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60230099 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 6043 # Number of float alu accesses -system.cpu0.num_func_calls 4917301 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7681441 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60230099 # number of integer instructions -system.cpu0.num_fp_insts 6043 # number of float instructions -system.cpu0.num_int_register_reads 109460291 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41577079 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4484 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1562 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 246097869 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26230649 # number of times the CC registers were written -system.cpu0.num_mem_refs 22747427 # number of memory refs -system.cpu0.num_load_insts 12471045 # Number of load instructions -system.cpu0.num_store_insts 10276382 # Number of store instructions -system.cpu0.num_idle_cycles 2686979283.194706 # Number of idle cycles -system.cpu0.num_busy_cycles 218799949.805294 # Number of busy cycles -system.cpu0.not_idle_fraction 0.075298 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.924702 # Percentage of idle cycles -system.cpu0.Branches 13013493 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46896636 67.27% 67.28% # Class of executed instruction -system.cpu0.op_class::IntMult 58754 0.08% 67.36% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4258 0.01% 67.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::MemRead 12471045 17.89% 85.26% # Class of executed instruction -system.cpu0.op_class::MemWrite 10276382 14.74% 100.00% # Class of executed instruction +system.cpu0.committedInsts 56844590 # Number of instructions committed +system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses +system.cpu0.num_func_calls 5072041 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60556147 # number of integer instructions +system.cpu0.num_fp_insts 5891 # number of float instructions +system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written +system.cpu0.num_mem_refs 22952183 # number of memory refs +system.cpu0.num_load_insts 12628752 # Number of load instructions +system.cpu0.num_store_insts 10323431 # Number of store instructions +system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles +system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles +system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles +system.cpu0.Branches 13135796 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction +system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69709278 # Class of executed instruction +system.cpu0.op_class::total 70074060 # Class of executed instruction system.cpu0.kern.inst.arm 0 # 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Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 821716 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.827808 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43234238 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 822228 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.581812 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177183348 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177183348 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11600363 # 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number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9579302 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19129684 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 255351 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 255736 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511087 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238694 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 466189 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235789 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 224613 # 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number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10346474500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016919 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017238 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014956 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015608 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228045 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228132 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228088 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018844 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.017634 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016597 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016428 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018653 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019228 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12630.027849 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12787.506723 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12709.430749 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36297.622580 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38064.144366 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37189.729623 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12158.138140 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12501.070198 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12337.131459 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11766.338678 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11804.756015 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11786.289852 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.244477 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23573.746883 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23146.421634 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.970710 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21945.089956 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21601.929439 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # 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average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -859,79 +834,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699876 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.774945 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113899876 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1700388 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.984639 # 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Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117300664 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117300664 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57350245 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56549631 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113899876 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57350245 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56549631 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113899876 # 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number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58198432 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57401838 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115600270 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58198432 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57401838 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115600270 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014574 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014846 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014709 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014574 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014846 # 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number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -940,46 +915,46 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 848187 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 852207 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1700394 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 848187 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 852207 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1700394 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 848187 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 852207 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1700394 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9867956501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10033302501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19901259002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9867956501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10033302501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19901259002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9867956501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10033302501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19901259002 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014709 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014709 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014709 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11703.910389 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -1014,61 +989,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6287 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6287 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1877 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4409 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walks 6646 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6286 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6286 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6286 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5205 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10664.029395 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8432.528945 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7016.441417 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 4168 80.08% 80.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1031 19.81% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-81919 3 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5205 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2238481496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.553158 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.497166 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000247500 44.68% 44.68% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1238233996 55.32% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2238481496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3350 64.37% 64.37% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1854 35.63% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5204 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5204 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5204 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11491 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12222323 # DTB read hits -system.cpu1.dtb.read_misses 5479 # DTB read misses -system.cpu1.dtb.write_hits 9816234 # DTB write hits -system.cpu1.dtb.write_misses 808 # DTB write misses -system.cpu1.dtb.flush_tlb 2935 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12057381 # DTB read hits +system.cpu1.dtb.read_misses 5757 # DTB read misses +system.cpu1.dtb.write_hits 9774636 # DTB write hits +system.cpu1.dtb.write_misses 889 # DTB write misses +system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4100 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 935 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12227802 # DTB read accesses -system.cpu1.dtb.write_accesses 9817042 # DTB write accesses +system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12063138 # DTB read accesses +system.cpu1.dtb.write_accesses 9775525 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22038557 # DTB hits -system.cpu1.dtb.misses 6287 # DTB misses -system.cpu1.dtb.accesses 22044844 # DTB accesses +system.cpu1.dtb.hits 21832017 # DTB hits +system.cpu1.dtb.misses 6646 # DTB misses +system.cpu1.dtb.accesses 21838663 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1098,127 +1072,125 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3158 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3158 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 699 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2459 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3158 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3158 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3158 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2331 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10972.758473 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8658.635701 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6654.132285 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 701 30.07% 30.07% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 5 0.21% 30.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 1063 45.60% 75.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 47 2.02% 77.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 1 0.04% 77.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 442 18.96% 96.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 72 3.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2331 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000205500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000205500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000205500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1632 70.01% 70.01% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 699 29.99% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2331 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3230 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3158 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3158 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2331 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2331 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5489 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 57401838 # ITB inst hits -system.cpu1.itb.inst_misses 3158 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 57139903 # ITB inst hits +system.cpu1.itb.inst_misses 3230 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2935 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2358 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57404996 # ITB inst accesses -system.cpu1.itb.hits 57401838 # DTB hits -system.cpu1.itb.misses 3158 # DTB misses -system.cpu1.itb.accesses 57404996 # DTB accesses -system.cpu1.numCycles 2904048276 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses +system.cpu1.itb.hits 57139903 # DTB hits +system.cpu1.itb.misses 3230 # DTB misses +system.cpu1.itb.accesses 57143133 # DTB accesses +system.cpu1.numCycles 2903230224 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55844358 # Number of instructions committed -system.cpu1.committedOps 67482566 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59712832 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5183 # Number of float alu accesses -system.cpu1.num_func_calls 4980648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7553958 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59712832 # number of integer instructions -system.cpu1.num_fp_insts 5183 # number of float instructions -system.cpu1.num_int_register_reads 108693830 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41104260 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4030 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1154 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 243842957 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25682716 # number of times the CC registers were written -system.cpu1.num_mem_refs 22677996 # number of memory refs -system.cpu1.num_load_insts 12382220 # Number of load instructions -system.cpu1.num_store_insts 10295776 # Number of store instructions -system.cpu1.num_idle_cycles 2693878470.584054 # Number of idle cycles -system.cpu1.num_busy_cycles 210169805.415946 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072371 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927629 # Percentage of idle cycles -system.cpu1.Branches 12913817 # Number of branches fetched -system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46316521 67.07% 67.07% # Class of executed instruction -system.cpu1.op_class::IntMult 55928 0.08% 67.15% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4215 0.01% 67.16% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::MemRead 12382220 17.93% 85.09% # Class of executed instruction -system.cpu1.op_class::MemWrite 10295776 14.91% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55611529 # Number of instructions committed +system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses +system.cpu1.num_func_calls 4819801 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59336824 # number of integer instructions +system.cpu1.num_fp_insts 5270 # number of float instructions +system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read +system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written +system.cpu1.num_mem_refs 22456627 # number of memory refs +system.cpu1.num_load_insts 12214155 # Number of load instructions +system.cpu1.num_store_insts 10242472 # Number of store instructions +system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles +system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles +system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles +system.cpu1.Branches 12781357 # Number of branches fetched +system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction +system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction +system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69054794 # Class of executed instruction +system.cpu1.op_class::total 68634629 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1239,11 +1211,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1264,11 +1236,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1308,23 +1280,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347068533 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.084285 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309430209000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084285 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067768 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067768 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1338,14 +1310,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9589202651 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9589202651 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1362,19 +1334,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264719.596152 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264719.596152 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55434 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.750839 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1388,14 +1360,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7705544661 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7705544661 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16965377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16965377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4749438915 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4749438915 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16965377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16965377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16965377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1404,255 +1376,250 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # 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Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.877670 # Average number of references to valid blocks. +system.l2c.tags.replacements 86345 # number of replacements +system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use +system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50576.969864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943928 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3885.587272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2054.187516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768426 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5757.064003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2648.035097 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.771743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.031344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.087846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.040406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990716 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2140.248339 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.767444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # 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Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26304357 # Number of tag accesses -system.l2c.tags.data_accesses 26304357 # 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number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 80755 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 165040 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 840087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 337994 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2755 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 842268 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 342247 # number of demand (read+write) hits -system.l2c.demand_hits::total 2380496 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6457 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3455 # number of overall hits -system.l2c.overall_hits::cpu0.inst 840087 # number of overall hits -system.l2c.overall_hits::cpu0.data 337994 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5233 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2755 # number of overall hits -system.l2c.overall_hits::cpu1.inst 842268 # number of overall hits -system.l2c.overall_hits::cpu1.data 342247 # number of overall hits -system.l2c.overall_hits::total 2380496 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8081 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5539 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9933 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6602 # number of ReadReq misses -system.l2c.ReadReq_misses::total 30164 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1370 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2721 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses +system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26318997 # Number of tag accesses +system.l2c.tags.data_accesses 26318997 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 848098 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 260151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 835810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 254237 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2217790 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 687030 # number of Writeback hits +system.l2c.Writeback_hits::total 687030 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 87471 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 80339 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167810 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6505 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 848098 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 347622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 835810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 334576 # number of demand (read+write) hits +system.l2c.demand_hits::total 2385600 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6505 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3514 # number of overall hits +system.l2c.overall_hits::cpu0.inst 848098 # number of overall hits +system.l2c.overall_hits::cpu0.data 347622 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits +system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits +system.l2c.overall_hits::cpu1.data 334576 # number of overall hits +system.l2c.overall_hits::total 2385600 # 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number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 546237750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2603822250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2793047000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5943107000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2054472000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2099890500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4154362500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 546237750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4658294250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4892937500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10097469500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.022455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013388 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988183 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990566 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989385 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424723 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459782 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.442429 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000155 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000289 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.167010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001336 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011656 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.180404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063393 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000155 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000289 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.167010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001336 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011656 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.180404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063393 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63977.297346 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62579.786277 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61601.437110 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10039.490007 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.343066 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.024256 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 60500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 60500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56615.989603 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55923.751131 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56252.680432 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.383799 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477609 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.432582 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062127 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062127 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1818,57 +1781,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70570 # Transaction distribution -system.membus.trans_dist::ReadResp 70570 # Transaction distribution -system.membus.trans_dist::WriteReq 27613 # Transaction distribution -system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 119066 # Transaction distribution +system.membus.trans_dist::ReadReq 70492 # Transaction distribution +system.membus.trans_dist::ReadResp 70492 # Transaction distribution +system.membus.trans_dist::WriteReq 27594 # Transaction distribution +system.membus.trans_dist::WriteResp 27594 # Transaction distribution +system.membus.trans_dist::Writeback 116167 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4495 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4497 # Transaction distribution -system.membus.trans_dist::ReadExReq 129184 # Transaction distribution -system.membus.trans_dist::ReadExResp 129184 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution +system.membus.trans_dist::ReadExReq 126147 # Transaction distribution +system.membus.trans_dist::ReadExResp 126147 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438193 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545857 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 654744 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15540476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15703901 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20339357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 319369 # Request fanout histogram +system.membus.snoop_fanout::samples 313389 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 319369 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 319369 # Request fanout histogram -system.membus.reqLayer0.occupancy 87174000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 313389 # Request fanout histogram +system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1737000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1663053000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1641418005 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1901,54 +1864,52 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303048 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303033 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686778 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2744 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2746 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295998 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295998 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418807 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2456695 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5928317 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108859704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96844773 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205776113 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53699 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3284622 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011100 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104768 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 52269 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3248164 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3284622 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4418893499 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7666187498 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782041495 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11977000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22953702 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f7aa432dd..f6bd584fc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.355615 # Number of seconds simulated -sim_ticks 47355615197500 # Number of ticks simulated -final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.357291 # Number of seconds simulated +sim_ticks 47357290872500 # Number of ticks simulated +final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119180 # Simulator instruction rate (inst/s) -host_op_rate 140167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6305360463 # Simulator tick rate (ticks/s) -host_mem_usage 747912 # Number of bytes of host memory used -host_seconds 7510.37 # Real time elapsed on the host -sim_insts 895084962 # Number of instructions simulated -sim_ops 1052703090 # Number of ops (including micro ops) simulated +host_inst_rate 179609 # Simulator instruction rate (inst/s) +host_op_rate 211253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9509351214 # Simulator tick rate (ticks/s) +host_mem_usage 764316 # Number of bytes of host memory used +host_seconds 4980.08 # Real time elapsed on the host +sim_insts 894465242 # Number of instructions simulated +sim_ops 1052057457 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory -system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory +system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 135884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 218607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 334033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 51517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 118125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 204412 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1077470 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1235035 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1237638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 183638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 295403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 451422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 159618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 276248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1456075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 183638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1669062 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1055887 # Number of read requests accepted -system.physmem.writeReqs 1888199 # Number of write requests accepted -system.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58784 # Per bank write bursts -system.physmem.perBankRdBursts::1 68771 # Per bank write bursts -system.physmem.perBankRdBursts::2 59130 # Per bank write bursts -system.physmem.perBankRdBursts::3 67531 # Per bank write bursts -system.physmem.perBankRdBursts::4 66855 # Per bank write bursts -system.physmem.perBankRdBursts::5 75133 # Per bank write bursts -system.physmem.perBankRdBursts::6 65903 # Per bank write bursts -system.physmem.perBankRdBursts::7 67407 # Per bank write bursts -system.physmem.perBankRdBursts::8 54196 # Per bank write bursts -system.physmem.perBankRdBursts::9 110706 # Per bank write bursts -system.physmem.perBankRdBursts::10 54461 # Per bank write bursts -system.physmem.perBankRdBursts::11 64104 # Per bank write bursts -system.physmem.perBankRdBursts::12 57097 # Per bank write bursts -system.physmem.perBankRdBursts::13 66166 # Per bank write bursts -system.physmem.perBankRdBursts::14 60751 # Per bank write bursts -system.physmem.perBankRdBursts::15 58597 # Per bank write bursts -system.physmem.perBankWrBursts::0 116651 # Per bank write bursts -system.physmem.perBankWrBursts::1 125865 # Per bank write bursts -system.physmem.perBankWrBursts::2 118664 # Per bank write bursts -system.physmem.perBankWrBursts::3 124773 # Per bank write bursts -system.physmem.perBankWrBursts::4 121001 # Per bank write bursts -system.physmem.perBankWrBursts::5 125597 # Per bank write bursts -system.physmem.perBankWrBursts::6 113710 # Per bank write bursts -system.physmem.perBankWrBursts::7 116980 # Per bank write bursts -system.physmem.perBankWrBursts::8 110183 # Per bank write bursts -system.physmem.perBankWrBursts::9 114411 # Per bank write bursts -system.physmem.perBankWrBursts::10 109841 # Per bank write bursts -system.physmem.perBankWrBursts::11 116847 # Per bank write bursts -system.physmem.perBankWrBursts::12 116927 # Per bank write bursts -system.physmem.perBankWrBursts::13 118874 # Per bank write bursts -system.physmem.perBankWrBursts::14 112844 # Per bank write bursts -system.physmem.perBankWrBursts::15 118210 # Per bank write bursts +system.physmem.bw_write::total 1669501 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1669062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 183638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 295842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 451422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 159618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 276248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3125576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1077470 # Number of read requests accepted +system.physmem.writeReqs 1907210 # Number of write requests accepted +system.physmem.readBursts 1077470 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1907210 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68937984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue +system.physmem.bytesWritten 118940800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68955768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 121915664 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 48739 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 118611 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58565 # Per bank write bursts +system.physmem.perBankRdBursts::1 71236 # Per bank write bursts +system.physmem.perBankRdBursts::2 60619 # Per bank write bursts +system.physmem.perBankRdBursts::3 68763 # Per bank write bursts +system.physmem.perBankRdBursts::4 63623 # Per bank write bursts +system.physmem.perBankRdBursts::5 74242 # Per bank write bursts +system.physmem.perBankRdBursts::6 69161 # Per bank write bursts +system.physmem.perBankRdBursts::7 67695 # Per bank write bursts +system.physmem.perBankRdBursts::8 61029 # Per bank write bursts +system.physmem.perBankRdBursts::9 112215 # Per bank write bursts +system.physmem.perBankRdBursts::10 55292 # Per bank write bursts +system.physmem.perBankRdBursts::11 71140 # Per bank write bursts +system.physmem.perBankRdBursts::12 63760 # Per bank write bursts +system.physmem.perBankRdBursts::13 63951 # Per bank write bursts +system.physmem.perBankRdBursts::14 57537 # Per bank write bursts +system.physmem.perBankRdBursts::15 58328 # Per bank write bursts +system.physmem.perBankWrBursts::0 113661 # Per bank write bursts +system.physmem.perBankWrBursts::1 123588 # Per bank write bursts +system.physmem.perBankWrBursts::2 119813 # Per bank write bursts +system.physmem.perBankWrBursts::3 126847 # Per bank write bursts +system.physmem.perBankWrBursts::4 114977 # Per bank write bursts +system.physmem.perBankWrBursts::5 123724 # Per bank write bursts +system.physmem.perBankWrBursts::6 117451 # Per bank write bursts +system.physmem.perBankWrBursts::7 117840 # Per bank write bursts +system.physmem.perBankWrBursts::8 112656 # Per bank write bursts +system.physmem.perBankWrBursts::9 114020 # Per bank write bursts +system.physmem.perBankWrBursts::10 109420 # Per bank write bursts +system.physmem.perBankWrBursts::11 118853 # Per bank write bursts +system.physmem.perBankWrBursts::12 108855 # Per bank write bursts +system.physmem.perBankWrBursts::13 111956 # Per bank write bursts +system.physmem.perBankWrBursts::14 111151 # Per bank write bursts +system.physmem.perBankWrBursts::15 113638 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47355613259000 # Total gap between requests +system.physmem.numWrRetry 260 # Number of times write queue was full causing retry +system.physmem.totGap 47357288950000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1055845 # Read request sizes (log2) +system.physmem.readPktSize::6 1077428 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1885596 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1904607 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 705573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 42943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 38392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,179 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 44576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 64765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 92305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 111564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 99926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 96399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 113990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 101913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 97920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 781 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads -system.physmem.totQLat 39480003252 # Total ticks spent queuing -system.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads +system.physmem.totQLat 41096385470 # Total ticks spent queuing +system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 797783 # Number of row buffer hits during reads -system.physmem.writeRowHits 1093063 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes -system.physmem.avgGap 16084996.59 # Average gap between requests -system.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764772 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing +system.physmem.readRowHits 809420 # Number of row buffer hits during reads +system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes +system.physmem.avgGap 15866789.39 # Average gap between requests +system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.775859 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.721243 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.740522 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -394,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131272413 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits +system.cpu0.branchPred.lookups 151571686 # Number of BP lookups +system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -433,67 +423,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 271399 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 310912 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83830376 # DTB read hits -system.cpu0.dtb.read_misses 224800 # DTB read misses -system.cpu0.dtb.write_hits 74836136 # DTB write hits -system.cpu0.dtb.write_misses 46599 # DTB write misses +system.cpu0.dtb.read_hits 98035121 # DTB read hits +system.cpu0.dtb.read_misses 261233 # DTB read misses +system.cpu0.dtb.write_hits 86222704 # DTB write hits +system.cpu0.dtb.write_misses 49679 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84055176 # DTB read accesses -system.cpu0.dtb.write_accesses 74882735 # DTB write accesses +system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98296354 # DTB read accesses +system.cpu0.dtb.write_accesses 86272383 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 158666512 # DTB hits -system.cpu0.dtb.misses 271399 # DTB misses -system.cpu0.dtb.accesses 158937911 # DTB accesses +system.cpu0.dtb.hits 184257825 # DTB hits +system.cpu0.dtb.misses 310912 # DTB misses +system.cpu0.dtb.accesses 184568737 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,185 +507,185 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 59516 # Table walker walks requested -system.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 67664 # Table walker walks requested +system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 234493726 # ITB inst hits -system.cpu0.itb.inst_misses 59516 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 272362835 # ITB inst hits +system.cpu0.itb.inst_misses 67664 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 234553242 # ITB inst accesses -system.cpu0.itb.hits 234493726 # DTB hits -system.cpu0.itb.misses 59516 # DTB misses -system.cpu0.itb.accesses 234553242 # DTB accesses -system.cpu0.numCycles 936626399 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses +system.cpu0.itb.hits 272362835 # DTB hits +system.cpu0.itb.misses 67664 # DTB misses +system.cpu0.itb.accesses 272430499 # DTB accesses +system.cpu0.numCycles 1079786982 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 433367687 # Number of instructions committed -system.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.161274 # CPI: cycles per instruction -system.cpu0.ipc 0.462690 # IPC: instructions per cycle +system.cpu0.committedInsts 504924574 # Number of instructions committed +system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.138511 # CPI: cycles per instruction +system.cpu0.ipc 0.467615 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed -system.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5387052 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits -system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses -system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed +system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 6269899 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.388707 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 371740852 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 371740852 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 90280740 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90280740 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80064017 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80064017 # number of WriteReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 281235 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 281235 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1931472 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1931472 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1872190 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1872190 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 170344757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 170344757 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 170344757 # number of overall hits +system.cpu0.dcache.overall_hits::total 170344757 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 4509015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 4509015 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2541213 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2541213 # number of WriteReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 864871 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 864871 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 140737 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 140737 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198480 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 198480 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7050228 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7050228 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7050228 # number of overall misses +system.cpu0.dcache.overall_misses::total 7050228 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 66986292890 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 66986292890 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47882988891 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 47882988891 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 35264024894 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 35264024894 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2028925085 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2028925085 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4179395855 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4179395855 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2760500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 114869281781 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 114869281781 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 114869281781 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 114869281781 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94789755 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94789755 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82605230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82605230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1146106 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1146106 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072209 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2072209 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2070670 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2070670 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 177394985 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 177394985 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 177394985 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 177394985 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047569 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.047569 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.754617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.754617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.067916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.067916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095853 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095853 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.039743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.081182 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.081182 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18842.571989 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18842.571989 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40773.739545 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40773.739545 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14416.429830 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14416.429830 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21057.012571 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21057.012571 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16292.988224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16292.988224 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,88 +694,88 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks -system.cpu0.dcache.writebacks::total 3733142 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4811395 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4374601 # number of writebacks +system.cpu0.dcache.writebacks::total 4374601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429861 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 429861 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1046667 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1046667 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 81 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 81 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 33 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 55 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 55 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1476528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1476528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1476528 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1476528 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 4079154 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 4079154 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1494546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1494546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 864790 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 864790 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140704 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140704 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 198425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5573700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5573700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5573700 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5573700 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53839740568 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53839740568 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26185332493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26185332493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 33958968357 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 33958968357 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1816137650 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1816137650 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3868892109 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3868892109 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 80025073061 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 80025073061 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80025073061 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 80025073061 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5766564749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5473208250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5473208250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11239772999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11239772999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031420 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031420 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -799,58 +783,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # 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Cycle average of tags in use +system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits -system.cpu0.icache.overall_hits::total 224826074 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses -system.cpu0.icache.overall_misses::total 9464200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 554607398 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 261841431 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 261841431 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 261841431 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 261841431 # number of overall hits +system.cpu0.icache.overall_hits::total 261841431 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10308179 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10308179 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10308179 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10308179 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 10308179 # number of overall misses +system.cpu0.icache.overall_misses::total 10308179 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 103403812050 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 103403812050 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 103403812050 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 103403812050 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 272149610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 272149610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 272149610 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 272149610 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 272149610 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 272149610 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037877 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037877 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,383 +842,384 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # 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average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10308179 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10308179 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 10308179 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10308179 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 10308179 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10308179 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93061406416 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 93061406416 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93061406416 # 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average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 11128158 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 11136239 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7035 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 12908052 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 12916183 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7100 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # 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Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13544 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 133 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 367 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1060 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 959 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 25 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1002 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2423 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4868 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5129 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.153748 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.826660 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 319708402 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8698965 # 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number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 764525 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 195483 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 179937 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1126447 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9464199 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4721418 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 14807252 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 475185 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146450 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9464199 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4721418 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 14807252 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056251 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 410 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1208 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 648 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3981 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4660 # 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mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.725161 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.725161 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.628747 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.628747 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793519 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.793519 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231718 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210133 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210133 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.117225 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25077.708478 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13624.298374 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 183500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36521.098204 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186936 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29763.331275 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26938.772911 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44997.202450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43674.769924 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43674.769924 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20418.408310 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20418.408310 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15115.924084 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15115.924084 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 389899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 389899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41290.896998 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41290.896998 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28945.720413 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1245,69 +1229,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 141025153 # Number of BP lookups -system.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits +system.cpu1.branchPred.lookups 120391711 # Number of BP lookups +system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1337,61 +1318,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 298651 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 259478 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90905034 # DTB read hits -system.cpu1.dtb.read_misses 248418 # DTB read misses -system.cpu1.dtb.write_hits 78767149 # DTB write hits -system.cpu1.dtb.write_misses 50233 # DTB write misses +system.cpu1.dtb.read_hits 76628852 # DTB read hits +system.cpu1.dtb.read_misses 212787 # DTB read misses +system.cpu1.dtb.write_hits 67332330 # DTB write hits +system.cpu1.dtb.write_misses 46691 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91153452 # DTB read accesses -system.cpu1.dtb.write_accesses 78817382 # DTB write accesses +system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 76841639 # DTB read accesses +system.cpu1.dtb.write_accesses 67379021 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 169672183 # DTB hits -system.cpu1.dtb.misses 298651 # DTB misses -system.cpu1.dtb.accesses 169970834 # DTB accesses +system.cpu1.dtb.hits 143961182 # DTB hits +system.cpu1.dtb.misses 259478 # DTB misses +system.cpu1.dtb.accesses 144220660 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1421,179 +1408,178 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 67610 # Table walker walks requested -system.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 59975 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 252933263 # ITB inst hits -system.cpu1.itb.inst_misses 67610 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 214508261 # ITB inst hits +system.cpu1.itb.inst_misses 59975 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 253000873 # ITB inst accesses -system.cpu1.itb.hits 252933263 # DTB hits -system.cpu1.itb.misses 67610 # DTB misses -system.cpu1.itb.accesses 253000873 # DTB accesses -system.cpu1.numCycles 943783669 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses +system.cpu1.itb.hits 214508261 # DTB hits +system.cpu1.itb.misses 59975 # DTB misses +system.cpu1.itb.accesses 214568236 # DTB accesses +system.cpu1.numCycles 819770260 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 461717275 # Number of instructions committed -system.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.044073 # CPI: cycles per instruction -system.cpu1.ipc 0.489219 # IPC: instructions per cycle +system.cpu1.committedInsts 389540668 # Number of instructions committed +system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.104454 # CPI: cycles per instruction +system.cpu1.ipc 0.475183 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed -system.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5624476 # number of replacements -system.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1854336 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 156964388 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 156964388 # number of overall hits -system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 4311289 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 141331 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193852 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 6678218 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6678218 # number of overall misses -system.cpu1.dcache.overall_misses::total 6678218 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 98815778897 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040810 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040810 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed +system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4705434 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 70292866 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 62721831 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 62721831 # number of WriteReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 37138 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 37138 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1710890 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1710890 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1626994 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1626994 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 133014697 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 133014697 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 133014697 # number of overall hits +system.cpu1.dcache.overall_hits::total 133014697 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3624776 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3624776 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2086736 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2086736 # number of WriteReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 382666 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 382666 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 105529 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 105529 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 188259 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 188259 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5711512 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5711512 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5711512 # number of overall misses +system.cpu1.dcache.overall_misses::total 5711512 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50593739173 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 50593739173 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36769582633 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 36769582633 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 10366896775 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 10366896775 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1534806603 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 1534806603 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3974138991 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 419804 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1602,88 +1588,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks -system.cpu1.dcache.writebacks::total 3711348 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1368730 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3913497 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1395991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 476533 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141284 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193784 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 5309488 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5309488 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46779736993 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20386885918 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10653380764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1693632498 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3584420895 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67166622911 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 67166622911 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 548139751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 613571252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1161711003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks +system.cpu1.dcache.writebacks::total 3043303 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 76 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1225748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 382590 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 382590 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105497 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105497 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 188206 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 188206 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4524503 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4524503 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4524503 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4524503 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40628902084 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40628902084 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20156955784 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1691,58 +1677,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9215030 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8513181 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.039853 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 205775695 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8513693 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.169969 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8369241421000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.039853 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990312 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990312 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 243489253 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 243489253 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 243489253 # number of overall hits -system.cpu1.icache.overall_hits::total 243489253 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9215542 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9215542 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9215542 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9215542 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9215542 # number of overall misses -system.cpu1.icache.overall_misses::total 9215542 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91468274167 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 91468274167 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 91468274167 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 91468274167 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 91468274167 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 91468274167 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 252704795 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 252704795 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 252704795 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 252704795 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 252704795 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 252704795 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036468 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.036468 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036468 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.036468 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036468 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.036468 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9925.436200 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9925.436200 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9925.436200 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9925.436200 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 437092471 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 437092471 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 205775695 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 205775695 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 205775695 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 205775695 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 205775695 # number of overall hits +system.cpu1.icache.overall_hits::total 205775695 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8513694 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8513694 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8513694 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8513694 # 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number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 214289389 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 214289389 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 214289389 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039730 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.039730 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039730 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.039730 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039730 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.039730 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9885.171123 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9885.171123 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9885.171123 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9885.171123 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1751,242 +1737,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # 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number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8513694 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513694 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8513694 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75624287377 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 75624287377 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75624287377 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 75624287377 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75624287377 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 75624287377 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8552000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8552000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8552000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8552000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039730 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.039730 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.039730 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8882.664491 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 10121407 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 10125724 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 3757 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2569302 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # 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Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 321109712 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3278512 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77280 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 939119 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8400098 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 4217631 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8400098 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 4217631 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 815444 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 775983 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses +system.cpu1.l2cache.prefetcher.pfSpanPage 1112844 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2221085 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13329.151476 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 13836589 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2237248 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.184647 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10494820402000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5280.158493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.775550 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 82.006725 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3962.886937 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2390.470426 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.853345 # 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number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 16244239643 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 32869715189 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33861408353 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 33861408353 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6819895822 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 6819895822 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2772663634 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2772663634 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2270029922 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2270029922 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2361497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2361497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7617845684 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7617845684 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286315515 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15972439241 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 23862085327 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 40487560873 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286315515 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15972439241 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 23862085327 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33861408353 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 74348969226 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7789000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 632822249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 640611249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 765196000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 765196000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7789000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1398018249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1405807249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.202853 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.113649 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.573995 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.639408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784248 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.587342 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.587342 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.665364 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.665364 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827885 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.200339 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.236903 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.236903 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.122848 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2146,66 +2131,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40424 # Transaction distribution -system.iobus.trans_dist::ReadResp 40424 # Transaction distribution -system.iobus.trans_dist::WriteReq 136766 # Transaction distribution -system.iobus.trans_dist::WriteResp 30038 # Transaction distribution +system.iobus.trans_dist::ReadReq 40350 # Transaction distribution +system.iobus.trans_dist::ReadResp 40350 # Transaction distribution +system.iobus.trans_dist::WriteReq 136657 # Transaction distribution +system.iobus.trans_dist::WriteResp 29929 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2220,13 +2202,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2241,13 +2223,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2275,71 +2257,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148521376 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115597 # number of replacements -system.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use +system.iocache.tags.replacements 115588 # number of replacements +system.iocache.tags.tagsinuse 11.296723 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115604 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9128912382000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841062 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.455661 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240066 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465979 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706045 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040901 # Number of tag accesses -system.iocache.tags.data_accesses 1040901 # Number of data accesses +system.iocache.tags.tag_accesses 1040820 # Number of tag accesses +system.iocache.tags.data_accesses 1040820 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8925 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses -system.iocache.demand_misses::total 8928 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses +system.iocache.demand_misses::total 8919 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8888 # number of overall misses -system.iocache.overall_misses::total 8928 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8879 # number of overall misses +system.iocache.overall_misses::total 8919 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1619625499 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1624820999 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1619625499 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1625189999 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1619625499 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1625189999 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2353,55 +2335,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182410.800653 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182236.540938 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110413 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16202 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.814776 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8879 # 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number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2415,558 +2397,564 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130278.657844 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130104.834343 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1473453 # number of replacements -system.l2c.tags.tagsinuse 64480.086956 # Cycle average of tags in use -system.l2c.tags.total_refs 5089807 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1533812 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.318403 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8003493500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id +system.l2c.tags.replacements 1509391 # number of replacements +system.l2c.tags.tagsinuse 64395.788312 # Cycle average of tags in use +system.l2c.tags.total_refs 5071928 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1569787 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.230966 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8741120000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 18420.928371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 254.564671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 327.558520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5783.699822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9967.407270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17191.318601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 126.325801 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 133.881896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2759.726372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3037.353013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6393.023977 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.281081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003884 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.088252 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.152091 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.262319 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001928 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.046346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.982602 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 14050 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_blocks::1024 46146 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1105 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 12755 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4647 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39226 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.214386 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65568567 # Number of tag accesses -system.l2c.tags.data_accesses 65568567 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 690690 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 361152 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 759258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 428313 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits -system.l2c.Writeback_hits::total 2491671 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 125819 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 140505 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 29765 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32403 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5875 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6386 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53337 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 690690 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 417549 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.159598 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.212332 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.772162 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.416217 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.680192 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.580068 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.618210 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.597717 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599180 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.575964 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.589362 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.600669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486599 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.551593 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.230987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.230987 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76466.442328 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75811.991013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 100350.980614 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33488.206062 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31928.465258 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33241.599928 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17801.475985 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.410326 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.437228 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17783.190071 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17807.754199 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17793.342409 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77798.752969 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70220.005490 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74922.402509 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2981,57 +2969,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 969598 # Transaction distribution -system.membus.trans_dist::ReadResp 969598 # Transaction distribution -system.membus.trans_dist::WriteReq 38347 # Transaction distribution -system.membus.trans_dist::WriteResp 38347 # Transaction distribution -system.membus.trans_dist::Writeback 1222910 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution -system.membus.trans_dist::UpgradeReq 426453 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115017 # Transaction distribution -system.membus.trans_dist::ReadExReq 144468 # Transaction distribution -system.membus.trans_dist::ReadExResp 127604 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 988965 # Transaction distribution +system.membus.trans_dist::ReadResp 988965 # Transaction distribution +system.membus.trans_dist::WriteReq 38599 # Transaction distribution +system.membus.trans_dist::WriteResp 38599 # Transaction distribution +system.membus.trans_dist::Writeback 1235035 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution +system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.membus.trans_dist::ReadExReq 147271 # Transaction distribution +system.membus.trans_dist::ReadExResp 130046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 617229 # Total snoops (count) -system.membus.snoop_fanout::samples 3621307 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 645066 # Total snoops (count) +system.membus.snoop_fanout::samples 3693594 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3621307 # Request fanout histogram -system.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3693594 # Request fanout histogram +system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3075,45 +3064,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1616950 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1680481 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index f3459bbfc..72f54d4c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.728175 # Number of seconds simulated -sim_ticks 51728174627500 # Number of ticks simulated -final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.690388 # Number of seconds simulated +sim_ticks 51690388482000 # Number of ticks simulated +final_tick 51690388482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121986 # Simulator instruction rate (inst/s) -host_op_rate 143338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6618487836 # Simulator tick rate (ticks/s) -host_mem_usage 708088 # Number of bytes of host memory used -host_seconds 7815.71 # Real time elapsed on the host -sim_insts 953410832 # Number of instructions simulated -sim_ops 1120287994 # Number of ops (including micro ops) simulated +host_inst_rate 185969 # Simulator instruction rate (inst/s) +host_op_rate 218525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10104822635 # Simulator tick rate (ticks/s) +host_mem_usage 719212 # Number of bytes of host memory used +host_seconds 5115.42 # Real time elapsed on the host +sim_insts 951311494 # Number of instructions simulated +sim_ops 1117847862 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10241472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 67386632 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory -system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 413184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 346752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10436032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 67415176 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415104 # Number of bytes read from this memory +system.physmem.bytes_read::total 79026248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10436032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10436032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 95778368 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1052929 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 95798948 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 163063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1053375 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6486 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1234798 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1496537 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1302707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1499110 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1304211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1528838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852924 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1303104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1230983 # Number of read requests accepted -system.physmem.writeReqs 2135785 # Number of write requests accepted -system.physmem.readBursts 1230983 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2135785 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78738176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44736 # Total number of bytes read from write queue -system.physmem.bytesWritten 136238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78782088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 136546148 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 699 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7032 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39789 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72855 # Per bank write bursts -system.physmem.perBankRdBursts::1 77589 # Per bank write bursts -system.physmem.perBankRdBursts::2 71702 # Per bank write bursts -system.physmem.perBankRdBursts::3 69206 # Per bank write bursts -system.physmem.perBankRdBursts::4 71012 # Per bank write bursts -system.physmem.perBankRdBursts::5 79882 # Per bank write bursts -system.physmem.perBankRdBursts::6 74555 # Per bank write bursts -system.physmem.perBankRdBursts::7 73696 # Per bank write bursts -system.physmem.perBankRdBursts::8 66951 # Per bank write bursts -system.physmem.perBankRdBursts::9 130748 # Per bank write bursts -system.physmem.perBankRdBursts::10 72702 # Per bank write bursts -system.physmem.perBankRdBursts::11 77684 # Per bank write bursts -system.physmem.perBankRdBursts::12 73029 # Per bank write bursts -system.physmem.perBankRdBursts::13 75645 # Per bank write bursts -system.physmem.perBankRdBursts::14 69035 # Per bank write bursts -system.physmem.perBankRdBursts::15 73993 # Per bank write bursts -system.physmem.perBankWrBursts::0 130105 # Per bank write bursts -system.physmem.perBankWrBursts::1 136647 # Per bank write bursts -system.physmem.perBankWrBursts::2 132594 # Per bank write bursts -system.physmem.perBankWrBursts::3 132058 # Per bank write bursts -system.physmem.perBankWrBursts::4 132790 # Per bank write bursts -system.physmem.perBankWrBursts::5 135723 # Per bank write bursts -system.physmem.perBankWrBursts::6 131916 # Per bank write bursts -system.physmem.perBankWrBursts::7 135307 # Per bank write bursts -system.physmem.perBankWrBursts::8 129762 # Per bank write bursts -system.physmem.perBankWrBursts::9 138269 # Per bank write bursts -system.physmem.perBankWrBursts::10 133041 # Per bank write bursts -system.physmem.perBankWrBursts::11 135411 # Per bank write bursts -system.physmem.perBankWrBursts::12 131809 # Per bank write bursts -system.physmem.perBankWrBursts::13 134107 # Per bank write bursts -system.physmem.perBankWrBursts::14 128778 # Per bank write bursts -system.physmem.perBankWrBursts::15 130414 # Per bank write bursts +system.physmem.bw_write::total 1853322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1304609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3382161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1234798 # Number of read requests accepted +system.physmem.writeReqs 2155868 # Number of write requests accepted +system.physmem.readBursts 1234798 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2155868 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78985984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 41088 # Total number of bytes read from write queue +system.physmem.bytesWritten 134775168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79026248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 137831460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 642 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49988 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39660 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74085 # Per bank write bursts +system.physmem.perBankRdBursts::1 76722 # Per bank write bursts +system.physmem.perBankRdBursts::2 75273 # Per bank write bursts +system.physmem.perBankRdBursts::3 67779 # Per bank write bursts +system.physmem.perBankRdBursts::4 73670 # Per bank write bursts +system.physmem.perBankRdBursts::5 87218 # Per bank write bursts +system.physmem.perBankRdBursts::6 75623 # Per bank write bursts +system.physmem.perBankRdBursts::7 75034 # Per bank write bursts +system.physmem.perBankRdBursts::8 70647 # Per bank write bursts +system.physmem.perBankRdBursts::9 127770 # Per bank write bursts +system.physmem.perBankRdBursts::10 77193 # Per bank write bursts +system.physmem.perBankRdBursts::11 73706 # Per bank write bursts +system.physmem.perBankRdBursts::12 69495 # Per bank write bursts +system.physmem.perBankRdBursts::13 70758 # Per bank write bursts +system.physmem.perBankRdBursts::14 68705 # Per bank write bursts +system.physmem.perBankRdBursts::15 70478 # Per bank write bursts +system.physmem.perBankWrBursts::0 131375 # Per bank write bursts +system.physmem.perBankWrBursts::1 133100 # Per bank write bursts +system.physmem.perBankWrBursts::2 134570 # Per bank write bursts +system.physmem.perBankWrBursts::3 130352 # Per bank write bursts +system.physmem.perBankWrBursts::4 132576 # Per bank write bursts +system.physmem.perBankWrBursts::5 140660 # Per bank write bursts +system.physmem.perBankWrBursts::6 130709 # Per bank write bursts +system.physmem.perBankWrBursts::7 134220 # Per bank write bursts +system.physmem.perBankWrBursts::8 130946 # Per bank write bursts +system.physmem.perBankWrBursts::9 136651 # Per bank write bursts +system.physmem.perBankWrBursts::10 131424 # Per bank write bursts +system.physmem.perBankWrBursts::11 131217 # Per bank write bursts +system.physmem.perBankWrBursts::12 125851 # Per bank write bursts +system.physmem.perBankWrBursts::13 128099 # Per bank write bursts +system.physmem.perBankWrBursts::14 126227 # Per bank write bursts +system.physmem.perBankWrBursts::15 127885 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51728172924500 # Total gap between requests +system.physmem.numWrRetry 155 # Number of times write queue was full causing retry +system.physmem.totGap 51690386784000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1230968 # Read request sizes (log2) +system.physmem.readPktSize::6 1234783 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2133212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1193516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2153295 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1198377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 29223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,161 +159,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 75161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 120471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 133680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 129638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 132279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 134371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 139351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 134041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 121456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 116921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 112653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 104822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 724941 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.543548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.840359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.964737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 292739 40.38% 40.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 175978 24.27% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 64522 8.90% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36242 5.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25200 3.48% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17306 2.39% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13334 1.84% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11857 1.64% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 87763 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 724941 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98383 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.504427 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 125.607658 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 98380 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 52281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 106555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 108316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 116449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 154618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 128128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 118111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 116108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 109682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 142032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 116099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 124147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 111898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 106882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 105751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 272 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 737863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.702517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.794717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.456499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 301335 40.84% 40.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 180643 24.48% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66243 8.98% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 37149 5.03% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25772 3.49% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17225 2.33% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13400 1.82% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11666 1.58% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 84430 11.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 737863 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 101448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.165149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 123.730461 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 101445 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98383 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.637183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.054808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.113777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 71754 72.93% 72.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 19885 20.21% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 3061 3.11% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 745 0.76% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 867 0.88% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 408 0.41% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 354 0.36% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 234 0.24% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 298 0.30% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 183 0.19% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 211 0.21% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 51 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 41 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 125 0.13% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 21 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 37 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 12 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98383 # Writes before turning the bus around for reads -system.physmem.totQLat 15890716010 # Total ticks spent queuing -system.physmem.totMemAccLat 38958541010 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6151420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12916.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 101448 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 101448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.758044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.253158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.739377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 97720 96.33% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2404 2.37% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 434 0.43% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 505 0.50% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 168 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 63 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 44 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 12 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 10 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 20 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-863 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-959 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 101448 # Writes before turning the bus around for reads +system.physmem.totQLat 16140892467 # Total ticks spent queuing +system.physmem.totMemAccLat 39281317467 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6170780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13078.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31666.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31828.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 953619 # Number of row buffer hits during reads -system.physmem.writeRowHits 1680454 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes -system.physmem.avgGap 15364341.39 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2748558960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1499709750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4605829800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6915067200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1310572243215 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29887277315250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34592251323855 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.731394 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49719326487750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 952465 # Number of row buffer hits during reads +system.physmem.writeRowHits 1649689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes +system.physmem.avgGap 15244906.69 # Average gap between requests +system.physmem.pageHitRate 77.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2866207680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1563903000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4722104400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6917801760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1320834277260 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29855603520000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34568672372100 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764092 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49666580122402 # Time in different power states +system.physmem_0.memoryStateTime::REF 1726055500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 281530424750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 297752382598 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2731995000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1490671875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4990338600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6879109680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1309819963770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29887937201250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34592481879855 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.735851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49720391571002 # Time in different power states -system.physmem_1.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem_1.actEnergy 2712036600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1479781875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4904265600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6728184000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1311236111385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29864022963750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34567247901210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.736534 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49680605946994 # Time in different power states +system.physmem_1.memoryStateTime::REF 1726055500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states +system.physmem_1.memoryStateTime::ACT 283722031756 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -337,15 +334,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261740307 # Number of BP lookups -system.cpu.branchPred.condPredicted 183617747 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12193617 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193974198 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136954935 # Number of BTB hits +system.cpu.branchPred.lookups 261231631 # Number of BP lookups +system.cpu.branchPred.condPredicted 183305796 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12196019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193363774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136711559 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.604718 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31757981 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2120874 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.701743 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31664930 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2143732 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -376,61 +373,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 587644 # Table walker walks requested -system.cpu.dtb.walker.walksLong 587644 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20971 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 193860 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 587644 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 587644 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 587644 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 214831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23073.231987 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 212337 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2138 1.00% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 152 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 133 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 38 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 214831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -243009796 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -243009796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -243009796 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 193861 90.24% 90.24% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20971 9.76% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 214832 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 587644 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 585994 # Table walker walks requested +system.cpu.dtb.walker.walksLong 585994 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21793 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191747 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 585994 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 585994 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 585994 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24710.005137 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20824.581984 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15872.776829 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 123160 57.68% 57.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 87731 41.08% 98.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1449 0.68% 99.44% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 786 0.37% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 33 0.02% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 127 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 51 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 62 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 77 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 191748 89.79% 89.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 21793 10.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213541 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 585994 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 587644 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 214832 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 585994 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213541 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 214832 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 802476 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213541 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 799535 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184101010 # DTB read hits -system.cpu.dtb.read_misses 486113 # DTB read misses -system.cpu.dtb.write_hits 163332837 # DTB write hits -system.cpu.dtb.write_misses 101531 # DTB write misses +system.cpu.dtb.read_hits 183604569 # DTB read hits +system.cpu.dtb.read_misses 484391 # DTB read misses +system.cpu.dtb.write_hits 162970808 # DTB write hits +system.cpu.dtb.write_misses 101603 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 79171 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14871 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 80226 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 794 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23598 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184587123 # DTB read accesses -system.cpu.dtb.write_accesses 163434368 # DTB write accesses +system.cpu.dtb.perms_faults 23565 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 184088960 # DTB read accesses +system.cpu.dtb.write_accesses 163072411 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 347433847 # DTB hits -system.cpu.dtb.misses 587644 # DTB misses -system.cpu.dtb.accesses 348021491 # DTB accesses +system.cpu.dtb.hits 346575377 # DTB hits +system.cpu.dtb.misses 585994 # DTB misses +system.cpu.dtb.accesses 347161371 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,175 +464,175 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136955 # Table walker walks requested -system.cpu.itb.walker.walksLong 136955 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1083 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 119238 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136955 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136955 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136955 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 120321 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 25178.697160 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 21090.590253 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16725.174106 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 117467 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2593 2.16% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 161 0.13% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 40 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 38 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136676 # Table walker walks requested +system.cpu.itb.walker.walksLong 136676 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118957 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136676 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136676 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136676 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27117.842072 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23228.726671 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17468.785563 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 117053 97.51% 97.51% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2702 2.25% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 172 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 64 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 25 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 17 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 120321 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -243525796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -243525796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -243525796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 119238 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1083 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 120321 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 118957 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1079 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120036 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136676 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136676 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120321 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 120321 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 257276 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 455989522 # ITB inst hits -system.cpu.itb.inst_misses 136955 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120036 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120036 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256712 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 454948976 # ITB inst hits +system.cpu.itb.inst_misses 136676 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56761 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57709 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 364272 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 370702 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 456126477 # ITB inst accesses -system.cpu.itb.hits 455989522 # DTB hits -system.cpu.itb.misses 136955 # DTB misses -system.cpu.itb.accesses 456126477 # DTB accesses -system.cpu.numCycles 2523007146 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 455085652 # ITB inst accesses +system.cpu.itb.hits 454948976 # DTB hits +system.cpu.itb.misses 136676 # DTB misses +system.cpu.itb.accesses 455085652 # DTB accesses +system.cpu.numCycles 2543244455 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 953410832 # Number of instructions committed -system.cpu.committedOps 1120287994 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97416264 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100934517430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.646296 # CPI: cycles per instruction -system.cpu.ipc 0.377887 # IPC: instructions per cycle +system.cpu.committedInsts 951311494 # Number of instructions committed +system.cpu.committedOps 1117847862 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97312681 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7756 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100838701590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.673409 # CPI: cycles per instruction +system.cpu.ipc 0.374054 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed -system.cpu.tickCycles 1807938889 # Number of cycles that the object actually ticked -system.cpu.idleCycles 715068257 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11209162 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959689 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 331084794 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.959689 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999921 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16616 # number of quiesce instructions executed +system.cpu.tickCycles 1803568308 # Number of cycles that the object actually ticked +system.cpu.idleCycles 739676147 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11160252 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957398 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 330283218 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11160764 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.593245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957398 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 169770938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 152453541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337498 # 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miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056420 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1387540349 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1387540349 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 169325544 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 169325544 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 152117254 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 152117254 # number of WriteReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336638 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336638 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4103260 # 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number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 249194 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 249194 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 12367141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12367141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12367141 # number of overall misses +system.cpu.dcache.overall_misses::total 12367141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 131461867675 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 131461867675 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 154903534956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 154903534956 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35707428702 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35707428702 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 286365402631 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 286365402631 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 286365402631 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 286365402631 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177372458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177372458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 156437481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156437481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581776 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1581776 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4352454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4352454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4350722 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4350722 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 333809939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 333809939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 333809939 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333809939 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045367 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.045367 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787177 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787177 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057254 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037126 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037126 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15933.402940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23155.343877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23155.343877 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,82 +641,82 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176220325212 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 8571803 # number of writebacks +system.cpu.dcache.writebacks::total 8571803 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 759012 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 759012 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1891728 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1891728 # 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number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2428499 # number of WriteReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244986 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244986 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9716401 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9716401 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9716401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9716401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108232242328 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108232242328 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80044946410 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80044946410 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33835516298 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33835516298 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 188277188738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 188277188738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188277188738 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 188277188738 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5752052750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5752052750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611431750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611431750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363484500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363484500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787081 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787081 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057253 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057253 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14850.946449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14850.946449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32960.666819 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32960.666819 # average WriteReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27177.427134 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27177.427134 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -720,58 +724,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24725990 # number of replacements -system.cpu.icache.tags.tagsinuse 511.931995 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 430886861 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24726502 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.426115 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21192166000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.931995 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999867 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999867 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24658319 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926866 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 429907589 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24658831 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.434224 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 23112715250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 480339884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 480339884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 430886861 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 430886861 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 430886861 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 430886861 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 430886861 # number of overall hits -system.cpu.icache.overall_hits::total 430886861 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24726512 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24726512 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24726512 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24726512 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24726512 # number of overall misses -system.cpu.icache.overall_misses::total 24726512 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328589993689 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328589993689 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328589993689 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328589993689 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328589993689 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328589993689 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 455613373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 455613373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 455613373 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 455613373 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 455613373 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 455613373 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13288.974753 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13288.974753 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13288.974753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13288.974753 # average overall miss latency +system.cpu.icache.tags.tag_accesses 479225270 # Number of tag accesses +system.cpu.icache.tags.data_accesses 479225270 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 429907589 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 429907589 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 429907589 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 429907589 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 429907589 # number of overall hits +system.cpu.icache.overall_hits::total 429907589 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24658841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24658841 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24658841 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24658841 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24658841 # number of overall misses +system.cpu.icache.overall_misses::total 24658841 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328732138519 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328732138519 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328732138519 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328732138519 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328732138519 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328732138519 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 454566430 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 454566430 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 454566430 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 454566430 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 454566430 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 454566430 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13331.208004 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13331.208004 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13331.208004 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13331.208004 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13331.208004 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13331.208004 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -780,208 +784,209 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24726512 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24726512 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24726512 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11287.019446 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 348.587735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 419.061629 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8126.200133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20284.052712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.551613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006394 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.309510 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996832 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 298 # 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number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24726509 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9964863 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35951246 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006337 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004359 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013530 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782463 # 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average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.920584 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61582.977042 # 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Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2389846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2389846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49557548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31248640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2279215 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83780992 # 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Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 33999690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33991608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8571803 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 49797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2378926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2378926 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31128556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2275060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83523491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581512448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1263125858 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2313872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7794488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2854746666 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 562001 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46265986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002499 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 46294483 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115543 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 46150346 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115640 0.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46410026 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 33063458385 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 46265986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32968786985 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1149000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1168500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37204558207 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37104005805 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15864083234 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15790852218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 409855669 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 409077948 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1306481232 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1301562725 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40405 # Transaction distribution -system.iobus.trans_dist::ReadResp 40405 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40307 # Transaction distribution +system.iobus.trans_dist::ReadResp 40307 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1180,13 +1183,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230972 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230972 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1201,13 +1204,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334320 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492862 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1235,71 +1238,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042384689 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606946752 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179052263 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148389141 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.452585 # Cycle average of tags in use +system.iocache.tags.replacements 115468 # number of replacements +system.iocache.tags.tagsinuse 10.447877 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115484 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141230176000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.516704 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935881 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219794 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653287 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13143236480000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519281 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928596 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219955 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433037 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652992 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.tags.tag_accesses 1039731 # Number of tag accesses +system.iocache.tags.data_accesses 1039731 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8822 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8859 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses -system.iocache.demand_misses::total 8879 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8822 # number of demand (read+write) misses +system.iocache.demand_misses::total 8862 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8839 # number of overall misses -system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1924538358 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1930023358 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28851084068 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28851084068 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1924538358 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1930362358 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1924538358 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1930362358 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8822 # number of overall misses +system.iocache.overall_misses::total 8862 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1598742761 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1603814761 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1598742761 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1604167261 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1598742761 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1604167261 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8822 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8859 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8822 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8862 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8822 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8862 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1313,55 +1316,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217442.920009 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217407.631265 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217407.631265 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225366 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181222.258105 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181037.900553 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 108614 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27560 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16000 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.177286 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.788375 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8822 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8859 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8822 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8862 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1464798862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1468359862 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23304534090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23304534090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1464798862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1468542862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1464798862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1468542862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8822 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8862 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1138893007 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1142035007 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1138893007 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1142228507 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1138893007 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1142228507 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1375,71 +1378,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129096.917592 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128912.406254 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 548979 # Transaction distribution -system.membus.trans_dist::ReadResp 548979 # Transaction distribution -system.membus.trans_dist::WriteReq 33870 # Transaction distribution -system.membus.trans_dist::WriteResp 33870 # Transaction distribution -system.membus.trans_dist::Writeback 1485997 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 647215 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 647215 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39795 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39797 # Transaction distribution -system.membus.trans_dist::ReadExReq 718688 # Transaction distribution -system.membus.trans_dist::ReadExResp 718688 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 553634 # Transaction distribution +system.membus.trans_dist::ReadResp 553634 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::Writeback 1496537 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 656758 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 656758 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39666 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39667 # Transaction distribution +system.membus.trans_dist::ReadExReq 717891 # Transaction distribution +system.membus.trans_dist::ReadExResp 717891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4994566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5124714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5460180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5031846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5161506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5496813 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13852 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201253164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201424076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14075072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14075072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 215499148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2915 # Total snoops (count) -system.membus.snoop_fanout::samples 3354632 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202791724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202962146 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14065984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14065984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 217028130 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3038 # Total snoops (count) +system.membus.snoop_fanout::samples 3378648 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3354632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3378648 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3354632 # Request fanout histogram -system.membus.reqLayer0.occupancy 113785000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3378648 # Request fanout histogram +system.membus.reqLayer0.occupancy 100002500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5606499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5714500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21358745741 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12721299869 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12484485177 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7256295209 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186617737 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151537359 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1450,11 +1453,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 3916ea1cc..5a693d4ac 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320647 # Number of seconds simulated -sim_ticks 51320647066500 # Number of ticks simulated -final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320469 # Number of seconds simulated +sim_ticks 51320468905000 # Number of ticks simulated +final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81694 # Simulator instruction rate (inst/s) -host_op_rate 95992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4889396972 # Simulator tick rate (ticks/s) -host_mem_usage 723156 # Number of bytes of host memory used -host_seconds 10496.31 # Real time elapsed on the host -sim_insts 857487967 # Number of instructions simulated -sim_ops 1007562352 # Number of ops (including micro ops) simulated +host_inst_rate 78766 # Simulator instruction rate (inst/s) +host_op_rate 92549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4725007878 # Simulator tick rate (ticks/s) +host_mem_usage 722788 # Number of bytes of host memory used +host_seconds 10861.46 # Real time elapsed on the host +sim_insts 855512158 # Number of instructions simulated +sim_ops 1005211605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory -system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory +system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 791544 # Number of read requests accepted -system.physmem.writeReqs 1694292 # Number of write requests accepted -system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue -system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 48315 # Per bank write bursts -system.physmem.perBankRdBursts::1 50150 # Per bank write bursts -system.physmem.perBankRdBursts::2 46175 # Per bank write bursts -system.physmem.perBankRdBursts::3 46946 # Per bank write bursts -system.physmem.perBankRdBursts::4 45323 # Per bank write bursts -system.physmem.perBankRdBursts::5 52981 # Per bank write bursts -system.physmem.perBankRdBursts::6 47646 # Per bank write bursts -system.physmem.perBankRdBursts::7 48748 # Per bank write bursts -system.physmem.perBankRdBursts::8 44337 # Per bank write bursts -system.physmem.perBankRdBursts::9 72322 # Per bank write bursts -system.physmem.perBankRdBursts::10 50834 # Per bank write bursts -system.physmem.perBankRdBursts::11 50772 # Per bank write bursts -system.physmem.perBankRdBursts::12 48451 # Per bank write bursts -system.physmem.perBankRdBursts::13 47387 # Per bank write bursts -system.physmem.perBankRdBursts::14 44232 # Per bank write bursts -system.physmem.perBankRdBursts::15 46363 # Per bank write bursts -system.physmem.perBankWrBursts::0 103979 # Per bank write bursts -system.physmem.perBankWrBursts::1 105038 # Per bank write bursts -system.physmem.perBankWrBursts::2 105754 # Per bank write bursts -system.physmem.perBankWrBursts::3 105161 # Per bank write bursts -system.physmem.perBankWrBursts::4 103562 # Per bank write bursts -system.physmem.perBankWrBursts::5 108435 # Per bank write bursts -system.physmem.perBankWrBursts::6 103867 # Per bank write bursts -system.physmem.perBankWrBursts::7 105467 # Per bank write bursts -system.physmem.perBankWrBursts::8 102645 # Per bank write bursts -system.physmem.perBankWrBursts::9 108407 # Per bank write bursts -system.physmem.perBankWrBursts::10 108582 # Per bank write bursts -system.physmem.perBankWrBursts::11 107982 # Per bank write bursts -system.physmem.perBankWrBursts::12 105330 # Per bank write bursts -system.physmem.perBankWrBursts::13 105345 # Per bank write bursts -system.physmem.perBankWrBursts::14 103911 # Per bank write bursts -system.physmem.perBankWrBursts::15 104029 # Per bank write bursts +system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 784654 # Number of read requests accepted +system.physmem.writeReqs 1688539 # Number of write requests accepted +system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue +system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 46664 # Per bank write bursts +system.physmem.perBankRdBursts::1 51485 # Per bank write bursts +system.physmem.perBankRdBursts::2 48018 # Per bank write bursts +system.physmem.perBankRdBursts::3 46409 # Per bank write bursts +system.physmem.perBankRdBursts::4 44064 # Per bank write bursts +system.physmem.perBankRdBursts::5 51949 # Per bank write bursts +system.physmem.perBankRdBursts::6 45895 # Per bank write bursts +system.physmem.perBankRdBursts::7 48923 # Per bank write bursts +system.physmem.perBankRdBursts::8 45299 # Per bank write bursts +system.physmem.perBankRdBursts::9 70789 # Per bank write bursts +system.physmem.perBankRdBursts::10 48156 # Per bank write bursts +system.physmem.perBankRdBursts::11 46739 # Per bank write bursts +system.physmem.perBankRdBursts::12 48771 # Per bank write bursts +system.physmem.perBankRdBursts::13 48997 # Per bank write bursts +system.physmem.perBankRdBursts::14 45133 # Per bank write bursts +system.physmem.perBankRdBursts::15 46835 # Per bank write bursts +system.physmem.perBankWrBursts::0 99610 # Per bank write bursts +system.physmem.perBankWrBursts::1 104326 # Per bank write bursts +system.physmem.perBankWrBursts::2 103481 # Per bank write bursts +system.physmem.perBankWrBursts::3 102430 # Per bank write bursts +system.physmem.perBankWrBursts::4 101747 # Per bank write bursts +system.physmem.perBankWrBursts::5 104971 # Per bank write bursts +system.physmem.perBankWrBursts::6 100056 # Per bank write bursts +system.physmem.perBankWrBursts::7 103888 # Per bank write bursts +system.physmem.perBankWrBursts::8 99840 # Per bank write bursts +system.physmem.perBankWrBursts::9 106110 # Per bank write bursts +system.physmem.perBankWrBursts::10 102643 # Per bank write bursts +system.physmem.perBankWrBursts::11 100858 # Per bank write bursts +system.physmem.perBankWrBursts::12 103355 # Per bank write bursts +system.physmem.perBankWrBursts::13 103593 # Per bank write bursts +system.physmem.perBankWrBursts::14 100350 # Per bank write bursts +system.physmem.perBankWrBursts::15 101960 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51320645833500 # Total gap between requests +system.physmem.numWrRetry 560 # Number of times write queue was full causing retry +system.physmem.totGap 51320467654000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 770259 # Read request sizes (log2) +system.physmem.readPktSize::6 763369 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1691719 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1685966 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,163 +159,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads -system.physmem.totQLat 15484448260 # Total ticks spent queuing -system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads +system.physmem.totQLat 15388206863 # Total ticks spent queuing +system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing -system.physmem.readRowHits 603455 # Number of row buffer hits during reads -system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 20645225.93 # Average gap between requests -system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.473889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing +system.physmem.readRowHits 598254 # Number of row buffer hits during reads +system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes +system.physmem.avgGap 20750692.59 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.470318 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.480369 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.479291 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states +system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -339,15 +336,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226505876 # Number of BP lookups -system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits +system.cpu.branchPred.lookups 226088242 # Number of BP lookups +system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,45 +375,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 200647 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 200647 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 200647 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 200647 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 200647 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 1467106000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 1467106000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 1467106000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 155618 91.17% 91.17% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 15067 8.83% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 170685 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200647 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 200795 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 200795 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 200795 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 200795 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 200795 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 1638530500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 1638530500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 1638530500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 155523 90.97% 90.97% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 15432 9.03% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 170955 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200795 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200647 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170685 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200795 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170955 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170685 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 371332 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170955 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 371750 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 161284967 # DTB read hits -system.cpu.checker.dtb.read_misses 149209 # DTB read misses -system.cpu.checker.dtb.write_hits 146334371 # DTB write hits -system.cpu.checker.dtb.write_misses 51438 # DTB write misses +system.cpu.checker.dtb.read_hits 160924630 # DTB read hits +system.cpu.checker.dtb.read_misses 149513 # DTB read misses +system.cpu.checker.dtb.write_hits 145982592 # DTB write hits +system.cpu.checker.dtb.write_misses 51282 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72843 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 72580 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7088 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7050 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19208 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 161434176 # DTB read accesses -system.cpu.checker.dtb.write_accesses 146385809 # DTB write accesses +system.cpu.checker.dtb.perms_faults 19166 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 161074143 # DTB read accesses +system.cpu.checker.dtb.write_accesses 146033874 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 307619338 # DTB hits -system.cpu.checker.dtb.misses 200647 # DTB misses -system.cpu.checker.dtb.accesses 307819985 # DTB accesses +system.cpu.checker.dtb.hits 306907222 # DTB hits +system.cpu.checker.dtb.misses 200795 # DTB misses +system.cpu.checker.dtb.accesses 307108017 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,46 +443,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 120779 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 120779 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 120779 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 120779 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 120779 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 1466561000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 1466561000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 1466561000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 108783 98.83% 98.83% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1287 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 110070 # Table walker page sizes translated +system.cpu.checker.itb.walker.walks 120591 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 120591 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 120591 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 120591 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 120591 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 1637932000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 1637932000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 1637932000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 108617 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1291 1.17% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109908 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120779 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120779 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120591 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120591 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 110070 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 110070 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 230849 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 857899518 # ITB inst hits -system.cpu.checker.itb.inst_misses 120779 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109908 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109908 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 230499 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 855922330 # ITB inst hits +system.cpu.checker.itb.inst_misses 120591 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 52284 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 52096 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 858020297 # ITB inst accesses -system.cpu.checker.itb.hits 857899518 # DTB hits -system.cpu.checker.itb.misses 120779 # DTB misses -system.cpu.checker.itb.accesses 858020297 # DTB accesses -system.cpu.checker.numCycles 1008137807 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 856042921 # ITB inst accesses +system.cpu.checker.itb.hits 855922330 # DTB hits +system.cpu.checker.itb.misses 120591 # DTB misses +system.cpu.checker.itb.accesses 856042921 # DTB accesses +system.cpu.checker.numCycles 1005785493 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -517,87 +514,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 931379 # Table walker walks requested -system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 945525 # Table walker walks requested +system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 171278986 # DTB read hits -system.cpu.dtb.read_misses 671795 # DTB read misses -system.cpu.dtb.write_hits 149102166 # DTB write hits -system.cpu.dtb.write_misses 259584 # DTB write misses +system.cpu.dtb.read_hits 170900022 # DTB read hits +system.cpu.dtb.read_misses 675244 # DTB read misses +system.cpu.dtb.write_hits 148749524 # DTB write hits +system.cpu.dtb.write_misses 270281 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171950781 # DTB read accesses -system.cpu.dtb.write_accesses 149361750 # DTB write accesses +system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171575266 # DTB read accesses +system.cpu.dtb.write_accesses 149019805 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320381152 # DTB hits -system.cpu.dtb.misses 931379 # DTB misses -system.cpu.dtb.accesses 321312531 # DTB accesses +system.cpu.dtb.hits 319649546 # DTB hits +system.cpu.dtb.misses 945525 # DTB misses +system.cpu.dtb.accesses 320595071 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -627,214 +623,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161841 # Table walker walks requested -system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161869 # Table walker walks requested +system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 360168043 # ITB inst hits -system.cpu.itb.inst_misses 161841 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 359459512 # ITB inst hits +system.cpu.itb.inst_misses 161869 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 360329884 # ITB inst accesses -system.cpu.itb.hits 360168043 # DTB hits -system.cpu.itb.misses 161841 # DTB misses -system.cpu.itb.accesses 360329884 # DTB accesses -system.cpu.numCycles 1576983833 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 359621381 # ITB inst accesses +system.cpu.itb.hits 359459512 # DTB hits +system.cpu.itb.misses 161869 # DTB misses +system.cpu.itb.accesses 359621381 # DTB accesses +system.cpu.numCycles 1580751099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -856,102 +847,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued -system.cpu.iq.rate 0.670005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued +system.cpu.iq.rate 0.666896 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224348 # number of nop insts executed -system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed -system.cpu.iew.exec_branches 198404489 # Number of branches executed -system.cpu.iew.exec_stores 149099070 # Number of stores executed -system.cpu.iew.exec_rate 0.662897 # Inst execution rate -system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back -system.cpu.iew.wb_producers 442335874 # num instructions producing a value -system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value +system.cpu.iew.exec_nop 222943 # number of nop insts executed +system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed +system.cpu.iew.exec_branches 197926826 # Number of branches executed +system.cpu.iew.exec_stores 148745526 # Number of stores executed +system.cpu.iew.exec_rate 0.659804 # Inst execution rate +system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back +system.cpu.iew.wb_producers 441278048 # num instructions producing a value +system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back +system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle -system.cpu.commit.committedInsts 857487967 # Number of instructions committed -system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle +system.cpu.commit.committedInsts 855512158 # Number of instructions committed +system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307720812 # Number of memory references committed -system.cpu.commit.loads 161382253 # Number of loads committed -system.cpu.commit.membars 7017472 # Number of memory barriers committed -system.cpu.commit.branches 191417503 # Number of branches committed -system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. -system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. -system.cpu.commit.function_calls 25509836 # Number of function calls committed. +system.cpu.commit.refs 307009160 # Number of memory references committed +system.cpu.commit.loads 161022390 # Number of loads committed +system.cpu.commit.membars 6998413 # Number of memory barriers committed +system.cpu.commit.branches 190975004 # Number of branches committed +system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions. +system.cpu.commit.int_insts 923410198 # Number of committed integer instructions. +system.cpu.commit.function_calls 25456304 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -974,236 +965,236 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction -system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction +system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2555751551 # The number of ROB reads -system.cpu.rob.rob_writes 2129995502 # The number of ROB writes -system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 857487967 # Number of Instructions Simulated -system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads -system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads -system.cpu.int_regfile_writes 738733253 # number of integer regfile writes -system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads -system.cpu.fp_regfile_writes 782548 # number of floating regfile writes -system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads -system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes -system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads -system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9822587 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 2555711925 # The number of ROB reads +system.cpu.rob.rob_writes 2125474325 # The number of ROB writes +system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 855512158 # Number of Instructions Simulated +system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads +system.cpu.int_regfile_writes 737118920 # number of integer regfile writes +system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads +system.cpu.fp_regfile_writes 784484 # number of floating regfile writes +system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads +system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes +system.cpu.misc_regfile_reads 5246257758 # number of misc regfile reads +system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9794555 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits -system.cpu.dcache.overall_hits::total 278710234 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses -system.cpu.dcache.overall_misses::total 22162626 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits +system.cpu.dcache.overall_hits::total 278057664 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22142972 # 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miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks -system.cpu.dcache.writebacks::total 7597183 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7148 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7148 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220034 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 220034 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13745551 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13745551 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13745551 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13745551 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5177976 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5177976 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041958 # 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number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks +system.cpu.dcache.writebacks::total 7577660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # 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number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # 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Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374842526 # 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number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 978 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 11.309816 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 717343 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 717343 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 717343 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 717343 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 717343 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 717343 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15084780 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15084780 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15084780 # 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number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1412899000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1412899000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1412899000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041930 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.041930 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.041930 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 744199 # 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number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # 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Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7620.063188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299945 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62489 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2670 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953506 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 273259305 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 273259305 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 799874 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299425 # 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Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9499 # 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average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # 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number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1607,66 +1597,62 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 606880 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.003347 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 583028 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 34397489 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 115519 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 34071281 99.66% 99.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115623 0.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40381 # Transaction distribution -system.iobus.trans_dist::ReadResp 40381 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40283 # Transaction distribution +system.iobus.trans_dist::ReadResp 40283 # Transaction distribution +system.iobus.trans_dist::WriteReq 136558 # Transaction distribution +system.iobus.trans_dist::WriteResp 29894 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1676,18 +1662,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1697,18 +1683,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1728,7 +1714,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1736,71 +1722,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115461 # number of replacements -system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use +system.iocache.tags.replacements 115456 # number of replacements +system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses -system.iocache.demand_misses::total 8855 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses +system.iocache.demand_misses::total 8851 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8815 # number of overall misses -system.iocache.overall_misses::total 8855 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8811 # number of overall misses +system.iocache.overall_misses::total 8851 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1814,55 +1800,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1876,71 +1862,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 411277 # Transaction distribution -system.membus.trans_dist::ReadResp 411277 # Transaction distribution -system.membus.trans_dist::WriteReq 33858 # Transaction distribution -system.membus.trans_dist::WriteResp 33858 # Transaction distribution -system.membus.trans_dist::Writeback 1089351 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution -system.membus.trans_dist::ReadExReq 417183 # Transaction distribution -system.membus.trans_dist::ReadExResp 417183 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 408284 # Transaction distribution +system.membus.trans_dist::ReadResp 408284 # Transaction distribution +system.membus.trans_dist::WriteReq 33682 # Transaction distribution +system.membus.trans_dist::WriteResp 33682 # Transaction distribution +system.membus.trans_dist::Writeback 1083893 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution +system.membus.trans_dist::ReadExReq 413056 # Transaction distribution +system.membus.trans_dist::ReadExResp 413056 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3154 # Total snoops (count) -system.membus.snoop_fanout::samples 2500418 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3023 # Total snoops (count) +system.membus.snoop_fanout::samples 2488136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2500418 # Request fanout histogram -system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2488136 # Request fanout histogram +system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1985,6 +1971,6 @@ system.realview.ethernet.coalescedTotal 0 # av system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 828771ce9..b1b40f923 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.345385 # Number of seconds simulated -sim_ticks 47345385235500 # Number of ticks simulated -final_tick 47345385235500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.305566 # Number of seconds simulated +sim_ticks 47305566199500 # Number of ticks simulated +final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106392 # Simulator instruction rate (inst/s) -host_op_rate 125133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5453309126 # Simulator tick rate (ticks/s) -host_mem_usage 767036 # Number of bytes of host memory used -host_seconds 8681.96 # Real time elapsed on the host -sim_insts 923688991 # Number of instructions simulated -sim_ops 1086395427 # Number of ops (including micro ops) simulated +host_inst_rate 109110 # Simulator instruction rate (inst/s) +host_op_rate 128307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5804669404 # Simulator tick rate (ticks/s) +host_mem_usage 767140 # Number of bytes of host memory used +host_seconds 8149.57 # Real time elapsed on the host +sim_insts 889196991 # Number of instructions simulated +sim_ops 1045647845 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 161152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 146432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4268768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16023832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 20180672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 156416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3463536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11559072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14510464 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437312 # Number of bytes read from this memory -system.physmem.bytes_read::total 71087496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4268768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3463536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7732304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86253568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory +system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86274384 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2288 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 250394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 315323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 54162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 180625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 226726 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6833 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1126775 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1347712 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75137680 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 952 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 201736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 203385 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39466 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 163804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 227756 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6861 # Number of read requests responded to by this memory +system.physmem.num_reads::total 936643 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1173701 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1350315 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 338445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 426244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 244144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 306481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1501466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73155 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 163317 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1821795 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1176304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 95193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 272901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 275161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 221592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 308133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1245500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 95193 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 148527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587908 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1822234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1821795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 338885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 426244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 244144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 306481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3323700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1126775 # Number of read requests accepted -system.physmem.writeReqs 2040290 # Number of write requests accepted -system.physmem.readBursts 1126775 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2040290 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72094336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19264 # Total number of bytes read from write queue -system.physmem.bytesWritten 130093376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 71087496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 130432784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7556 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 121134 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65675 # Per bank write bursts -system.physmem.perBankRdBursts::1 75833 # Per bank write bursts -system.physmem.perBankRdBursts::2 67256 # Per bank write bursts -system.physmem.perBankRdBursts::3 67290 # Per bank write bursts -system.physmem.perBankRdBursts::4 71240 # Per bank write bursts -system.physmem.perBankRdBursts::5 82191 # Per bank write bursts -system.physmem.perBankRdBursts::6 67013 # Per bank write bursts -system.physmem.perBankRdBursts::7 67787 # Per bank write bursts -system.physmem.perBankRdBursts::8 61707 # Per bank write bursts -system.physmem.perBankRdBursts::9 85775 # Per bank write bursts -system.physmem.perBankRdBursts::10 61014 # Per bank write bursts -system.physmem.perBankRdBursts::11 72520 # Per bank write bursts -system.physmem.perBankRdBursts::12 65793 # Per bank write bursts -system.physmem.perBankRdBursts::13 74631 # Per bank write bursts -system.physmem.perBankRdBursts::14 69278 # Per bank write bursts -system.physmem.perBankRdBursts::15 71471 # Per bank write bursts -system.physmem.perBankWrBursts::0 122526 # Per bank write bursts -system.physmem.perBankWrBursts::1 130111 # Per bank write bursts -system.physmem.perBankWrBursts::2 125889 # Per bank write bursts -system.physmem.perBankWrBursts::3 127486 # Per bank write bursts -system.physmem.perBankWrBursts::4 126972 # Per bank write bursts -system.physmem.perBankWrBursts::5 136977 # Per bank write bursts -system.physmem.perBankWrBursts::6 126845 # Per bank write bursts -system.physmem.perBankWrBursts::7 128268 # Per bank write bursts -system.physmem.perBankWrBursts::8 123854 # Per bank write bursts -system.physmem.perBankWrBursts::9 125736 # Per bank write bursts -system.physmem.perBankWrBursts::10 125360 # Per bank write bursts -system.physmem.perBankWrBursts::11 131761 # Per bank write bursts -system.physmem.perBankWrBursts::12 119984 # Per bank write bursts -system.physmem.perBankWrBursts::13 126166 # Per bank write bursts -system.physmem.perBankWrBursts::14 125889 # Per bank write bursts -system.physmem.perBankWrBursts::15 128885 # Per bank write bursts +system.physmem.bw_write::total 1588348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 95193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 273341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 275161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 221592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 308133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2833848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 936643 # Number of read requests accepted +system.physmem.writeReqs 1837953 # Number of write requests accepted +system.physmem.readBursts 936643 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1837953 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59924608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 114470976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58919096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117483216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49325 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 117374 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 55305 # Per bank write bursts +system.physmem.perBankRdBursts::1 59995 # Per bank write bursts +system.physmem.perBankRdBursts::2 52034 # Per bank write bursts +system.physmem.perBankRdBursts::3 56018 # Per bank write bursts +system.physmem.perBankRdBursts::4 58058 # Per bank write bursts +system.physmem.perBankRdBursts::5 68871 # Per bank write bursts +system.physmem.perBankRdBursts::6 59545 # Per bank write bursts +system.physmem.perBankRdBursts::7 57406 # Per bank write bursts +system.physmem.perBankRdBursts::8 51483 # Per bank write bursts +system.physmem.perBankRdBursts::9 77850 # Per bank write bursts +system.physmem.perBankRdBursts::10 53930 # Per bank write bursts +system.physmem.perBankRdBursts::11 57982 # Per bank write bursts +system.physmem.perBankRdBursts::12 54532 # Per bank write bursts +system.physmem.perBankRdBursts::13 56851 # Per bank write bursts +system.physmem.perBankRdBursts::14 60976 # Per bank write bursts +system.physmem.perBankRdBursts::15 55486 # Per bank write bursts +system.physmem.perBankWrBursts::0 110085 # Per bank write bursts +system.physmem.perBankWrBursts::1 112883 # Per bank write bursts +system.physmem.perBankWrBursts::2 108062 # Per bank write bursts +system.physmem.perBankWrBursts::3 109070 # Per bank write bursts +system.physmem.perBankWrBursts::4 113169 # Per bank write bursts +system.physmem.perBankWrBursts::5 118310 # Per bank write bursts +system.physmem.perBankWrBursts::6 115499 # Per bank write bursts +system.physmem.perBankWrBursts::7 111959 # Per bank write bursts +system.physmem.perBankWrBursts::8 107874 # Per bank write bursts +system.physmem.perBankWrBursts::9 113071 # Per bank write bursts +system.physmem.perBankWrBursts::10 109141 # Per bank write bursts +system.physmem.perBankWrBursts::11 113654 # Per bank write bursts +system.physmem.perBankWrBursts::12 105244 # Per bank write bursts +system.physmem.perBankWrBursts::13 111328 # Per bank write bursts +system.physmem.perBankWrBursts::14 115976 # Per bank write bursts +system.physmem.perBankWrBursts::15 113284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 614 # Number of times write queue was full causing retry -system.physmem.totGap 47345383810500 # Total gap between requests +system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry +system.physmem.totGap 47305564753000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) -system.physmem.readPktSize::4 21334 # Read request sizes (log2) +system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1105404 # Read request sizes (log2) +system.physmem.readPktSize::6 915273 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2037687 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 495851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 118863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 70028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1835350 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 429452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 211261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 35792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 27031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,140 +188,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 58821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 69578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 77864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 89177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 97306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 106336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 112038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 121912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 121861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 124135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 125483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 131449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 118558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 117002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 113440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 105060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 29238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 25813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 22998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 20720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 18797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 16980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 15279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 13444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 11652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 10311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 9180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 8124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 6654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 5145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 4249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 3131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1502 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1131657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.664737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.493979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 249.059793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 718344 63.48% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 219262 19.38% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56669 5.01% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25497 2.25% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20148 1.78% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11584 1.02% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9545 0.84% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8895 0.79% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61713 5.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1131657 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 74075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.207155 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.468886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 74072 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 25942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 42762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 67617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 70370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 78632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 77296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 79817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 88544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 102987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 87472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 82523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 74776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 5896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 74075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 74075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.441228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.793858 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 451.068024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1023 74039 99.95% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1024-2047 13 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2048-3071 9 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3072-4095 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4096-5119 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5120-6143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26624-27647 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33792-34815 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64512-65535 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 74075 # Writes before turning the bus around for reads -system.physmem.totQLat 56140564025 # Total ticks spent queuing -system.physmem.totMemAccLat 77261951525 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5632370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 49837.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads +system.physmem.totQLat 43948740923 # Total ticks spent queuing +system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68587.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 851046 # Number of row buffer hits during reads -system.physmem.writeRowHits 1176475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes -system.physmem.avgGap 14949293.37 # Average gap between requests -system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4318120800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2356117500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4401423000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6642421200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1163515422960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27386602512000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31660206295860 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.707358 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45559855793000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing +system.physmem.readRowHits 706637 # Number of row buffer hits during reads +system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes +system.physmem.avgGap 17049532.53 # Average gap between requests +system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.633528 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 204562609000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4237153200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2311938750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4385027400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6529429440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1165548686490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27384818947500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31660201461180 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.707256 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45556862760500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.622864 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 207555509500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -355,15 +351,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 145356452 # Number of BP lookups -system.cpu0.branchPred.condPredicted 96435082 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7088203 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 101789401 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67765064 # Number of BTB hits +system.cpu0.branchPred.lookups 136259129 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.573792 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20004195 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 205158 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -394,89 +390,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 580611 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 580611 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13679 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93135 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 259311 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 321300 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1669.368192 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 317448 98.80% 98.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 2037 0.63% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 845 0.26% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 576 0.18% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 232 0.07% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 45 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 42 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 321300 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 293805 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 291279 99.14% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1809 0.62% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 367 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 189 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 105 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 293805 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 521650035508 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.610400 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.526555 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 520697119508 99.82% 99.82% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 543124000 0.10% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 195186500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 85165500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 70245500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 34070500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 11934000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 12740000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 448500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 521650035508 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 93135 87.19% 87.19% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13679 12.81% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106814 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 580611 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 520196 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 580611 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106814 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 687425 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105404836 # DTB read hits -system.cpu0.dtb.read_misses 420652 # DTB read misses -system.cpu0.dtb.write_hits 86890500 # DTB write hits -system.cpu0.dtb.write_misses 159959 # DTB write misses +system.cpu0.dtb.read_hits 98496070 # DTB read hits +system.cpu0.dtb.read_misses 369414 # DTB read misses +system.cpu0.dtb.write_hits 81551465 # DTB write hits +system.cpu0.dtb.write_misses 150782 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40944 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 605 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8089 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40127 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105825488 # DTB read accesses -system.cpu0.dtb.write_accesses 87050459 # DTB write accesses +system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98865484 # DTB read accesses +system.cpu0.dtb.write_accesses 81702247 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 192295336 # DTB hits -system.cpu0.dtb.misses 580611 # DTB misses -system.cpu0.dtb.accesses 192875947 # DTB accesses +system.cpu0.dtb.hits 180047535 # DTB hits +system.cpu0.dtb.misses 520196 # DTB misses +system.cpu0.dtb.accesses 180567731 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,588 +498,584 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 84622 # Table walker walks requested -system.cpu0.itb.walker.walksLong 84622 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 994 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61729 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9515 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75107 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1146.297948 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8819.384812 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 74551 99.26% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 182 0.24% 99.50% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 223 0.30% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 112 0.15% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 5 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75107 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70635 97.78% 97.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1318 1.82% 99.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 148 0.20% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.11% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 81590 # Table walker walks requested +system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 405678068016 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.851697 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.355553 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 60184359568 14.84% 14.84% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 345473805948 85.16% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 18871000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1025500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 405678068016 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61729 98.42% 98.42% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 994 1.58% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 62723 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84622 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84622 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62723 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62723 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 147345 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 229226252 # ITB inst hits -system.cpu0.itb.inst_misses 84622 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 213929001 # ITB inst hits +system.cpu0.itb.inst_misses 81590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29308 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 225641 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 229310874 # ITB inst accesses -system.cpu0.itb.hits 229226252 # DTB hits -system.cpu0.itb.misses 84622 # DTB misses -system.cpu0.itb.accesses 229310874 # DTB accesses -system.cpu0.numCycles 787784387 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses +system.cpu0.itb.hits 213929001 # DTB hits +system.cpu0.itb.misses 81590 # DTB misses +system.cpu0.itb.accesses 214010591 # DTB accesses +system.cpu0.numCycles 728554790 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 93175923 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 642526185 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 145356452 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87769259 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 654798115 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15283958 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1702071 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 255624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6308926 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 745987 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 671334 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 229000663 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1782311 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27660 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 765299959 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.983676 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.220176 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 404626902 52.87% 52.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 139960190 18.29% 71.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 49291261 6.44% 77.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 171421606 22.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 765299959 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.184513 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.815612 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 110781464 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 368356745 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 241543971 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39160465 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5457314 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 20998766 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2230758 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 666506782 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 24554495 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5457314 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 147799214 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53385858 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 247347968 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 243020975 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 68288630 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 648373688 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6354822 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9340488 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 358878 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 691420 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31770877 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 13042 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 618836498 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1000163983 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 765756832 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 980941 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 557557100 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 61279388 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16104693 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13959035 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79116837 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 106280749 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90455195 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9698755 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8363084 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 625354037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16149817 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 628774014 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2896491 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54006760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 37569824 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 287316 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 765299959 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.821605 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.068919 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 51306825 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 423230722 55.30% 55.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 141522259 18.49% 73.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 122647115 16.03% 89.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 69647275 9.10% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8247243 1.08% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5342 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 765299959 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65414267 45.68% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 59912 0.04% 45.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 17829 0.01% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 19 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37349884 26.08% 71.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40363750 28.19% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 430163495 68.41% 68.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1578221 0.25% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 81407 0.01% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 125 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 78656 0.01% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 108646479 17.28% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88225631 14.03% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 628774014 # Type of FU issued -system.cpu0.iq.rate 0.798155 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 143205661 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227754 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2167577171 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 695106277 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 611404783 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1372966 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 554126 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 508083 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 771129089 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 850586 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2930031 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued +system.cpu0.iq.rate 0.806867 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 650811943 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 476069 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13213228 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17078 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 150900 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6091069 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2819130 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4221569 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5457314 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7826815 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 3783393 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 641629807 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 106280749 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90455195 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13677015 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 59030 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3651240 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 150900 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2214888 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3025224 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5240112 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 620548589 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105398618 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7653008 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 125953 # number of nop insts executed -system.cpu0.iew.exec_refs 192287971 # number of memory reference insts executed -system.cpu0.iew.exec_branches 117275797 # Number of branches executed -system.cpu0.iew.exec_stores 86889353 # Number of stores executed -system.cpu0.iew.exec_rate 0.787714 # Inst execution rate -system.cpu0.iew.wb_sent 612710943 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 611912866 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 297952907 # num instructions producing a value -system.cpu0.iew.wb_consumers 488842231 # num instructions consuming a value +system.cpu0.iew.exec_nop 115074 # number of nop insts executed +system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109604684 # Number of branches executed +system.cpu0.iew.exec_stores 81550489 # Number of stores executed +system.cpu0.iew.exec_rate 0.796169 # Inst execution rate +system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 278067639 # num instructions producing a value +system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.776752 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609507 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50177444 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15862501 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4903538 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 755787028 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.772749 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.571704 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 501065306 66.30% 66.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 130810768 17.31% 83.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 56911365 7.53% 91.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19253126 2.55% 93.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13929285 1.84% 95.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9339201 1.24% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6281388 0.83% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4033068 0.53% 98.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14163521 1.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 755787028 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 497564314 # Number of instructions committed -system.cpu0.commit.committedOps 584033993 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 464477894 # Number of instructions committed +system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 177431645 # Number of memory references committed -system.cpu0.commit.loads 93067519 # Number of loads committed -system.cpu0.commit.membars 3925399 # Number of memory barriers committed -system.cpu0.commit.branches 111370146 # Number of branches committed -system.cpu0.commit.fp_insts 496516 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 535821487 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14891305 # Number of function calls committed. +system.cpu0.commit.refs 165983876 # Number of memory references committed +system.cpu0.commit.loads 86857868 # Number of loads committed +system.cpu0.commit.membars 3594521 # Number of memory barriers committed +system.cpu0.commit.branches 103961213 # Number of branches committed +system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13758946 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 405157799 69.37% 69.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1311833 0.22% 69.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63039 0.01% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 69677 0.01% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 93067519 15.94% 85.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84364126 14.45% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 378032624 69.33% 69.33% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 584033993 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14163521 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1371348086 # The number of ROB reads -system.cpu0.rob.rob_writes 1277898548 # The number of ROB writes -system.cpu0.timesIdled 1050969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22484428 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93902986117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 497564314 # Number of Instructions Simulated -system.cpu0.committedOps 584033993 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.583282 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.583282 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.631600 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.631600 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 732616408 # number of integer regfile reads -system.cpu0.int_regfile_writes 435784003 # number of integer regfile writes -system.cpu0.fp_regfile_reads 812591 # number of floating regfile reads -system.cpu0.fp_regfile_writes 450624 # number of floating regfile writes -system.cpu0.cc_regfile_reads 135724425 # number of cc regfile reads -system.cpu0.cc_regfile_writes 136350840 # number of cc regfile writes -system.cpu0.misc_regfile_reads 3048491910 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15942846 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6332598 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.098749 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 164710199 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6333110 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.007791 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1750140500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.098749 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.945505 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.945505 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 368140426 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 368140426 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86285504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86285504 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73342402 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73342402 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 227851 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 227851 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 264480 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 264480 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878345 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1878345 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1911240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1911240 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 159627906 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 159627906 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 159855757 # number of overall hits -system.cpu0.dcache.overall_hits::total 159855757 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7088092 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7088092 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7774496 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7774496 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 746133 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 746133 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 842824 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 842824 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 281020 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 281020 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209055 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 209055 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14862588 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14862588 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15608721 # number of overall misses -system.cpu0.dcache.overall_misses::total 15608721 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 105859717159 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 137077029934 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 45622327717 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 45622327717 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4025426932 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4025426932 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4395434712 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4395434712 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3232000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3232000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 242936747093 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 242936747093 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 93373596 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 93373596 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81116898 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81116898 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 973984 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 973984 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1107304 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1107304 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2159365 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2159365 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2120295 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2120295 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 174490494 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 174490494 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 175464478 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 175464478 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075911 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075911 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095843 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.095843 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766063 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766063 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.761150 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.761150 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130140 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130140 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098597 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098597 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085177 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.085177 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088957 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088957 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134 # average StoreCondReq miss latency +system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads +system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes +system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 464477894 # Number of Instructions Simulated +system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.637533 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 684802624 # number of integer regfile reads +system.cpu0.int_regfile_writes 407591789 # number of integer regfile writes +system.cpu0.fp_regfile_reads 737398 # number of floating regfile reads +system.cpu0.fp_regfile_writes 323628 # number of floating regfile writes +system.cpu0.cc_regfile_reads 126081114 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126833812 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2842254449 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14406777 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 5807270 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.185727 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154700200 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5807781 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.636714 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1931738500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.185727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982785 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.982785 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 344453115 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 344453115 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80805507 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80805507 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69071717 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69071717 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209524 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 209524 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 255543 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 255543 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1772811 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1772811 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798532 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1798532 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 149877224 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149877224 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150086748 # number of overall hits +system.cpu0.dcache.overall_hits::total 150086748 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6456855 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6456855 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6956516 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 6956516 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 664764 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 664764 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 829133 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 829133 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 256042 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 256042 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194087 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 194087 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13413371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13413371 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14078135 # number of overall misses +system.cpu0.dcache.overall_misses::total 14078135 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92345367100 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 92345367100 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 122121346040 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 122121346040 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37689944158 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37689944158 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3513328512 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3513328512 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4123602814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4123602814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5259500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5259500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 214466713140 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 214466713140 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 214466713140 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 214466713140 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87262362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87262362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76028233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76028233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874288 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 874288 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1084676 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1084676 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2028853 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2028853 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1992619 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1992619 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 163290595 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 163290595 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164164883 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164164883 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073994 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.073994 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091499 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.091499 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760349 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760349 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.764406 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.764406 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.126200 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.126200 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097403 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097403 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082144 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.082144 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.085756 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14301.911240 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14301.911240 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17554.957976 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17554.957976 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 45457.054728 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 45457.054728 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13721.688286 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13721.688286 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21246.156693 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21246.156693 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 13488103 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19786702 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 752105 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 757651 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.933803 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 26.115853 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4276528 # number of writebacks -system.cpu0.dcache.writebacks::total 4276528 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664529 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3664529 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6233308 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6233308 # 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number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1541188 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 739665 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 739665 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 838083 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 838083 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139692 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139692 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209050 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 209050 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4964751 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4964751 # 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number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1737566757 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1737566757 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3967184288 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3967184288 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3082000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3082000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73477028091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 73477028091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90281694423 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 90281694423 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5575976491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5575976491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5325987989 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5325987989 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10901964480 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10901964480 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036665 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036665 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019000 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019000 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759422 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759422 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.756868 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.756868 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064691 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064691 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098595 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098595 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032510 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032510 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks +system.cpu0.dcache.writebacks::total 3967066 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3312893 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5560546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5560546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4546 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132684 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132684 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8873439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 8873439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8873439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 8873439 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3143962 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3143962 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1395970 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1395970 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 657971 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 657971 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 824587 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 824587 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194072 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194072 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4539932 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4539932 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5197903 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5197903 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41375173894 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41375173894 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26017592924 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26017592924 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14556234769 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14556234769 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36285250520 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36285250520 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1556312588 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1556312588 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3823478686 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3823478686 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5096000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5096000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67392766818 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 67392766818 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81949001587 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 81949001587 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5745168998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5745168998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5504162016 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5504162016 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11249331014 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11249331014 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036029 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036029 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018361 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018361 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752579 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752579 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.760215 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097395 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097395 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027803 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027803 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031663 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031663 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13160.201648 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18637.644737 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18637.644737 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22122.912361 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 44004.150587 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19701.341183 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # 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average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1095,461 +1083,462 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6368542 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.961816 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 222275153 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6369054 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.899241 # 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Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 464315009 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 464315009 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 222275153 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 222275153 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 222275153 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 222275153 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 222275153 # number of overall hits -system.cpu0.icache.overall_hits::total 222275153 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6697664 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6697664 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6697664 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6697664 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6697664 # number of overall misses -system.cpu0.icache.overall_misses::total 6697664 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70928372732 # 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number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029251 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029251 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029251 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029251 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029251 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029251 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10590.016569 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10590.016569 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8781241 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 821 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 708037 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.402235 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 74.636364 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 433467798 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 433467798 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 207290998 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 207290998 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 207290998 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 207290998 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 207290998 # number of overall hits +system.cpu0.icache.overall_hits::total 207290998 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6406823 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6406823 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6406823 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6406823 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6406823 # number of overall misses +system.cpu0.icache.overall_misses::total 6406823 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 67980327142 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 67980327142 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 67980327142 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 67980327142 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 67980327142 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 67980327142 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 213697821 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 213697821 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 213697821 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 213697821 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 213697821 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 213697821 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029981 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029981 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029981 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029981 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029981 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029981 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10610.614206 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10610.614206 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10610.614206 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10610.614206 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9344678 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 782 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 720412 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.971297 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 78.200000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 328289 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 328289 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 328289 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 328289 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 328289 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 328289 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6369375 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6369375 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6369375 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6369375 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6369375 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6369375 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 57966761800 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 57966761800 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 57966761800 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 57966761800 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 57966761800 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 57966761800 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699560248 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699560248 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027817 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9100.855547 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 334667 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 334667 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 334667 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 334667 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 334667 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 334667 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6072156 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6072156 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6072156 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6072156 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6072156 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6072156 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 58462486516 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 58462486516 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 58462486516 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 58462486516 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 58462486516 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 58462486516 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028415 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028415 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9627.961883 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8232125 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8569505 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 292099 # 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Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2067342500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7528.605833 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 71.466332 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.040507 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3487.680197 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4098.714387 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 925.047154 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.459510 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004362 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005557 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.212871 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.250166 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056460 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988925 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1513 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14421 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 709 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 196 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 537 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 818 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6042 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2879 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4513 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.092346 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.007385 # 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number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114761 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 114761 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36815 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36815 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991246 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 991246 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 582155 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182687 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5666433 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4176192 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10607467 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 582155 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182687 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5666433 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4176192 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10607467 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12607 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9261 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 702626 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1115482 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1839976 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 4 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 4 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 637762 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 637762 # 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number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 212101792 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2828322980 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2828322980 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3448129857 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3448129857 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3007000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3007000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16311576734 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16311576734 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 468497682 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 383886915 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20661944862 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 56054929527 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 77569258986 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 468497682 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 383886915 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20661944862 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 56054929527 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 77569258986 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 594762 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 191948 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6369059 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4300428 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11456197 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4276525 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4276525 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 836505 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 836505 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 252875 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 252875 # 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miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.762413 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.762413 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.546175 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.546175 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823890 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823890 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 993362 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2579397 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16158.447303 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 688 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5473 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2257 # 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mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824919 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824919 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207527 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207527 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.164920 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220782 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220782 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161046 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229475 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 496400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219706 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27494.820566 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26462.092491 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49836.623813 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48324.735965 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48324.735965 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20003.630551 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20003.630551 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14795.152488 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14795.152488 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 225131.473684 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 225131.473684 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40411.076926 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40411.076926 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28342.966722 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34081.682009 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1559,69 +1548,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 13921371 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11750633 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4276525 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1274288 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1162561 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 836505 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 509905 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 381643 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 535354 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 87 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1437620 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1309284 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12781022 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18390339 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414542 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294088 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 32879991 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407960480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 693234728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1535584 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4758096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1107488888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4767578 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 22911203 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.193957 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.395396 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18467409 80.60% 80.60% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 4443794 19.40% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22911203 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14408211332 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208870495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9596174213 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9165770534 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 223497560 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 700918244 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 124370032 # Number of BP lookups -system.cpu1.branchPred.condPredicted 83075187 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6189003 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87824878 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 56905034 # Number of BTB hits +system.cpu1.branchPred.lookups 124182653 # Number of BP lookups +system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.793752 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16687776 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 168367 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1651,90 +1638,81 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 538943 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 538943 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11373 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87574 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 237839 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 301104 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1852.353340 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 297190 98.70% 98.70% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2030 0.67% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 795 0.26% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 637 0.21% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 257 0.09% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 66 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 39 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 48 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 301104 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 268131 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 265367 98.97% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1941 0.72% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 396 0.15% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 232 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 106 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 37 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 534049 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 268131 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 435751861088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.614829 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.532518 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 434859464588 99.80% 99.80% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 474800000 0.11% 99.90% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 202701000 0.05% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 89682000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 62866500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 34103000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 13310500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 14713000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 214000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 435751861088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 87574 88.51% 88.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11373 11.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 98947 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 538943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 538943 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98947 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98947 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 637890 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91392867 # DTB read hits -system.cpu1.dtb.read_misses 373745 # DTB read misses -system.cpu1.dtb.write_hits 75805429 # DTB write hits -system.cpu1.dtb.write_misses 165198 # DTB write misses +system.cpu1.dtb.read_hits 91849877 # DTB read hits +system.cpu1.dtb.read_misses 382442 # DTB read misses +system.cpu1.dtb.write_hits 75119650 # DTB write hits +system.cpu1.dtb.write_misses 151607 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37451 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5879 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 40297 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91766612 # DTB read accesses -system.cpu1.dtb.write_accesses 75970627 # DTB write accesses +system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92232319 # DTB read accesses +system.cpu1.dtb.write_accesses 75271257 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 167198296 # DTB hits -system.cpu1.dtb.misses 538943 # DTB misses -system.cpu1.dtb.accesses 167737239 # DTB accesses +system.cpu1.dtb.hits 166969527 # DTB hits +system.cpu1.dtb.misses 534049 # DTB misses +system.cpu1.dtb.accesses 167503576 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1764,587 +1742,589 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 85244 # Table walker walks requested -system.cpu1.itb.walker.walksLong 85244 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 675 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61262 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9941 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 75303 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1139.330438 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8399.837182 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 74771 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 180 0.24% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 193 0.26% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 128 0.17% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 12 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75303 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71878 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70231 97.71% 97.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1324 1.84% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 179 0.25% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 46 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 85651 # Table walker walks requested +system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71878 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 397094361424 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.878531 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.326828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 48253813024 12.15% 12.15% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 348822790900 87.84% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 16535000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1219500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 397094361424 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61262 98.91% 98.91% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 675 1.09% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61937 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85244 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61937 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61937 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 147181 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 196146030 # ITB inst hits -system.cpu1.itb.inst_misses 85244 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 196330607 # ITB inst hits +system.cpu1.itb.inst_misses 85651 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26780 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 213163 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 196231274 # ITB inst accesses -system.cpu1.itb.hits 196146030 # DTB hits -system.cpu1.itb.misses 85244 # DTB misses -system.cpu1.itb.accesses 196231274 # DTB accesses -system.cpu1.numCycles 664388878 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses +system.cpu1.itb.hits 196330607 # DTB hits +system.cpu1.itb.misses 85651 # DTB misses +system.cpu1.itb.accesses 196416258 # DTB accesses +system.cpu1.numCycles 659201565 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 79880322 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 552169788 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 124370032 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 73592810 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 551328487 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13340182 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1707326 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 246511 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6080767 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 727313 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 602439 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 195911596 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1586691 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647243256 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.003235 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.226187 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 336573756 52.00% 52.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 120960986 18.69% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 40749741 6.30% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 148958773 23.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647243256 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.187195 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.831094 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 96356177 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 306396299 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 204571849 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 35206357 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4712574 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17589142 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1996203 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 573391383 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21361954 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4712574 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 129172911 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 40460241 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 212107385 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 206565063 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 54225082 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 557977037 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5352379 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8193976 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 222351 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 303036 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 21276416 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 13923 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 530659712 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 862978619 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 659902858 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 766208 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 478267677 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52392029 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15246817 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13453544 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 71065053 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 91863812 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78915989 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8629555 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7664780 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 536633802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15513444 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 541699362 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2485495 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 46695905 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 31776612 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 271399 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647243256 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.836933 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.069144 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 46992661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 349912497 54.06% 54.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 127097301 19.64% 73.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 103346931 15.97% 89.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 59640858 9.21% 98.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7242720 1.12% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2949 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647243256 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 54464030 43.99% 43.99% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 55578 0.04% 44.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 15828 0.01% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 9 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33234382 26.84% 70.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36043585 29.11% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 369233279 68.16% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1193564 0.22% 68.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69127 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 46847 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94164053 17.38% 85.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76992429 14.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 541699362 # Type of FU issued -system.cpu1.iq.rate 0.815335 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 123813412 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.228565 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1855831634 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 598546046 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 526634223 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1109251 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 439129 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 408402 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 664822270 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 690492 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2431611 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued +system.cpu1.iq.rate 0.818910 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 597058317 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 514947 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11396985 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16347 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 143339 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5491640 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2526857 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3486247 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4712574 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5829545 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1427417 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 552265728 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 91863812 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78915989 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13236985 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 56254 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1314129 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 143339 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1858186 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2653609 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4511795 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 534690067 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 91388435 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6481283 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 118482 # number of nop insts executed -system.cpu1.iew.exec_refs 167194328 # number of memory reference insts executed -system.cpu1.iew.exec_branches 100087893 # Number of branches executed -system.cpu1.iew.exec_stores 75805893 # Number of stores executed -system.cpu1.iew.exec_rate 0.804785 # Inst execution rate -system.cpu1.iew.wb_sent 527704335 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 527042625 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 254576573 # num instructions producing a value -system.cpu1.iew.wb_consumers 416898701 # num instructions consuming a value +system.cpu1.iew.exec_nop 123079 # number of nop insts executed +system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed +system.cpu1.iew.exec_branches 99765376 # Number of branches executed +system.cpu1.iew.exec_stores 75118031 # Number of stores executed +system.cpu1.iew.exec_rate 0.808170 # Inst execution rate +system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 254712512 # num instructions producing a value +system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.793274 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610644 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43642021 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15242045 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4231486 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 638973832 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.786200 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.579868 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 417556945 65.35% 65.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 116379063 18.21% 83.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 48152991 7.54% 91.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16068254 2.51% 93.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11811974 1.85% 95.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7886914 1.23% 96.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5403679 0.85% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3345009 0.52% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12369003 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 638973832 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 426124677 # Number of instructions committed -system.cpu1.commit.committedOps 502361434 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 424719097 # Number of instructions committed +system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 153891175 # Number of memory references committed -system.cpu1.commit.loads 80466826 # Number of loads committed -system.cpu1.commit.membars 3635433 # Number of memory barriers committed -system.cpu1.commit.branches 94895008 # Number of branches committed -system.cpu1.commit.fp_insts 399904 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 461321486 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12405087 # Number of function calls committed. +system.cpu1.commit.refs 153560878 # Number of memory references committed +system.cpu1.commit.loads 80761178 # Number of loads committed +system.cpu1.commit.membars 3652883 # Number of memory barriers committed +system.cpu1.commit.branches 94624372 # Number of branches committed +system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12685398 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 347396188 69.15% 69.15% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 977319 0.19% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55389 0.01% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 41321 0.01% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 80466826 16.02% 85.38% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 73424349 14.62% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 502361434 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12369003 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1168820475 # The number of ROB reads -system.cpu1.rob.rob_writes 1100237743 # The number of ROB writes -system.cpu1.timesIdled 913492 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 17145622 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94026381638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 426124677 # Number of Instructions Simulated -system.cpu1.committedOps 502361434 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.559142 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.559142 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.641378 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.641378 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 632226075 # number of integer regfile reads -system.cpu1.int_regfile_writes 374528717 # number of integer regfile writes -system.cpu1.fp_regfile_reads 661926 # number of floating regfile reads -system.cpu1.fp_regfile_writes 331836 # number of floating regfile writes -system.cpu1.cc_regfile_reads 114587184 # number of cc regfile reads -system.cpu1.cc_regfile_writes 115385602 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2619636946 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15333141 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5236220 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.332610 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 143091306 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5236730 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.324553 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8478701081000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.332610 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893228 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.893228 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 319394188 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 319394188 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 74655263 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74655263 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64023189 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64023189 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 163779 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 163779 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 39797 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 39797 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1738928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1738928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1751406 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1751406 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138678452 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138678452 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138842231 # number of overall hits -system.cpu1.dcache.overall_hits::total 138842231 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6126939 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6126939 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6982821 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6982821 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 659533 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 659533 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 425377 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 425377 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 260578 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 260578 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204152 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 204152 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13109760 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13109760 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13769293 # number of overall misses -system.cpu1.dcache.overall_misses::total 13769293 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92549514245 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 92549514245 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 116311286360 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11708163921 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11708163921 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3758503444 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3758503444 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4320848660 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4320848660 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3489000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3489000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 208860800605 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 208860800605 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 80782202 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 80782202 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71006010 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71006010 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823312 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 823312 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 465174 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 465174 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1999506 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1999506 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1955558 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1955558 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 151788212 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 151788212 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 152611524 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 152611524 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075845 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.075845 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098341 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.098341 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801073 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801073 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.914447 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.914447 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130321 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130321 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104396 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104396 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086369 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.086369 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090224 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.090224 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads +system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes +system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 424719097 # Number of Instructions Simulated +system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads +system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes +system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads +system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes +system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads +system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5151228 # number of replacements +system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 63737585 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits +system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195781 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 12732138 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13362314 # number of overall misses +system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 117804291686 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13004978477 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4150746008 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 205130711833 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799987 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1879220 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 151625684 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 152425671 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083971 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087664 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21200.964384 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2855420 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17544431 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 337066 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 700468 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.471397 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 25.046727 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3392584 # number of writebacks -system.cpu1.dcache.writebacks::total 3392584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3127909 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3127909 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5647115 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5647115 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3296 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3296 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132105 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132105 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8775024 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8775024 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8775024 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8775024 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2999030 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2999030 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335706 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1335706 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659449 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 659449 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 422081 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 422081 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 128473 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 128473 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204145 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 204145 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4334736 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4334736 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4994185 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4994185 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38225367292 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38225367292 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21845579142 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21845579142 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15240654080 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15240654080 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10753431338 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10753431338 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1629520255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1629520255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3904363340 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3904363340 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3325000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3325000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60070946434 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 60070946434 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75311600514 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 75311600514 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 796916503 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 796916503 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 897774501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 897774501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1694691004 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1694691004 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037125 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037125 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018811 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018811 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800971 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800971 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.907362 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.907362 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064252 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064252 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104392 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104392 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028558 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028558 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032725 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032725 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks +system.cpu1.dcache.writebacks::total 3264704 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # 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mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # 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average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10273.874329 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8139519 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 675212 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.236665 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 39 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.054761 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 288337 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 288337 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 288337 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 288337 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 288337 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 288337 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5522944 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5522944 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5522944 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5522944 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5522944 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5522944 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50254087338 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 50254087338 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50254087338 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 50254087338 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50254087338 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 50254087338 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5802498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5802498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5802498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5802498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028192 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028192 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9099.148450 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311064 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 311064 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 311064 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 311064 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5668523 # 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number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 52921398555 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6131248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # 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average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7021877 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7194867 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 149461 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 884477 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 867.986079 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.336610 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004965 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005350 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.235263 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.190756 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052978 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.825921 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1495 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14476 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2136964 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 465 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 510 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 477 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1150 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5680 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4086 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3438 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.091248 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883545 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 250860566 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 250860566 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 536921 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182584 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4917912 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781477 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8418894 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3392565 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3392565 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 191757 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 191757 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71744 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 71744 # 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number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 241449363 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2956550746 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2956550746 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3438458831 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3438458831 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3243000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3243000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10870225593 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10870225593 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 492758189 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 83729362095 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 639050750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 644653500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 738464498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 738464498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1377515248 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1383117998 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256480 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.155504 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.544047 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.544047 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.669881 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.669881 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845860 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.845860 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.599313 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.599313 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.678857 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.678857 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825419 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825419 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211837 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211837 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.166458 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210117 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210117 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.160804 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.229614 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222054 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26055.301051 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24665.159580 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.847871 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33685.706333 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33685.706333 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19753.023167 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19753.023167 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 257666.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25897.791789 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33559.952085 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2816,66 +2793,64 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12802922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10291743 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3392582 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1076196 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1156933 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 420701 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 464615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 376292 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 486818 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1296360 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1132878 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11046012 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15089863 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 415115 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1210522 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27761512 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353468736 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 564735319 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1532736 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4394080 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 924130871 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5316111 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 20559073 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.243524 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.429209 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15552442 75.65% 75.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 5006631 24.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20559073 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11602796673 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182870488 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8299279905 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7848510644 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 224378946 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 662954125 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40399 # Transaction distribution -system.iobus.trans_dist::ReadResp 40399 # Transaction distribution -system.iobus.trans_dist::WriteReq 136785 # Transaction distribution -system.iobus.trans_dist::WriteResp 30057 # Transaction distribution +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution +system.iobus.trans_dist::WriteReq 136633 # Transaction distribution +system.iobus.trans_dist::WriteResp 29905 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47726 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2885,18 +2860,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48174 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2906,18 +2881,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156195 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497097 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36604000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2937,7 +2912,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2945,71 +2920,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043087367 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93034000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179187461 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115604 # number of replacements -system.iocache.tags.tagsinuse 11.301402 # Cycle average of tags in use +system.iocache.tags.replacements 115568 # number of replacements +system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9117040369000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.419209 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.882193 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463701 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242637 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706338 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040757 # Number of tag accesses -system.iocache.tags.data_accesses 1040757 # Number of data accesses +system.iocache.tags.tag_accesses 1040640 # Number of tag accesses +system.iocache.tags.data_accesses 1040640 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses -system.iocache.demand_misses::total 8912 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses +system.iocache.demand_misses::total 8899 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8872 # number of overall misses -system.iocache.overall_misses::total 8912 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1954318592 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1960025592 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28939092314 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28939092314 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1954318592 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1960382592 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1954318592 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1960382592 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8859 # number of overall misses +system.iocache.overall_misses::total 8899 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3023,55 +2998,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220005.117522 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219971.116697 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219971.116697 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228427 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184548.172941 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184548.172941 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 112586 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16234 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.295878 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.935198 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8859 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8859 # 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number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1178344651 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3085,562 +3060,567 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132617.806863 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132433.863647 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134124.688573 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134124.688573 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1613331 # number of replacements -system.l2c.tags.tagsinuse 64339.343113 # Cycle average of tags in use -system.l2c.tags.total_refs 4797018 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1673818 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.865914 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3243842500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19101.398352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.742619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 228.186438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3981.341018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11353.199987 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.349370 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 266.651363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3248.685748 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4974.329517 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9177.250333 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.291464 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.060750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.173236 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.075902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.981740 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10683 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49559 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 995 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9444 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3090 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42149 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163010 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.756210 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 64781750 # Number of tag accesses -system.l2c.tags.data_accesses 64781750 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6508 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4319 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 640995 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 651108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 307248 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6236 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4043 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 550704 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 545723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 278481 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2995365 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2564009 # number of Writeback hits -system.l2c.Writeback_hits::total 2564009 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 138658 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 123170 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 261828 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 30955 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32781 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 63736 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6525 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5847 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12372 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 54058 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53543 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107601 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6508 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 640995 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 705166 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 307248 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4043 # 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number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 252797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 315511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2810 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2444 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 54313 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 182987 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 226783 # number of demand (read+write) misses -system.l2c.demand_misses::total 1104077 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2518 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2288 # number of overall misses -system.l2c.overall_misses::cpu0.inst 61626 # number of overall misses -system.l2c.overall_misses::cpu0.data 252797 # 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Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1437791 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.127126 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3245891000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17415.702003 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.555673 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 13.071281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4037.254225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5874.753333 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3721.003209 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 357.239386 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 523.990627 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2776.282665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11847.144423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17848.477746 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.265743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000199 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.089642 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.056778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.007995 # 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Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2371 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42888 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.157471 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.759247 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 59850638 # Number of tag accesses +system.l2c.tags.data_accesses 59850638 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5089 # 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mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.548649 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.236645 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.236645 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 85881.831473 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83462.927180 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 109172.214092 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39770.223840 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32925.810283 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38295.304891 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.312265 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.788603 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17832.963641 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17782.215985 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.660979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17792.847192 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79892.229254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77613.909784 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78962.043055 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3655,57 +3635,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1032278 # Transaction distribution -system.membus.trans_dist::ReadResp 1032278 # Transaction distribution -system.membus.trans_dist::WriteReq 38581 # Transaction distribution -system.membus.trans_dist::WriteResp 38581 # Transaction distribution -system.membus.trans_dist::Writeback 1347712 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 689975 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 689975 # Transaction distribution -system.membus.trans_dist::UpgradeReq 447979 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 332386 # Transaction distribution -system.membus.trans_dist::UpgradeResp 121150 # Transaction distribution -system.membus.trans_dist::ReadExReq 152231 # Transaction distribution -system.membus.trans_dist::ReadExResp 135895 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123088 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 855568 # Transaction distribution +system.membus.trans_dist::ReadResp 855568 # Transaction distribution +system.membus.trans_dist::WriteReq 38542 # Transaction distribution +system.membus.trans_dist::WriteResp 38542 # Transaction distribution +system.membus.trans_dist::Writeback 1173701 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution +system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.membus.trans_dist::ReadExReq 139893 # Transaction distribution +system.membus.trans_dist::ReadExResp 122444 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25972 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5571157 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5720295 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6056198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156195 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 187423448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 187632159 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14096832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 201728991 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 678374 # Total snoops (count) -system.membus.snoop_fanout::samples 3943213 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 651055 # Total snoops (count) +system.membus.snoop_fanout::samples 3600660 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3943213 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3943213 # Request fanout histogram -system.membus.reqLayer0.occupancy 98700492 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3600660 # Request fanout histogram +system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21600991 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 19952700228 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 11115498245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187180539 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3749,49 +3730,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4932840 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4925609 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38581 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38581 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2564009 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 955023 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 848293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 504313 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 344758 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 849071 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 157 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 306644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 306644 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8600677 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6275419 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14876096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 289885704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198430935 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 488316639 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1740265 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9550575 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012108 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109370 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1675443 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9434933 98.79% 98.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115642 1.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9550575 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18722164156 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7552500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 13115425494 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 11201753623 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13602 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5345 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 48ca1dfde..6f7d21c4e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320647 # Number of seconds simulated -sim_ticks 51320647066500 # Number of ticks simulated -final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320469 # Number of seconds simulated +sim_ticks 51320468905000 # Number of ticks simulated +final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114690 # Simulator instruction rate (inst/s) -host_op_rate 134762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6864170011 # Simulator tick rate (ticks/s) -host_mem_usage 721888 # Number of bytes of host memory used -host_seconds 7476.60 # Real time elapsed on the host -sim_insts 857487967 # Number of instructions simulated -sim_ops 1007562352 # Number of ops (including micro ops) simulated +host_inst_rate 114377 # Simulator instruction rate (inst/s) +host_op_rate 134391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6861255780 # Simulator tick rate (ticks/s) +host_mem_usage 720736 # Number of bytes of host memory used +host_seconds 7479.75 # Real time elapsed on the host +sim_insts 855512158 # Number of instructions simulated +sim_ops 1005211605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory -system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory +system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 791544 # Number of read requests accepted -system.physmem.writeReqs 1694292 # Number of write requests accepted -system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue -system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 48315 # Per bank write bursts -system.physmem.perBankRdBursts::1 50150 # Per bank write bursts -system.physmem.perBankRdBursts::2 46175 # Per bank write bursts -system.physmem.perBankRdBursts::3 46946 # Per bank write bursts -system.physmem.perBankRdBursts::4 45323 # Per bank write bursts -system.physmem.perBankRdBursts::5 52981 # Per bank write bursts -system.physmem.perBankRdBursts::6 47646 # Per bank write bursts -system.physmem.perBankRdBursts::7 48748 # Per bank write bursts -system.physmem.perBankRdBursts::8 44337 # Per bank write bursts -system.physmem.perBankRdBursts::9 72322 # Per bank write bursts -system.physmem.perBankRdBursts::10 50834 # Per bank write bursts -system.physmem.perBankRdBursts::11 50772 # Per bank write bursts -system.physmem.perBankRdBursts::12 48451 # Per bank write bursts -system.physmem.perBankRdBursts::13 47387 # Per bank write bursts -system.physmem.perBankRdBursts::14 44232 # Per bank write bursts -system.physmem.perBankRdBursts::15 46363 # Per bank write bursts -system.physmem.perBankWrBursts::0 103979 # Per bank write bursts -system.physmem.perBankWrBursts::1 105038 # Per bank write bursts -system.physmem.perBankWrBursts::2 105754 # Per bank write bursts -system.physmem.perBankWrBursts::3 105161 # Per bank write bursts -system.physmem.perBankWrBursts::4 103562 # Per bank write bursts -system.physmem.perBankWrBursts::5 108435 # Per bank write bursts -system.physmem.perBankWrBursts::6 103867 # Per bank write bursts -system.physmem.perBankWrBursts::7 105467 # Per bank write bursts -system.physmem.perBankWrBursts::8 102645 # Per bank write bursts -system.physmem.perBankWrBursts::9 108407 # Per bank write bursts -system.physmem.perBankWrBursts::10 108582 # Per bank write bursts -system.physmem.perBankWrBursts::11 107982 # Per bank write bursts -system.physmem.perBankWrBursts::12 105330 # Per bank write bursts -system.physmem.perBankWrBursts::13 105345 # Per bank write bursts -system.physmem.perBankWrBursts::14 103911 # Per bank write bursts -system.physmem.perBankWrBursts::15 104029 # Per bank write bursts +system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 784654 # Number of read requests accepted +system.physmem.writeReqs 1688539 # Number of write requests accepted +system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue +system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 46664 # Per bank write bursts +system.physmem.perBankRdBursts::1 51485 # Per bank write bursts +system.physmem.perBankRdBursts::2 48018 # Per bank write bursts +system.physmem.perBankRdBursts::3 46409 # Per bank write bursts +system.physmem.perBankRdBursts::4 44064 # Per bank write bursts +system.physmem.perBankRdBursts::5 51949 # Per bank write bursts +system.physmem.perBankRdBursts::6 45895 # Per bank write bursts +system.physmem.perBankRdBursts::7 48923 # Per bank write bursts +system.physmem.perBankRdBursts::8 45299 # Per bank write bursts +system.physmem.perBankRdBursts::9 70789 # Per bank write bursts +system.physmem.perBankRdBursts::10 48156 # Per bank write bursts +system.physmem.perBankRdBursts::11 46739 # Per bank write bursts +system.physmem.perBankRdBursts::12 48771 # Per bank write bursts +system.physmem.perBankRdBursts::13 48997 # Per bank write bursts +system.physmem.perBankRdBursts::14 45133 # Per bank write bursts +system.physmem.perBankRdBursts::15 46835 # Per bank write bursts +system.physmem.perBankWrBursts::0 99610 # Per bank write bursts +system.physmem.perBankWrBursts::1 104326 # Per bank write bursts +system.physmem.perBankWrBursts::2 103481 # Per bank write bursts +system.physmem.perBankWrBursts::3 102430 # Per bank write bursts +system.physmem.perBankWrBursts::4 101747 # Per bank write bursts +system.physmem.perBankWrBursts::5 104971 # Per bank write bursts +system.physmem.perBankWrBursts::6 100056 # Per bank write bursts +system.physmem.perBankWrBursts::7 103888 # Per bank write bursts +system.physmem.perBankWrBursts::8 99840 # Per bank write bursts +system.physmem.perBankWrBursts::9 106110 # Per bank write bursts +system.physmem.perBankWrBursts::10 102643 # Per bank write bursts +system.physmem.perBankWrBursts::11 100858 # Per bank write bursts +system.physmem.perBankWrBursts::12 103355 # Per bank write bursts +system.physmem.perBankWrBursts::13 103593 # Per bank write bursts +system.physmem.perBankWrBursts::14 100350 # Per bank write bursts +system.physmem.perBankWrBursts::15 101960 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51320645833500 # Total gap between requests +system.physmem.numWrRetry 560 # Number of times write queue was full causing retry +system.physmem.totGap 51320467654000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 770259 # Read request sizes (log2) +system.physmem.readPktSize::6 763369 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1691719 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1685966 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,163 +159,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads -system.physmem.totQLat 15484448260 # Total ticks spent queuing -system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads +system.physmem.totQLat 15388206863 # Total ticks spent queuing +system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing -system.physmem.readRowHits 603455 # Number of row buffer hits during reads -system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 20645225.93 # Average gap between requests -system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.473889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing +system.physmem.readRowHits 598254 # Number of row buffer hits during reads +system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes +system.physmem.avgGap 20750692.59 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.470318 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.480369 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.479291 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states +system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -339,15 +336,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226505876 # Number of BP lookups -system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits +system.cpu.branchPred.lookups 226088242 # Number of BP lookups +system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,87 +375,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 931379 # Table walker walks requested -system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 945525 # Table walker walks requested +system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 171278986 # DTB read hits -system.cpu.dtb.read_misses 671795 # DTB read misses -system.cpu.dtb.write_hits 149102166 # DTB write hits -system.cpu.dtb.write_misses 259584 # DTB write misses +system.cpu.dtb.read_hits 170900022 # DTB read hits +system.cpu.dtb.read_misses 675244 # DTB read misses +system.cpu.dtb.write_hits 148749524 # DTB write hits +system.cpu.dtb.write_misses 270281 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171950781 # DTB read accesses -system.cpu.dtb.write_accesses 149361750 # DTB write accesses +system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171575266 # DTB read accesses +system.cpu.dtb.write_accesses 149019805 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320381152 # DTB hits -system.cpu.dtb.misses 931379 # DTB misses -system.cpu.dtb.accesses 321312531 # DTB accesses +system.cpu.dtb.hits 319649546 # DTB hits +system.cpu.dtb.misses 945525 # DTB misses +system.cpu.dtb.accesses 320595071 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,214 +484,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161841 # Table walker walks requested -system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161869 # Table walker walks requested +system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 360168043 # ITB inst hits -system.cpu.itb.inst_misses 161841 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 359459512 # ITB inst hits +system.cpu.itb.inst_misses 161869 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 360329884 # ITB inst accesses -system.cpu.itb.hits 360168043 # DTB hits -system.cpu.itb.misses 161841 # DTB misses -system.cpu.itb.accesses 360329884 # DTB accesses -system.cpu.numCycles 1576983833 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 359621381 # ITB inst accesses +system.cpu.itb.hits 359459512 # DTB hits +system.cpu.itb.misses 161869 # DTB misses +system.cpu.itb.accesses 359621381 # DTB accesses +system.cpu.numCycles 1580751099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -717,102 +708,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued -system.cpu.iq.rate 0.670005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued +system.cpu.iq.rate 0.666896 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224348 # number of nop insts executed -system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed -system.cpu.iew.exec_branches 198404489 # Number of branches executed -system.cpu.iew.exec_stores 149099070 # Number of stores executed -system.cpu.iew.exec_rate 0.662897 # Inst execution rate -system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back -system.cpu.iew.wb_producers 442335874 # num instructions producing a value -system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value +system.cpu.iew.exec_nop 222943 # number of nop insts executed +system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed +system.cpu.iew.exec_branches 197926826 # Number of branches executed +system.cpu.iew.exec_stores 148745526 # Number of stores executed +system.cpu.iew.exec_rate 0.659804 # Inst execution rate +system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back +system.cpu.iew.wb_producers 441278048 # num instructions producing a value +system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back +system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle -system.cpu.commit.committedInsts 857487967 # Number of instructions committed -system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle +system.cpu.commit.committedInsts 855512158 # Number of instructions committed +system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307720812 # Number of memory references committed -system.cpu.commit.loads 161382253 # Number of loads committed -system.cpu.commit.membars 7017472 # Number of memory barriers committed -system.cpu.commit.branches 191417503 # Number of branches committed -system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. -system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. -system.cpu.commit.function_calls 25509836 # Number of function calls committed. +system.cpu.commit.refs 307009160 # Number of memory references committed +system.cpu.commit.loads 161022390 # Number of loads committed +system.cpu.commit.membars 6998413 # Number of memory barriers committed +system.cpu.commit.branches 190975004 # Number of branches committed +system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions. +system.cpu.commit.int_insts 923410198 # Number of committed integer instructions. +system.cpu.commit.function_calls 25456304 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -835,236 +826,236 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction -system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction +system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2555751551 # The number of ROB reads -system.cpu.rob.rob_writes 2129995502 # The number of ROB writes -system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 857487967 # Number of Instructions Simulated -system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads -system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads -system.cpu.int_regfile_writes 738733043 # number of integer regfile writes -system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads -system.cpu.fp_regfile_writes 782548 # number of floating regfile writes -system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads -system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes -system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads -system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9822587 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 2555711925 # The number of ROB reads +system.cpu.rob.rob_writes 2125474325 # The number of ROB writes +system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 855512158 # Number of Instructions Simulated +system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads +system.cpu.int_regfile_writes 737118708 # number of integer regfile writes +system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads +system.cpu.fp_regfile_writes 784484 # number of floating regfile writes +system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads +system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes +system.cpu.misc_regfile_reads 5246257758 # number of misc regfile reads +system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9794555 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits -system.cpu.dcache.overall_hits::total 278710234 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses -system.cpu.dcache.overall_misses::total 22162626 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits +system.cpu.dcache.overall_hits::total 278057664 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # 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number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7597183 # 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number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # 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mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # 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average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks +system.cpu.dcache.writebacks::total 7577660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,277 +1063,276 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15084162 # number of replacements -system.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15070815 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374842526 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 343955623 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 343955623 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 343955623 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 343955623 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 343955623 # number of overall hits -system.cpu.icache.overall_hits::total 343955623 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15802123 # 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average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1166252 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65308.801684 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29080427 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1229042 # 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Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22418684 # 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mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1468,62 +1458,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 606880 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003347 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 583028 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 34397489 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115519 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40381 # Transaction distribution -system.iobus.trans_dist::ReadResp 40381 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40283 # Transaction distribution +system.iobus.trans_dist::ReadResp 40283 # Transaction distribution +system.iobus.trans_dist::WriteReq 136558 # Transaction distribution +system.iobus.trans_dist::WriteResp 29894 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1533,18 +1521,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1554,18 +1542,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1585,7 +1573,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1593,71 +1581,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115461 # number of replacements -system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use +system.iocache.tags.replacements 115456 # number of replacements +system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses -system.iocache.demand_misses::total 8855 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses +system.iocache.demand_misses::total 8851 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8815 # number of overall misses -system.iocache.overall_misses::total 8855 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # 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number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1671,55 +1659,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1733,71 +1721,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 411277 # Transaction distribution -system.membus.trans_dist::ReadResp 411277 # Transaction distribution -system.membus.trans_dist::WriteReq 33858 # Transaction distribution -system.membus.trans_dist::WriteResp 33858 # Transaction distribution -system.membus.trans_dist::Writeback 1089351 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution -system.membus.trans_dist::ReadExReq 417183 # Transaction distribution -system.membus.trans_dist::ReadExResp 417183 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 408284 # Transaction distribution +system.membus.trans_dist::ReadResp 408284 # Transaction distribution +system.membus.trans_dist::WriteReq 33682 # Transaction distribution +system.membus.trans_dist::WriteResp 33682 # Transaction distribution +system.membus.trans_dist::Writeback 1083893 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution +system.membus.trans_dist::ReadExReq 413056 # Transaction distribution +system.membus.trans_dist::ReadExResp 413056 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3154 # Total snoops (count) -system.membus.snoop_fanout::samples 2500418 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3023 # Total snoops (count) +system.membus.snoop_fanout::samples 2488136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2500418 # Request fanout histogram -system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2488136 # Request fanout histogram +system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1842,6 +1830,6 @@ system.realview.ethernet.coalescedTotal 0 # av system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index e7103dcb2..8e7b17b1a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.234984 # Number of seconds simulated -sim_ticks 51234983764500 # Number of ticks simulated -final_tick 51234983764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.274696 # Number of seconds simulated +sim_ticks 51274696167500 # Number of ticks simulated +final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293597 # Simulator instruction rate (inst/s) -host_op_rate 345003 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16999127000 # Simulator tick rate (ticks/s) -host_mem_usage 723216 # Number of bytes of host memory used -host_seconds 3013.98 # Real time elapsed on the host -sim_insts 884896163 # Number of instructions simulated -sim_ops 1039832130 # Number of ops (including micro ops) simulated +host_inst_rate 298693 # Simulator instruction rate (inst/s) +host_op_rate 350975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17280969451 # Simulator tick rate (ticks/s) +host_mem_usage 723560 # Number of bytes of host memory used +host_seconds 2967.12 # Real time elapsed on the host +sim_insts 886256415 # Number of instructions simulated +sim_ops 1041383802 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 129856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 125184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2903796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24969352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 34560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 29888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 811648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7348736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 94656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 89280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2169408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 17774080 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413120 # Number of bytes read from this memory -system.physmem.bytes_read::total 56893564 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2903796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 811648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2169408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5884852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77105472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 116160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 120000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2956980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25219400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 40192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 37376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 753536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7117376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 92544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 94080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2191808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 17867136 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430080 # Number of bytes read from this memory +system.physmem.bytes_read::total 57036668 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2956980 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 753536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2191808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5902324 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77190720 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77126052 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 390159 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 114824 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 33897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 277720 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 929382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1204773 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77211300 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1875 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 394066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 584 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 111209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 34247 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 279174 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6720 # Number of read requests responded to by this memory +system.physmem.num_reads::total 931618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1206105 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1207346 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 56676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 487350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 15842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 143432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 346913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1110444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 56676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 15842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42342 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 114860 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1504938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1505340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1504938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 56676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 487751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 15842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 143432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 346913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2615783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443127 # Number of read requests accepted -system.physmem.writeReqs 607625 # Number of write requests accepted -system.physmem.readBursts 443127 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 607625 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28344960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15168 # Total number of bytes read from write queue -system.physmem.bytesWritten 38801344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28360128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 38888000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 237 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1354 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18550 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25211 # Per bank write bursts -system.physmem.perBankRdBursts::1 29295 # Per bank write bursts -system.physmem.perBankRdBursts::2 27890 # Per bank write bursts -system.physmem.perBankRdBursts::3 27887 # Per bank write bursts -system.physmem.perBankRdBursts::4 27824 # Per bank write bursts -system.physmem.perBankRdBursts::5 30839 # Per bank write bursts -system.physmem.perBankRdBursts::6 26245 # Per bank write bursts -system.physmem.perBankRdBursts::7 26732 # Per bank write bursts -system.physmem.perBankRdBursts::8 26610 # Per bank write bursts -system.physmem.perBankRdBursts::9 29578 # Per bank write bursts -system.physmem.perBankRdBursts::10 29152 # Per bank write bursts -system.physmem.perBankRdBursts::11 31219 # Per bank write bursts -system.physmem.perBankRdBursts::12 26466 # Per bank write bursts -system.physmem.perBankRdBursts::13 26838 # Per bank write bursts -system.physmem.perBankRdBursts::14 25148 # Per bank write bursts -system.physmem.perBankRdBursts::15 25956 # Per bank write bursts -system.physmem.perBankWrBursts::0 36103 # Per bank write bursts -system.physmem.perBankWrBursts::1 37925 # Per bank write bursts -system.physmem.perBankWrBursts::2 36544 # Per bank write bursts -system.physmem.perBankWrBursts::3 38823 # Per bank write bursts -system.physmem.perBankWrBursts::4 41056 # Per bank write bursts -system.physmem.perBankWrBursts::5 42229 # Per bank write bursts -system.physmem.perBankWrBursts::6 37594 # Per bank write bursts -system.physmem.perBankWrBursts::7 36950 # Per bank write bursts -system.physmem.perBankWrBursts::8 37999 # Per bank write bursts -system.physmem.perBankWrBursts::9 38649 # Per bank write bursts -system.physmem.perBankWrBursts::10 38477 # Per bank write bursts -system.physmem.perBankWrBursts::11 38558 # Per bank write bursts -system.physmem.perBankWrBursts::12 34649 # Per bank write bursts -system.physmem.perBankWrBursts::13 36757 # Per bank write bursts -system.physmem.perBankWrBursts::14 36686 # Per bank write bursts -system.physmem.perBankWrBursts::15 37272 # Per bank write bursts +system.physmem.num_writes::total 1208678 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 57669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 491849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 138809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 348459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1112375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 57669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 115112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1505435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1505836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1505435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 57669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 492250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 138809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 348459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2618211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 440592 # Number of read requests accepted +system.physmem.writeReqs 615308 # Number of write requests accepted +system.physmem.readBursts 440592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 615308 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28181248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue +system.physmem.bytesWritten 38332736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28197888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 39379712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16359 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18561 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25854 # Per bank write bursts +system.physmem.perBankRdBursts::1 28544 # Per bank write bursts +system.physmem.perBankRdBursts::2 25469 # Per bank write bursts +system.physmem.perBankRdBursts::3 27506 # Per bank write bursts +system.physmem.perBankRdBursts::4 26728 # Per bank write bursts +system.physmem.perBankRdBursts::5 30588 # Per bank write bursts +system.physmem.perBankRdBursts::6 26415 # Per bank write bursts +system.physmem.perBankRdBursts::7 27502 # Per bank write bursts +system.physmem.perBankRdBursts::8 26500 # Per bank write bursts +system.physmem.perBankRdBursts::9 31676 # Per bank write bursts +system.physmem.perBankRdBursts::10 27941 # Per bank write bursts +system.physmem.perBankRdBursts::11 30917 # Per bank write bursts +system.physmem.perBankRdBursts::12 25895 # Per bank write bursts +system.physmem.perBankRdBursts::13 27920 # Per bank write bursts +system.physmem.perBankRdBursts::14 25066 # Per bank write bursts +system.physmem.perBankRdBursts::15 25811 # Per bank write bursts +system.physmem.perBankWrBursts::0 36067 # Per bank write bursts +system.physmem.perBankWrBursts::1 36031 # Per bank write bursts +system.physmem.perBankWrBursts::2 34636 # Per bank write bursts +system.physmem.perBankWrBursts::3 37309 # Per bank write bursts +system.physmem.perBankWrBursts::4 37132 # Per bank write bursts +system.physmem.perBankWrBursts::5 40234 # Per bank write bursts +system.physmem.perBankWrBursts::6 38375 # Per bank write bursts +system.physmem.perBankWrBursts::7 37986 # Per bank write bursts +system.physmem.perBankWrBursts::8 35542 # Per bank write bursts +system.physmem.perBankWrBursts::9 42123 # Per bank write bursts +system.physmem.perBankWrBursts::10 38624 # Per bank write bursts +system.physmem.perBankWrBursts::11 39603 # Per bank write bursts +system.physmem.perBankWrBursts::12 35582 # Per bank write bursts +system.physmem.perBankWrBursts::13 38033 # Per bank write bursts +system.physmem.perBankWrBursts::14 36333 # Per bank write bursts +system.physmem.perBankWrBursts::15 35339 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 51233787261500 # Total gap between requests +system.physmem.numWrRetry 73 # Number of times write queue was full causing retry +system.physmem.totGap 51273531025000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443127 # Read request sizes (log2) +system.physmem.readPktSize::6 440592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 607625 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 312054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 615308 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 297815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 95022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -180,199 +180,206 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 24672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 28080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 33366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 36383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 37105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 38583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 39124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 40093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 39396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 38019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 33410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 31074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.749383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.139289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.784627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 125431 45.72% 45.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 68607 25.01% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24542 8.95% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12363 4.51% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8633 3.15% 87.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5464 1.99% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4467 1.63% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3979 1.45% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20857 7.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274343 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 29886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.819313 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.330264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 12451 41.66% 41.66% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 16121 53.94% 95.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1059 3.54% 99.15% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 175 0.59% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 53 0.18% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 15 0.05% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 5 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 22598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 26146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 30213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 32129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 33829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 34268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 34523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 35690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 37755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 35326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 34217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 40396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 33787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 31090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 182 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 276595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.471737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.485529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.203347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 127319 46.03% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 69542 25.14% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24812 8.97% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12377 4.47% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8866 3.21% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5372 1.94% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4514 1.63% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3651 1.32% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20142 7.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 276595 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 29231 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.063871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.425422 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 11898 40.70% 40.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 15954 54.58% 95.28% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1083 3.70% 98.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 204 0.70% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 56 0.19% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 22 0.08% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::304-319 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 29886 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 29886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.286121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.739916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.649180 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 14 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 35 0.12% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 26501 88.67% 88.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1006 3.37% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 913 3.05% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 433 1.45% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 255 0.85% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 96 0.32% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 167 0.56% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 135 0.45% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 90 0.30% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 37 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 67 0.22% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 27 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 22 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 15 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 37 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 7 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 29886 # Writes before turning the bus around for reads -system.physmem.totQLat 10134279500 # Total ticks spent queuing -system.physmem.totMemAccLat 18438467000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2214450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22882.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::176-191 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 29231 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 29231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.490199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.518949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.634153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 58 0.20% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 27476 94.00% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 804 2.75% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 250 0.86% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 169 0.58% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 102 0.35% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 99 0.34% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 124 0.42% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 61 0.21% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 8 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 19 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 5 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 29231 # Writes before turning the bus around for reads +system.physmem.totQLat 10175638298 # Total ticks spent queuing +system.physmem.totMemAccLat 18431863298 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2201660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23109.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41632.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41859.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.76 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.35 # Average write queue length when enqueuing -system.physmem.readRowHits 333517 # Number of row buffer hits during reads -system.physmem.writeRowHits 441289 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.79 # Row buffer hit rate for writes -system.physmem.avgGap 48759162.26 # Average gap between requests -system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1059231600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 575701500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1730999400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1990714320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1163638516455 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29573392417500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34046889932055 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.714209 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48801846776250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem.avgWrQLen 25.67 # Average write queue length when enqueuing +system.physmem.readRowHits 330665 # Number of row buffer hits during reads +system.physmem.writeRowHits 432014 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.13 # Row buffer hit rate for writes +system.physmem.avgGap 48559078.53 # Average gap between requests +system.physmem.pageHitRate 73.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1047672360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 569481000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1705126800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1929536640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1163738784870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29596559989500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34072715762610 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.713146 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48842268608197 # Time in different power states +system.physmem_0.memoryStateTime::REF 1690779740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 103138521750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102045610303 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1014703200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 551648625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1723542600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1937720880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1160546619285 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29579668954500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34049945540370 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.696345 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48806318983250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem_1.actEnergy 1043355600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 567088500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1729462800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1951549200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1164487973490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29604202640250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34081147241280 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.697375 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48841133395944 # Time in different power states +system.physmem_1.memoryStateTime::REF 1690779740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 98691186250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 103204176556 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -409,48 +416,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 113519 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 113519 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 113519 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 113519 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 113519 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 1125423795568 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.567721 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.495393 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 486496827068 43.23% 43.23% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 638926968500 56.77% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1125423795568 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 82853 84.60% 84.60% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 15081 15.40% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 97934 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113519 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 113114 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 113114 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 113114 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 113114 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 113114 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 1113616699016 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.572841 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.494666 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 475691482516 42.72% 42.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 637925216500 57.28% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1113616699016 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 82726 84.85% 84.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 14770 15.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 97496 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113114 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113519 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97934 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97496 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97934 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 211453 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 210610 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78562985 # DTB read hits -system.cpu0.dtb.read_misses 85240 # DTB read misses -system.cpu0.dtb.write_hits 72018023 # DTB write hits -system.cpu0.dtb.write_misses 28279 # DTB write misses -system.cpu0.dtb.flush_tlb 1287 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 78321186 # DTB read hits +system.cpu0.dtb.read_misses 84847 # DTB read misses +system.cpu0.dtb.write_hits 71529400 # DTB write hits +system.cpu0.dtb.write_misses 28267 # DTB write misses +system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 51639 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 51007 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3776 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4028 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9794 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78648225 # DTB read accesses -system.cpu0.dtb.write_accesses 72046302 # DTB write accesses +system.cpu0.dtb.perms_faults 9780 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78406033 # DTB read accesses +system.cpu0.dtb.write_accesses 71557667 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 150581008 # DTB hits -system.cpu0.dtb.misses 113519 # DTB misses -system.cpu0.dtb.accesses 150694527 # DTB accesses +system.cpu0.dtb.hits 149850586 # DTB hits +system.cpu0.dtb.misses 113114 # DTB misses +system.cpu0.dtb.accesses 149963700 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -480,432 +487,430 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 63212 # Table walker walks requested -system.cpu0.itb.walker.walksLong 63212 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 63212 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 63212 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 63212 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 1125423794068 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.567766 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.495387 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 486446960568 43.22% 43.22% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 638976833500 56.78% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1125423794068 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54978 95.14% 95.14% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2806 4.86% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57784 # Table walker page sizes translated +system.cpu0.itb.walker.walks 63285 # Table walker walks requested +system.cpu0.itb.walker.walksLong 63285 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 63285 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 63285 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 63285 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 1113616695516 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.572887 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.494659 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 475639854016 42.71% 42.71% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 637976841500 57.29% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1113616695516 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 55054 95.20% 95.20% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2776 4.80% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57830 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63212 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63285 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63285 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 120996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 421062407 # ITB inst hits -system.cpu0.itb.inst_misses 63212 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57830 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57830 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 121115 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 419986176 # ITB inst hits +system.cpu0.itb.inst_misses 63285 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1287 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 36180 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 35884 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 421125619 # ITB inst accesses -system.cpu0.itb.hits 421062407 # DTB hits -system.cpu0.itb.misses 63212 # DTB misses -system.cpu0.itb.accesses 421125619 # DTB accesses -system.cpu0.numCycles 506570818 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 420049461 # ITB inst accesses +system.cpu0.itb.hits 419986176 # DTB hits +system.cpu0.itb.misses 63285 # DTB misses +system.cpu0.itb.accesses 420049461 # DTB accesses +system.cpu0.numCycles 505091044 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 420869800 # Number of instructions committed -system.cpu0.committedOps 495253800 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 454669961 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 407169 # Number of float alu accesses -system.cpu0.num_func_calls 25355566 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64011433 # number of instructions that are conditional controls -system.cpu0.num_int_insts 454669961 # number of integer instructions -system.cpu0.num_fp_insts 407169 # number of float instructions -system.cpu0.num_int_register_reads 669912724 # number of times the integer registers were read -system.cpu0.num_int_register_writes 361261423 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 658306 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 339356 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110690043 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 110438637 # number of times the CC registers were written -system.cpu0.num_mem_refs 150674741 # number of memory refs -system.cpu0.num_load_insts 78636195 # Number of load instructions -system.cpu0.num_store_insts 72038546 # Number of store instructions -system.cpu0.num_idle_cycles 494843268.961767 # Number of idle cycles -system.cpu0.num_busy_cycles 11727549.038232 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023151 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976849 # Percentage of idle cycles -system.cpu0.Branches 93932517 # Number of branches fetched +system.cpu0.committedInsts 419794202 # Number of instructions committed +system.cpu0.committedOps 493796806 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 453197936 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 421943 # Number of float alu accesses +system.cpu0.num_func_calls 25265539 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 63928321 # number of instructions that are conditional controls +system.cpu0.num_int_insts 453197936 # number of integer instructions +system.cpu0.num_fp_insts 421943 # number of float instructions +system.cpu0.num_int_register_reads 668318275 # number of times the integer registers were read +system.cpu0.num_int_register_writes 360308744 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 682016 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 353392 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110766057 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 110481712 # number of times the CC registers were written +system.cpu0.num_mem_refs 149944655 # number of memory refs +system.cpu0.num_load_insts 78394551 # Number of load instructions +system.cpu0.num_store_insts 71550104 # Number of store instructions +system.cpu0.num_idle_cycles 493080351.361326 # Number of idle cycles +system.cpu0.num_busy_cycles 12010692.638674 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023779 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976221 # Percentage of idle cycles +system.cpu0.Branches 93737042 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 343715794 69.36% 69.36% # Class of executed instruction -system.cpu0.op_class::IntMult 1059861 0.21% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 47874 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 49044 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 78636195 15.87% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 72038546 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 342973363 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1071330 0.22% 69.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 48623 0.01% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 51721 0.01% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::MemRead 78394551 15.87% 85.52% # Class of executed instruction +system.cpu0.op_class::MemWrite 71550104 14.48% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 495547316 # Class of executed instruction +system.cpu0.op_class::total 494089735 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16313 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10214702 # number of replacements +system.cpu0.dcache.tags.replacements 10220953 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 304791830 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10215214 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.837048 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 305187926 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10221465 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.857552 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.816800 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.965643 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.217276 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970345 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009699 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.019956 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.221457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.755911 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 8.022352 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971136 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.013195 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.015669 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1295808199 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1295808199 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73344072 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 23670257 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 59561251 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156575580 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68109688 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 21690684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 50098487 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 139898859 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 192172 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58926 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 140820 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 391918 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 149127 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 52869 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 128452 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 330448 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1807582 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 555748 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1239879 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3603209 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1920927 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 598964 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1426295 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3946186 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 141453760 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 45360941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 109659738 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296474439 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 141645932 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 45419867 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 109800558 # number of overall hits -system.cpu0.dcache.overall_hits::total 296866357 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2534039 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 789361 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 4745712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 8069112 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1082533 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 339457 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 4257122 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5679112 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 624926 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 200468 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 451799 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1277193 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 751391 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 141795 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data 340989 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1234175 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 114175 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 43476 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 234793 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 392444 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1297346809 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1297346809 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73103498 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 24004695 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 59713819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156822012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67621876 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 22136915 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 50273570 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 140032361 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 191205 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58550 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144781 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 394536 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 151179 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 54099 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 126065 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 331343 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1805832 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 567281 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1240318 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3613431 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1916828 # 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average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10656.400668 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14692.893780 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14032.145473 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10022.927557 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 75250 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30714.428571 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19381.596163 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26450.190545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18911.895047 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16458.681291 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25186.241999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17304.342992 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 16525094 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 18605 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1165104 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 417 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.183364 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 44.616307 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017233 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015263 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013430 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.772612 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.750803 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.386644 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.728409 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.721153 # 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number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10803547759 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2690383999 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 6865304661 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 9555688660 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 463968000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1147138011 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1611106011 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 184000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20066054383 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 54721440751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 74787495134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22783073883 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 62807969010 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 85591042893 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 895108750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474898001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2370006751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 895104500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1438317956 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2333422456 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1790213250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2913215957 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4703429207 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.032110 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017256 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013544 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758455 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.746313 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.382892 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726869 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.723656 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306874 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059658 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060507 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031364 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024189 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023419 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012583 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027034 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014585 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13174.512020 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15018.399262 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14506.104274 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26840.685559 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34004.539272 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31745.347553 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14804.559131 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20646.617420 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18832.391141 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15614.478635 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29214.023956 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25199.426761 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12459.369389 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12636.193464 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12589.530155 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33833.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17260.844407 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20005.756686 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19214.990502 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16889.312920 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20094.202488 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19160.711407 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023378 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023590 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012595 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027137 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027271 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014573 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13969.532503 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14813.666446 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14583.200315 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28093.961722 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32572.882762 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31196.486788 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14749.416433 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 17782.555628 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.098290 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 18686.985567 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 20406.521061 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 19891.191595 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12659.081608 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12920.839934 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12844.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 46000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18165.473548 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19493.093439 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -916,142 +921,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14521093 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.976902 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 611027566 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14521605 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.077137 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9055108500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.542496 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.290435 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.143971 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971763 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.008380 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019812 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 14550991 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 611237841 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14551503 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.005135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9058621500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 496.705744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.210417 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.060673 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970128 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.010177 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019650 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 640492964 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 640492964 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 414512221 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 132673632 # 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number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14943672 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6607970 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 2066459 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 6269243 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14943672 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6607970 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 2066459 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 6269243 # number of overall misses -system.cpu0.icache.overall_misses::total 14943672 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 27753435750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 83574446765 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 111327882515 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 27753435750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 83574446765 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 111327882515 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 27753435750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 83574446765 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 111327882515 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 421120191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 134740091 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 70110956 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 625971238 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 421120191 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 134740091 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 70110956 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 625971238 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 421120191 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 134740091 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 70110956 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 625971238 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015691 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015337 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089419 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023873 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015691 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015337 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023873 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015691 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015337 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023873 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13430.431356 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13330.867342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7449.834453 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13430.431356 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13330.867342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7449.834453 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13430.431356 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13330.867342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7449.834453 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 42762 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 640780747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 640780747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 413451033 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 134065919 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 63720889 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13095.859222 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7378.836625 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13396.093910 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13095.859222 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7378.836625 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 51965 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 3542 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 3925 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.072840 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.239490 # 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mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012642 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11613.624763 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11613.624763 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11613.624763 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 439662 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 439662 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 439662 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 439662 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 439662 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 439662 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2115468 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5843181 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 7958649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 2115468 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 5843181 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 7958649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 2115468 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 5843181 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 7958649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25161480508 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 69932206790 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 95093687298 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25161480508 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 69932206790 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 95093687298 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25161480508 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 69932206790 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 95093687298 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012709 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012709 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012709 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11948.471066 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1082,72 +1087,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 39379 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 39379 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 5977 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28234 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 39373 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.279379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 55.436197 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 39372 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::10240-11263 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 39373 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 34217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21462.701289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17640.355852 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13201.639709 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 33415 97.66% 97.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 571 1.67% 99.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 171 0.50% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 26 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 6 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 34217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1508431008 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.298098 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.457423 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1058770000 70.19% 70.19% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 449661008 29.81% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1508431008 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 28234 82.53% 82.53% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 5977 17.47% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 34211 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 39379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 40069 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 40069 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6011 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28822 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 40066 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.287026 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 57.452621 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 40065 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 40066 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 34836 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23148.919221 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19687.951217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13456.896972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 22742 65.28% 65.28% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 11809 33.90% 99.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 149 0.43% 99.61% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 100 0.29% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 34836 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2552299344 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.586801 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.492408 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1054607500 41.32% 41.32% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1497691844 58.68% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2552299344 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 28822 82.74% 82.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6011 17.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 34833 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40069 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 39379 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34833 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34211 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 73590 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34833 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 74902 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25323699 # DTB read hits -system.cpu1.dtb.read_misses 30085 # DTB read misses -system.cpu1.dtb.write_hits 22831654 # DTB write hits -system.cpu1.dtb.write_misses 9294 # DTB write misses -system.cpu1.dtb.flush_tlb 1278 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25646035 # DTB read hits +system.cpu1.dtb.read_misses 30818 # DTB read misses +system.cpu1.dtb.write_hits 23287178 # DTB write hits +system.cpu1.dtb.write_misses 9251 # DTB write misses +system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 21869 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 22057 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1270 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 3016 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25353784 # DTB read accesses -system.cpu1.dtb.write_accesses 22840948 # DTB write accesses +system.cpu1.dtb.perms_faults 2875 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25676853 # DTB read accesses +system.cpu1.dtb.write_accesses 23296429 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 48155353 # DTB hits -system.cpu1.dtb.misses 39379 # DTB misses -system.cpu1.dtb.accesses 48194732 # DTB accesses +system.cpu1.dtb.hits 48933213 # DTB hits +system.cpu1.dtb.misses 40069 # DTB misses +system.cpu1.dtb.accesses 48973282 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1177,135 +1180,137 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 23659 # Table walker walks requested -system.cpu1.itb.walker.walksLong 23659 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1141 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20683 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 23659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 23659 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 23659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 21824 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24542.418897 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21182.327207 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14187.388293 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 20284 92.94% 92.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 1308 5.99% 98.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.73% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 37 0.17% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 21824 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 23826 # Table walker walks requested +system.cpu1.itb.walker.walksLong 23826 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1156 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20921 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 23826 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 23826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 23826 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 22077 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26240.136794 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22930.281403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15976.450560 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 11277 51.08% 51.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 10485 47.49% 98.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 121 0.55% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 153 0.69% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 22077 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 20683 94.77% 94.77% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1141 5.23% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 21824 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 20921 94.76% 94.76% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1156 5.24% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 22077 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23659 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23659 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23826 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23826 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 45483 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 134740091 # ITB inst hits -system.cpu1.itb.inst_misses 23659 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 22077 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 22077 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 45903 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 136181387 # ITB inst hits +system.cpu1.itb.inst_misses 23826 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1278 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16092 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 134763750 # ITB inst accesses -system.cpu1.itb.hits 134740091 # DTB hits -system.cpu1.itb.misses 23659 # DTB misses -system.cpu1.itb.accesses 134763750 # DTB accesses -system.cpu1.numCycles 1278124825 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 136205213 # ITB inst accesses +system.cpu1.itb.hits 136181387 # DTB hits +system.cpu1.itb.misses 23826 # DTB misses +system.cpu1.itb.accesses 136205213 # DTB accesses +system.cpu1.numCycles 1276125055 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 134646225 # Number of instructions committed -system.cpu1.committedOps 158126706 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 145069492 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 137737 # Number of float alu accesses -system.cpu1.num_func_calls 7885244 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20644863 # number of instructions that are conditional controls -system.cpu1.num_int_insts 145069492 # number of integer instructions -system.cpu1.num_fp_insts 137737 # number of float instructions -system.cpu1.num_int_register_reads 212132646 # number of times the integer registers were read -system.cpu1.num_int_register_writes 115229722 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 221669 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 118820 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35576682 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 35511484 # number of times the CC registers were written -system.cpu1.num_mem_refs 48152949 # number of memory refs -system.cpu1.num_load_insts 25322940 # Number of load instructions -system.cpu1.num_store_insts 22830009 # Number of store instructions -system.cpu1.num_idle_cycles 1251340382.439470 # Number of idle cycles -system.cpu1.num_busy_cycles 26784442.560530 # Number of busy cycles -system.cpu1.not_idle_fraction 0.020956 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.979044 # Percentage of idle cycles -system.cpu1.Branches 30070128 # Number of branches fetched +system.cpu1.committedInsts 136088494 # Number of instructions committed +system.cpu1.committedOps 159971532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 146914767 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 136439 # Number of float alu accesses +system.cpu1.num_func_calls 8067189 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20777484 # number of instructions that are conditional controls +system.cpu1.num_int_insts 146914767 # number of integer instructions +system.cpu1.num_fp_insts 136439 # number of float instructions +system.cpu1.num_int_register_reads 213265371 # number of times the integer registers were read +system.cpu1.num_int_register_writes 116491926 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 215836 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 125376 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 35465151 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 35400633 # number of times the CC registers were written +system.cpu1.num_mem_refs 48930269 # number of memory refs +system.cpu1.num_load_insts 25645213 # Number of load instructions +system.cpu1.num_store_insts 23285056 # Number of store instructions +system.cpu1.num_idle_cycles 1249288140.787440 # Number of idle cycles +system.cpu1.num_busy_cycles 26836914.212560 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021030 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978970 # Percentage of idle cycles +system.cpu1.Branches 30426471 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 109684380 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 350403 0.22% 69.55% # Class of executed instruction -system.cpu1.op_class::IntDiv 14329 0.01% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 18470 0.01% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::MemRead 25322940 16.00% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 22830009 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 110766463 69.20% 69.20% # Class of executed instruction +system.cpu1.op_class::IntMult 334649 0.21% 69.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 13512 0.01% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 19532 0.01% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::MemRead 25645213 16.02% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 23285056 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 158220572 # Class of executed instruction +system.cpu1.op_class::total 160064425 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 97203672 # Number of BP lookups -system.cpu2.branchPred.condPredicted 66186757 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4359750 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 65808751 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47109720 # Number of BTB hits +system.cpu2.branchPred.lookups 97087615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 66103650 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4347660 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 66231841 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47108077 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.585799 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12465679 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 131865 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.126027 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12454763 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 133862 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1335,81 +1340,88 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 641865 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 641865 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11159 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66692 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 388613 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 253252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 1931.812977 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 11499.357470 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-65535 251854 99.45% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-131071 1074 0.42% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::131072-196607 172 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::196608-262143 83 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::262144-327679 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 253252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 288612 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 20860.236245 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 16529.214515 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 15237.417207 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 285772 99.02% 99.02% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 2386 0.83% 99.84% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 259 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 137 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 41 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 288612 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 644386966916 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.557890 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.603276 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-3 643756648416 99.90% 99.90% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-7 358289000 0.06% 99.96% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-11 119891000 0.02% 99.98% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-15 74898000 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-19 28944500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-23 14290500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-27 13699500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-31 16934500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::32-35 3107500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walks 649855 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 649855 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11017 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66935 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 396890 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 252965 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 2053.590418 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 12193.038070 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-65535 251454 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-131071 1182 0.47% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-196607 177 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::262144-327679 45 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::393216-458751 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 252965 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 293492 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 21382.093181 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 17292.884496 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 15231.620197 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 288902 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 4097 1.40% 99.83% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 265 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 159 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 56 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 293492 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 636867012660 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.530422 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.615162 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-3 636197778160 99.89% 99.89% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-7 383895000 0.06% 99.96% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-11 122059000 0.02% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-15 78250500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-19 30640500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-23 15817000 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-27 14461500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-31 20012000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::32-35 3793500 0.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 644386966916 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 66692 85.67% 85.67% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 11159 14.33% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 77851 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 641865 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walksPending::40-43 22000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::44-47 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::48-51 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::56-59 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 636867012660 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 66935 85.87% 85.87% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 11017 14.13% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 77952 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 649855 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 641865 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77851 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 649855 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77952 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77851 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 719716 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77952 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 727807 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 77755602 # DTB read hits -system.cpu2.dtb.read_misses 445998 # DTB read misses -system.cpu2.dtb.write_hits 59736492 # DTB write hits -system.cpu2.dtb.write_misses 195867 # DTB write misses -system.cpu2.dtb.flush_tlb 1279 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 77417011 # DTB read hits +system.cpu2.dtb.read_misses 450124 # DTB read misses +system.cpu2.dtb.write_hits 59942200 # DTB write hits +system.cpu2.dtb.write_misses 199731 # DTB write misses +system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 38251 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 105 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 6104 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 38279 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 93 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 6471 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 37697 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 78201600 # DTB read accesses -system.cpu2.dtb.write_accesses 59932359 # DTB write accesses +system.cpu2.dtb.perms_faults 38915 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 77867135 # DTB read accesses +system.cpu2.dtb.write_accesses 60141931 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 137492094 # DTB hits -system.cpu2.dtb.misses 641865 # DTB misses -system.cpu2.dtb.accesses 138133959 # DTB accesses +system.cpu2.dtb.hits 137359211 # DTB hits +system.cpu2.dtb.misses 649855 # DTB misses +system.cpu2.dtb.accesses 138009066 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1439,396 +1451,397 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 80363 # Table walker walks requested -system.cpu2.itb.walker.walksLong 80363 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2481 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55642 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 10291 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 70072 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1335.283708 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 8007.621087 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-32767 69580 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-65535 258 0.37% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-98303 168 0.24% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::98304-131071 29 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::131072-163839 18 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walks 80378 # Table walker walks requested +system.cpu2.itb.walker.walksLong 80378 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2425 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 10589 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 69789 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1377.194114 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 8185.559112 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-32767 69315 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-65535 221 0.32% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-98303 162 0.23% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-131071 61 0.09% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu2.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 70072 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 68414 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 25615.416172 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 21446.317164 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 15929.809681 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 60316 88.16% 88.16% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 7055 10.31% 98.48% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 610 0.89% 99.37% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 277 0.40% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 68 0.10% 99.87% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 37 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 13 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 11 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 68414 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 468293315780 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.887572 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.316276 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 52695891356 11.25% 11.25% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 415558218424 88.74% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 33808000 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 3984500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 940500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::6 21500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::7 47500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 468293315780 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 55642 95.73% 95.73% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 2481 4.27% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 58123 # Table walker page sizes translated +system.cpu2.itb.walker.walkWaitTime::total 69789 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 68780 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 26602.237307 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 22568.644275 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 16910.110071 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 37031 53.84% 53.84% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 30619 44.52% 98.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 406 0.59% 98.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 526 0.76% 99.71% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 70 0.10% 99.81% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.10% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 14 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 68780 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 465075818820 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.908790 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.288323 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 42467517784 9.13% 9.13% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 422566839536 90.86% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 36100000 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 4751500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 426500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 73000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 66000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::7 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 465075818820 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 55766 95.83% 95.83% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 2425 4.17% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 58191 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80363 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80363 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80378 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80378 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58123 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58123 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 138486 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70281222 # ITB inst hits -system.cpu2.itb.inst_misses 80363 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58191 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58191 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 138569 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70175055 # ITB inst hits +system.cpu2.itb.inst_misses 80378 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1279 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 29841 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 30057 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 147172 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 147979 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70361585 # ITB inst accesses -system.cpu2.itb.hits 70281222 # DTB hits -system.cpu2.itb.misses 80363 # DTB misses -system.cpu2.itb.accesses 70361585 # DTB accesses -system.cpu2.numCycles 465003102 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70255433 # ITB inst accesses +system.cpu2.itb.hits 70175055 # DTB hits +system.cpu2.itb.misses 80378 # DTB misses +system.cpu2.itb.accesses 70255433 # DTB accesses +system.cpu2.numCycles 460136549 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 180276648 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 431826640 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 97203672 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 59575399 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 257301281 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9838745 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 1858453 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 8409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1979 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3769521 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 119476 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 4195 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 70111000 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2676908 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 31653 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 448259178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.125687 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.367693 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 178152693 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 431776536 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 97087615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 59562840 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 255654820 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9805571 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 1895155 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3768954 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 115299 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 5484 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 70003785 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2663761 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 31715 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 444504807 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.135202 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.375157 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 341932387 76.28% 76.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13442109 3.00% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13673824 3.05% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9898176 2.21% 84.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 19945540 4.45% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6633561 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7181223 1.60% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6340938 1.41% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 29211420 6.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 338236255 76.09% 76.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13308034 2.99% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13681319 3.08% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9908939 2.23% 84.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 20069262 4.51% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6632314 1.49% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7130783 1.60% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6321378 1.42% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 29216523 6.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 448259178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.209039 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.928653 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 147221492 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 209051737 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 78610938 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9453516 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3919439 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14421531 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1013878 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 471467563 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3120361 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3919439 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 152659562 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18224952 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 165892682 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82476717 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25083567 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 460107253 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 59923 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1862817 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1245864 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 11710592 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 3796 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 439693345 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 700325975 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 542687716 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 700561 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 367082877 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 72610468 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 9962331 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8523572 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 52244758 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 74674759 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 62877107 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9528051 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10323504 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 437324992 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9951593 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 435965427 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 606984 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 56598171 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 39504404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 237598 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 448259178 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.972574 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.684760 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 444504807 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.210997 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.938366 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 145587242 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 206867789 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 78822121 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9322949 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3902682 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14396196 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1015243 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 471778409 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3111772 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3902682 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 151005109 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 15075303 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 166939616 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82595953 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 24983877 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 460482983 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 55875 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1575989 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1122405 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 11824382 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 2747 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 440049969 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 701739830 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 543201034 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 591948 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 368298602 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 71751367 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 10111591 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8659381 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 51276485 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74779146 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 63098170 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9504759 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10253668 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 437555873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10088471 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 436351243 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 628919 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 55749778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 38531819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 239828 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 444504807 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.981657 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.695270 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 279914977 62.44% 62.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 68317821 15.24% 77.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32057682 7.15% 84.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22901153 5.11% 89.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 17277675 3.85% 93.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11955785 2.67% 96.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 7990147 1.78% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4753228 1.06% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3090710 0.69% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 276381275 62.18% 62.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 68338590 15.37% 77.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 31936602 7.18% 84.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22769301 5.12% 89.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 16982310 3.82% 93.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11978521 2.69% 96.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 8056839 1.81% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4822285 1.08% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3239084 0.73% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 448259178 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 444504807 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2208249 25.46% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 17979 0.21% 25.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1386 0.02% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3543832 40.86% 66.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2901485 33.45% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2174414 25.25% 25.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 16907 0.20% 25.44% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1448 0.02% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3443156 39.98% 65.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2977212 34.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 294954302 67.66% 67.66% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1046783 0.24% 67.90% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49286 0.01% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 204 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 50291 0.01% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 79323839 18.19% 86.11% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 60540722 13.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 20 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 295429003 67.70% 67.70% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1051015 0.24% 67.95% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50004 0.01% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 103 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 46521 0.01% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 79012045 18.11% 86.07% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 60762532 13.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 435965427 # Type of FU issued -system.cpu2.iq.rate 0.937554 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8672932 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.019894 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1328634186 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 503978442 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 419353037 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 835762 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 397688 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 361980 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 444191291 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 447068 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3425545 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 436351243 # Type of FU issued +system.cpu2.iq.rate 0.948308 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8613137 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.019739 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1325660566 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 503495404 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 420349481 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 788783 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 388209 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 352523 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 444542452 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 421908 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3464909 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 12352202 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 15972 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 509888 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6626020 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 12199650 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 16692 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 497657 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6603925 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2713782 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 6189069 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 2708670 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 5665546 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3919439 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10963120 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 5851568 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 447374999 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1338773 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 74674759 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 62877107 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8331773 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 175433 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 5598830 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 509888 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 2010429 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1729641 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3740070 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 430866261 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77742862 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4466264 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 3902682 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10385108 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3443992 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 447742813 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1337786 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74779146 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 63098170 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8466807 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 165633 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3216656 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 497657 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 2020710 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1734931 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3755641 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 431226765 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77404459 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4484174 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 98414 # number of nop insts executed -system.cpu2.iew.exec_refs 137478821 # number of memory reference insts executed -system.cpu2.iew.exec_branches 79993995 # Number of branches executed -system.cpu2.iew.exec_stores 59735959 # Number of stores executed -system.cpu2.iew.exec_rate 0.926588 # Inst execution rate -system.cpu2.iew.wb_sent 420591447 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 419715017 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 207428552 # num instructions producing a value -system.cpu2.iew.wb_consumers 360230847 # num instructions consuming a value +system.cpu2.iew.exec_nop 98469 # number of nop insts executed +system.cpu2.iew.exec_refs 137346126 # number of memory reference insts executed +system.cpu2.iew.exec_branches 80126150 # Number of branches executed +system.cpu2.iew.exec_stores 59941667 # Number of stores executed +system.cpu2.iew.exec_rate 0.937171 # Inst execution rate +system.cpu2.iew.wb_sent 421619050 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 420702004 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 208179390 # num instructions producing a value +system.cpu2.iew.wb_consumers 361509938 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.902607 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575821 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.914298 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575861 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 60870503 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9713995 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3359660 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 437963055 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.882384 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.879484 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 60056737 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9848643 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3347389 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 434346973 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.892410 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.889968 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 298875540 68.24% 68.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 66218430 15.12% 83.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24721461 5.64% 89.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 11149325 2.55% 91.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 8001884 1.83% 93.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4923567 1.12% 94.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4422174 1.01% 95.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 3021510 0.69% 96.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16629164 3.80% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 295032576 67.93% 67.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 66481508 15.31% 83.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24486149 5.64% 88.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 11154018 2.57% 91.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 8043816 1.85% 93.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4878030 1.12% 94.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4540806 1.05% 95.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 2951206 0.68% 96.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16778864 3.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 437963055 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 329380138 # Number of instructions committed -system.cpu2.commit.committedOps 386451624 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 434346973 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 330373719 # Number of instructions committed +system.cpu2.commit.committedOps 387615464 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 118573644 # Number of memory references committed -system.cpu2.commit.loads 62322557 # Number of loads committed -system.cpu2.commit.membars 2596368 # Number of memory barriers committed -system.cpu2.commit.branches 73601182 # Number of branches committed -system.cpu2.commit.fp_insts 348235 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 355043998 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9589619 # Number of function calls committed. +system.cpu2.commit.refs 119073741 # Number of memory references committed +system.cpu2.commit.loads 62579496 # Number of loads committed +system.cpu2.commit.membars 2588612 # Number of memory barriers committed +system.cpu2.commit.branches 73762518 # Number of branches committed +system.cpu2.commit.fp_insts 337914 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 356071087 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9588871 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 267002089 69.09% 69.09% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 796041 0.21% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 36743 0.01% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 43107 0.01% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 62322557 16.13% 85.44% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 56251087 14.56% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 267662094 69.05% 69.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 802922 0.21% 69.26% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 37337 0.01% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 39370 0.01% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 62579496 16.14% 85.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 56494245 14.57% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 386451624 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16629164 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 387615464 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16778864 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 866035132 # The number of ROB reads -system.cpu2.rob.rob_writes 904953656 # The number of ROB writes -system.cpu2.timesIdled 2976137 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 16743924 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99448354933 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 329380138 # Number of Instructions Simulated -system.cpu2.committedOps 386451624 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.411752 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.411752 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.708340 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.708340 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 506713870 # number of integer regfile reads -system.cpu2.int_regfile_writes 300217827 # number of integer regfile writes -system.cpu2.fp_regfile_reads 684649 # number of floating regfile reads -system.cpu2.fp_regfile_writes 429068 # number of floating regfile writes -system.cpu2.cc_regfile_reads 91867416 # number of cc regfile reads -system.cpu2.cc_regfile_writes 92641749 # number of cc regfile writes -system.cpu2.misc_regfile_reads 1672272175 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9817116 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40335 # Transaction distribution -system.iobus.trans_dist::ReadResp 40335 # Transaction distribution -system.iobus.trans_dist::WriteReq 136665 # Transaction distribution -system.iobus.trans_dist::WriteResp 30001 # Transaction distribution +system.cpu2.rob.rob_reads 862595097 # The number of ROB reads +system.cpu2.rob.rob_writes 905518660 # The number of ROB writes +system.cpu2.timesIdled 2960768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 15631742 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99536690500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 330373719 # Number of Instructions Simulated +system.cpu2.committedOps 387615464 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.392776 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.392776 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.717991 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.717991 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 507371314 # number of integer regfile reads +system.cpu2.int_regfile_writes 300778245 # number of integer regfile writes +system.cpu2.fp_regfile_reads 673893 # number of floating regfile reads +system.cpu2.fp_regfile_writes 409456 # number of floating regfile writes +system.cpu2.cc_regfile_reads 92253105 # number of cc regfile reads +system.cpu2.cc_regfile_writes 93114012 # number of cc regfile writes +system.cpu2.misc_regfile_reads 1670741863 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9943766 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40265 # Transaction distribution +system.iobus.trans_dist::ReadResp 40265 # Transaction distribution +system.iobus.trans_dist::WriteReq 136537 # Transaction distribution +system.iobus.trans_dist::WriteResp 29873 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1843,13 +1856,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353604 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1864,87 +1877,87 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13687000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13825000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 7449000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 8203000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 16992000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 331631076 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 196611881 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 38629000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39351000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36767371 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36922037 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.417241 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.421568 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085934181009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.549977 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.867264 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221874 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429204 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651078 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13085930884009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547277 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.874291 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221705 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.tags.tag_accesses 1039659 # Number of tag accesses +system.iocache.tags.data_accesses 1039659 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8820 # number of demand (read+write) misses -system.iocache.demand_misses::total 8860 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses +system.iocache.demand_misses::total 8854 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8820 # number of overall misses -system.iocache.overall_misses::total 8860 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 78330160 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 81082160 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9376503545 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9376503545 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 78330160 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 81082160 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 78330160 # number of overall miss cycles -system.iocache.overall_miss_latency::total 81082160 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8814 # number of overall misses +system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 61206163 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 63638163 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 61206163 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 63638163 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 61206163 # number of overall miss cycles +system.iocache.overall_miss_latency::total 63638163 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8820 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8860 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8820 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8860 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1958,416 +1971,410 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 8880.970522 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 9154.585074 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87906.918407 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 87906.918407 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 9151.485327 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 9151.485327 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 58174 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 6944.198207 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 7189.940459 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 60800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 60800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7340 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3712 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.925613 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.615032 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 459 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34504 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 34504 # number of WriteInvalidateReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 424 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 35584 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 35584 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 459 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 424 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 459 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 475 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 54458660 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 56378660 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7582053787 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7582053787 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 54458660 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 56378660 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 54458660 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 56378660 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 424 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 440 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1600000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 38938201 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 40538201 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4786173717 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4786173717 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 1600000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 38938201 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 40538201 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 1600000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 38938201 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 40538201 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.053630 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.323483 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.323483 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.049712 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.333608 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.333608 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.053612 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.049695 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.053612 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 118646.318083 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118691.915789 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219744.197397 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219744.197397 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency +system.iocache.overall_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.049695 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 91835.379717 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 92132.275000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134503.532964 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134503.532964 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1296056 # number of replacements -system.l2c.tags.tagsinuse 65324.265743 # Cycle average of tags in use -system.l2c.tags.total_refs 28829950 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1358778 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.217557 # Average number of references to valid blocks. +system.l2c.tags.replacements 1296366 # number of replacements +system.l2c.tags.tagsinuse 65320.100787 # Cycle average of tags in use +system.l2c.tags.total_refs 28848747 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1358615 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.233938 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37285.924880 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 168.149057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 240.751709 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3675.446789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8312.608354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 50.722331 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 75.631311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1066.604817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3135.281683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 117.351685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 183.998379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2140.151911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 8871.642837 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.568938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003674 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.126840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.016275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.047841 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002808 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.135371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996769 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 311 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 310 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54001 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004745 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.952316 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 273473120 # Number of tag accesses -system.l2c.tags.data_accesses 273473120 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 199000 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 127150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6565279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3138242 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 69576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 49228 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 2053777 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 983926 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 389952 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 151346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 5813280 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 2472232 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22012988 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7876656 # number of Writeback hits -system.l2c.Writeback_hits::total 7876656 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347388 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 111332 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu2.data 265723 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 724443 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4844 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1532 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 3474 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9850 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 804234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 251858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 549088 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1605180 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 199000 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 127150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6565279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3942476 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 69576 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 49228 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 2053777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 1235784 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 389952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 151346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 5813280 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 3021320 # number of demand (read+write) hits -system.l2c.demand_hits::total 23618168 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 199000 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 127150 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6565279 # number of overall hits -system.l2c.overall_hits::cpu0.data 3942476 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 69576 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 49228 # number of overall hits -system.l2c.overall_hits::cpu1.inst 2053777 # number of overall hits -system.l2c.overall_hits::cpu1.data 1235784 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 389952 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 151346 # number of overall hits -system.l2c.overall_hits::cpu2.inst 5813280 # number of overall hits -system.l2c.overall_hits::cpu2.data 3021320 # number of overall hits -system.l2c.overall_hits::total 23618168 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2029 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1956 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 42691 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 134898 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 540 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 467 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 12682 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 37643 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 1489 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1413 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 33897 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 109098 # number of ReadReq misses -system.l2c.ReadReq_misses::total 378803 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 404003 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 30463 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu2.data 72816 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 507282 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17431 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5541 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 12769 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35741 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37068.766455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 192.906222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 268.941849 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3824.960525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8195.071890 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 57.414493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 82.820036 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 874.447112 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2433.555862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 94.156487 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 158.776869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2237.420000 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 9830.862987 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565624 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002944 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.058364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.125047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001264 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001437 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.002423 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.150007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996706 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 358 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61891 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 358 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 590 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2804 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4928 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53429 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005463 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.944382 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 273721010 # Number of tag accesses +system.l2c.tags.data_accesses 273721010 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 197948 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 127305 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6549451 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3139875 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 71739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 49467 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 2103694 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 962152 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 389616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 148852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 5808812 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 2494651 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22043562 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7872498 # number of Writeback hits +system.l2c.Writeback_hits::total 7872498 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 348712 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 112622 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu2.data 261017 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 722351 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 4748 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1579 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 3377 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9704 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 802024 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 244881 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 560523 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1607428 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 197948 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 127305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6549451 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3941899 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 71739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 49467 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 2103694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 1207033 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 389616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 148852 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 5808812 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3055174 # number of demand (read+write) hits +system.l2c.demand_hits::total 23650990 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 197948 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 127305 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6549451 # 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mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.403777 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.234895 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.235279 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116851 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.085113 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.084268 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.018101 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.085113 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.084268 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.018101 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63444.451824 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73925.270446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 69662.173862 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20456.882185 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 26943.763266 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25030.403741 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10004.602396 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.512234 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61375.342097 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 82629.743678 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75956.062337 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237202 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.229828 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.115309 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017972 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017972 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70684.888876 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 80226.246291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76625.596229 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31506.347922 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 32994.424201 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32557.461479 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17532.667268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17754.370121 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17687.229290 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68006.622871 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 88461.348427 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82062.371797 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2565,55 +2568,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 464425 # Transaction distribution -system.membus.trans_dist::ReadResp 464425 # Transaction distribution -system.membus.trans_dist::WriteReq 33772 # Transaction distribution -system.membus.trans_dist::WriteResp 33772 # Transaction distribution -system.membus.trans_dist::Writeback 1204773 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 613884 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 613884 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36393 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36397 # Transaction distribution -system.membus.trans_dist::ReadExReq 501696 # Transaction distribution -system.membus.trans_dist::ReadExResp 501696 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 465050 # Transaction distribution +system.membus.trans_dist::ReadResp 465050 # Transaction distribution +system.membus.trans_dist::WriteReq 33644 # Transaction distribution +system.membus.trans_dist::WriteResp 33644 # Transaction distribution +system.membus.trans_dist::Writeback 1206105 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 615969 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 615969 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36256 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36258 # Transaction distribution +system.membus.trans_dist::ReadExReq 502974 # Transaction distribution +system.membus.trans_dist::ReadExResp 502974 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4167195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4504521 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4046690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4176068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4513354 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159270496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159440210 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14195136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14195136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173635346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 600 # Total snoops (count) -system.membus.snoop_fanout::samples 2744389 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159620960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159790354 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 541 # Total snoops (count) +system.membus.snoop_fanout::samples 2749696 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2744389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2749696 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2744389 # Request fanout histogram -system.membus.reqLayer0.occupancy 42480999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2749696 # Request fanout histogram +system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1323000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1342002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6141947499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3662717737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4337026701 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2514330197 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 38901629 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37911963 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2657,55 +2662,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 22911195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22910936 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7876656 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1266229 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1231725 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45591 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45598 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2107463 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2107463 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29129582 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28533410 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 850957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 60274765 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 929555284 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158084670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3113192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6291728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2097044874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 377016 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 34216462 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003376 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.058008 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 22942749 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22942559 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7872498 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1267320 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1231707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45322 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45326 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2110986 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2110986 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29189373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28540858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760970 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 60340199 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 931468564 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158220350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3098688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 376855 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 34241641 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003374 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.057992 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 34100938 99.66% 99.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115524 0.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 34126094 99.66% 99.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115547 0.34% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 34216462 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 26470973727 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 972000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 34241641 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 35634626823 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 21264279204 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11949873226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 7318478020 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 276240027 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 275201891 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 654460701 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 650856160 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index 726dee18b..6fc6c48c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.358448 # Number of seconds simulated -sim_ticks 51358448410500 # Number of ticks simulated -final_tick 51358448410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.318118 # Number of seconds simulated +sim_ticks 51318118168000 # Number of ticks simulated +final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129809 # Simulator instruction rate (inst/s) -host_op_rate 152542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7366025588 # Simulator tick rate (ticks/s) -host_mem_usage 732256 # Number of bytes of host memory used -host_seconds 6972.34 # Real time elapsed on the host -sim_insts 905073903 # Number of instructions simulated -sim_ops 1063573170 # Number of ops (including micro ops) simulated +host_inst_rate 134411 # Simulator instruction rate (inst/s) +host_op_rate 157933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7593762336 # Simulator tick rate (ticks/s) +host_mem_usage 732664 # Number of bytes of host memory used +host_seconds 6757.93 # Real time elapsed on the host +sim_insts 908340493 # Number of instructions simulated +sim_ops 1067303522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 167040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 151040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3952000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28582936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 161216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 144320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3546944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27869040 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401920 # Number of bytes read from this memory -system.physmem.bytes_read::total 64976456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3952000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3546944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7498944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83152960 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 160000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3855296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28386264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 162496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 145216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3634496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27952240 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430656 # Number of bytes read from this memory +system.physmem.bytes_read::total 64872776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3855296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3634496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7489792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83283200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83173540 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 61750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 446616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 55421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 435459 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6280 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1015270 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1299265 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83303780 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2500 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 60239 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 443543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2269 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56789 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 436759 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6729 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1013650 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1301300 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1301838 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 76949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 556538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 69063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 542638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1265156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 76949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 69063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 146012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1619071 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1303873 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 75125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 553143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 544686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1264130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 75125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 145948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1622881 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1619471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1619071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 76949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 556939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 69063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 542638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2884628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1015270 # Number of read requests accepted -system.physmem.writeReqs 1929008 # Number of write requests accepted -system.physmem.readBursts 1015270 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1929008 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64941248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36032 # Total number of bytes read from write queue -system.physmem.bytesWritten 123000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64976456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 123312420 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 563 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7116 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 37405 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 61592 # Per bank write bursts -system.physmem.perBankRdBursts::1 63105 # Per bank write bursts -system.physmem.perBankRdBursts::2 59504 # Per bank write bursts -system.physmem.perBankRdBursts::3 58627 # Per bank write bursts -system.physmem.perBankRdBursts::4 63182 # Per bank write bursts -system.physmem.perBankRdBursts::5 72471 # Per bank write bursts -system.physmem.perBankRdBursts::6 63664 # Per bank write bursts -system.physmem.perBankRdBursts::7 61386 # Per bank write bursts -system.physmem.perBankRdBursts::8 55404 # Per bank write bursts -system.physmem.perBankRdBursts::9 84358 # Per bank write bursts -system.physmem.perBankRdBursts::10 61903 # Per bank write bursts -system.physmem.perBankRdBursts::11 68457 # Per bank write bursts -system.physmem.perBankRdBursts::12 58658 # Per bank write bursts -system.physmem.perBankRdBursts::13 64087 # Per bank write bursts -system.physmem.perBankRdBursts::14 58698 # Per bank write bursts -system.physmem.perBankRdBursts::15 59611 # Per bank write bursts -system.physmem.perBankWrBursts::0 118843 # Per bank write bursts -system.physmem.perBankWrBursts::1 118980 # Per bank write bursts -system.physmem.perBankWrBursts::2 119959 # Per bank write bursts -system.physmem.perBankWrBursts::3 120276 # Per bank write bursts -system.physmem.perBankWrBursts::4 119980 # Per bank write bursts -system.physmem.perBankWrBursts::5 124689 # Per bank write bursts -system.physmem.perBankWrBursts::6 121042 # Per bank write bursts -system.physmem.perBankWrBursts::7 120315 # Per bank write bursts -system.physmem.perBankWrBursts::8 116178 # Per bank write bursts -system.physmem.perBankWrBursts::9 121715 # Per bank write bursts -system.physmem.perBankWrBursts::10 120153 # Per bank write bursts -system.physmem.perBankWrBursts::11 124890 # Per bank write bursts -system.physmem.perBankWrBursts::12 118317 # Per bank write bursts -system.physmem.perBankWrBursts::13 123673 # Per bank write bursts -system.physmem.perBankWrBursts::14 117041 # Per bank write bursts -system.physmem.perBankWrBursts::15 115838 # Per bank write bursts +system.physmem.bw_write::total 1623282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1622881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 75125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 553544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 544686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2887412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1013650 # Number of read requests accepted +system.physmem.writeReqs 1930075 # Number of write requests accepted +system.physmem.readBursts 1013650 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1930075 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 64838144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35456 # Total number of bytes read from write queue +system.physmem.bytesWritten 120356480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 64872776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 123380708 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49498 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 37388 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 61871 # Per bank write bursts +system.physmem.perBankRdBursts::1 62981 # Per bank write bursts +system.physmem.perBankRdBursts::2 60043 # Per bank write bursts +system.physmem.perBankRdBursts::3 58309 # Per bank write bursts +system.physmem.perBankRdBursts::4 58023 # Per bank write bursts +system.physmem.perBankRdBursts::5 70636 # Per bank write bursts +system.physmem.perBankRdBursts::6 62371 # Per bank write bursts +system.physmem.perBankRdBursts::7 61877 # Per bank write bursts +system.physmem.perBankRdBursts::8 57508 # Per bank write bursts +system.physmem.perBankRdBursts::9 84884 # Per bank write bursts +system.physmem.perBankRdBursts::10 63101 # Per bank write bursts +system.physmem.perBankRdBursts::11 65471 # Per bank write bursts +system.physmem.perBankRdBursts::12 60660 # Per bank write bursts +system.physmem.perBankRdBursts::13 66399 # Per bank write bursts +system.physmem.perBankRdBursts::14 58532 # Per bank write bursts +system.physmem.perBankRdBursts::15 60430 # Per bank write bursts +system.physmem.perBankWrBursts::0 115217 # Per bank write bursts +system.physmem.perBankWrBursts::1 115969 # Per bank write bursts +system.physmem.perBankWrBursts::2 118272 # Per bank write bursts +system.physmem.perBankWrBursts::3 117255 # Per bank write bursts +system.physmem.perBankWrBursts::4 115771 # Per bank write bursts +system.physmem.perBankWrBursts::5 124355 # Per bank write bursts +system.physmem.perBankWrBursts::6 120059 # Per bank write bursts +system.physmem.perBankWrBursts::7 119259 # Per bank write bursts +system.physmem.perBankWrBursts::8 113485 # Per bank write bursts +system.physmem.perBankWrBursts::9 118397 # Per bank write bursts +system.physmem.perBankWrBursts::10 117107 # Per bank write bursts +system.physmem.perBankWrBursts::11 118510 # Per bank write bursts +system.physmem.perBankWrBursts::12 116303 # Per bank write bursts +system.physmem.perBankWrBursts::13 122603 # Per bank write bursts +system.physmem.perBankWrBursts::14 113656 # Per bank write bursts +system.physmem.perBankWrBursts::15 114352 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 47 # Number of times write queue was full causing retry -system.physmem.totGap 51358447292000 # Total gap between requests +system.physmem.numWrRetry 644 # Number of times write queue was full causing retry +system.physmem.totGap 51318117066500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1015255 # Read request sizes (log2) +system.physmem.readPktSize::6 1013635 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1926435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 609091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 267826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 93793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1927502 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 564185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 294633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 102008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 45915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -162,210 +162,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 38881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 81306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 107299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 121019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 120126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 130475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 126860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 129040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 115411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 107895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 107384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 92996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 90709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 88958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 633988 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.443718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.837628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.480307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 262069 41.34% 41.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 150940 23.81% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56528 8.92% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28800 4.54% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20482 3.23% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13112 2.07% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10788 1.70% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9843 1.55% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 81426 12.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 633988 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79397 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.779954 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 57.830581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 79390 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 718 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 101978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 95256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 108517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 90319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 86324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 81769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2118 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 627585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.090291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.534210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.652886 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 259317 41.32% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149298 23.79% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56496 9.00% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28437 4.53% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21665 3.45% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12676 2.02% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11310 1.80% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8646 1.38% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 79740 12.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 627585 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69573 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.561338 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 62.076495 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 69566 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79397 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.206066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.327441 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 16.891492 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 78 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 11 0.01% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.01% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 74 0.09% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 53395 67.25% 67.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2838 3.57% 71.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 719 0.91% 71.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6583 8.29% 80.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7477 9.42% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1320 1.66% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1452 1.83% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 838 1.06% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 841 1.06% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 314 0.40% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 349 0.44% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 180 0.23% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 342 0.43% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 280 0.35% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 234 0.29% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 238 0.30% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 362 0.46% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 134 0.17% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 99 0.12% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 90 0.11% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 295 0.37% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 94 0.12% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 72 0.09% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 132 0.17% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 106 0.13% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 42 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 41 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 32 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 104 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 22 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 10 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 22 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 21 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 15 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 11 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 20 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 17 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 9 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79397 # Writes before turning the bus around for reads -system.physmem.totQLat 27026112263 # Total ticks spent queuing -system.physmem.totMemAccLat 46051868513 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5073535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26634.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 69573 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69573 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.030170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.998159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 37.100716 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 59064 84.90% 84.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 4267 6.13% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4153 5.97% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 990 1.42% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 298 0.43% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 151 0.22% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 89 0.13% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 92 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 109 0.16% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 106 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 80 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 57 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 25 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 19 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 14 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1600-1631 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69573 # Writes before turning the bus around for reads +system.physmem.totQLat 27603415095 # Total ticks spent queuing +system.physmem.totMemAccLat 46598965095 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5065480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27246.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45384.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45996.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 2.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.31 # Average write queue length when enqueuing -system.physmem.readRowHits 781715 # Number of row buffer hits during reads -system.physmem.writeRowHits 1520891 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes -system.physmem.avgGap 17443477.58 # Average gap between requests -system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2437517880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1329994875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3927541800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6247264320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1237564295100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29729485998000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34335476748615 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.545842 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49457442122001 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.19 # Average write queue length when enqueuing +system.physmem.readRowHits 781690 # Number of row buffer hits during reads +system.physmem.writeRowHits 1484389 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.93 # Row buffer hit rate for writes +system.physmem.avgGap 17433054.06 # Average gap between requests +system.physmem.pageHitRate 78.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2390683680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1304440500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3869626800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6131097360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1233875646405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29708521981500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34307943272085 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.534751 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49422598441359 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713624640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 186034306749 # Time in different power states +system.physmem_0.memoryStateTime::ACT 181894714141 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2355431400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1285205625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3987126000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6206576400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235795450580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29731037607750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34335151534395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.539510 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49460023829001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem_1.actEnergy 2353858920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1284347625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4032475200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6054996240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1235994503985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29706663342750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34308233320560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.540403 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49419482573169 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713624640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183452804499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 185010821331 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -395,15 +360,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 134182977 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91246699 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5930019 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 92418572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 65829087 # Number of BTB hits +system.cpu0.branchPred.lookups 133240776 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90773806 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5898398 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90806413 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 65300191 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.229284 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17386110 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187768 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.911431 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17271308 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187435 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -434,97 +399,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 898809 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 898809 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17395 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94113 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 544060 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 354749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2049.828188 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 11956.771667 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 349905 98.63% 98.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 2560 0.72% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 1330 0.37% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 450 0.13% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 167 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 126 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 45 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 59 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 16 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 24 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 354749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 411281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21163.528109 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16798.259479 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15588.127658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 367100 89.26% 89.26% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 39499 9.60% 98.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2985 0.73% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 830 0.20% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 180 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 394 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 143 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 73 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 14 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 17 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 411281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 359646036796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.131612 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.643594 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 358749976796 99.75% 99.75% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 501279000 0.14% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 178636500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 105104000 0.03% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 41922000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 20797500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 20431000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 22734000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 4793500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 308500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walks 900960 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 900960 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16847 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91388 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 546326 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 354634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2141.455698 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12590.575916 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 352292 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1866 0.53% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 247 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 95 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 68 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 354634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 411836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21432.646658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17288.307814 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16337.255715 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 405278 98.41% 98.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5723 1.39% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 333 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 332 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 90 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 39 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 411836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 323720569592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.132299 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.681450 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 322818413592 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 497609500 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 179612000 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 106469500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 44651500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 21065000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 19836500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 27755000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 4822000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 304000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 19500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::44-47 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 3500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 359646036796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94113 84.40% 84.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17395 15.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 111508 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 898809 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::48-51 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 323720569592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 91388 84.43% 84.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16847 15.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 108235 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 900960 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 898809 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111508 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 900960 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108235 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111508 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1010317 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108235 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1009195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106848795 # DTB read hits -system.cpu0.dtb.read_misses 623268 # DTB read misses -system.cpu0.dtb.write_hits 83024984 # DTB write hits -system.cpu0.dtb.write_misses 275541 # DTB write misses -system.cpu0.dtb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 105886901 # DTB read hits +system.cpu0.dtb.read_misses 623655 # DTB read misses +system.cpu0.dtb.write_hits 81874264 # DTB write hits +system.cpu0.dtb.write_misses 277305 # DTB write misses +system.cpu0.dtb.flush_tlb 1077 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56194 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 160 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9669 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 54719 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 205 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9949 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56033 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 107472063 # DTB read accesses -system.cpu0.dtb.write_accesses 83300525 # DTB write accesses +system.cpu0.dtb.perms_faults 55268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106510556 # DTB read accesses +system.cpu0.dtb.write_accesses 82151569 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 189873779 # DTB hits -system.cpu0.dtb.misses 898809 # DTB misses -system.cpu0.dtb.accesses 190772588 # DTB accesses +system.cpu0.dtb.hits 187761165 # DTB hits +system.cpu0.dtb.misses 900960 # DTB misses +system.cpu0.dtb.accesses 188662125 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -554,673 +508,680 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 108604 # Table walker walks requested -system.cpu0.itb.walker.walksLong 108604 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3026 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 75552 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14309 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 94295 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1394.214964 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8384.902945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 93563 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 326 0.35% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 303 0.32% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 55 0.06% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 94295 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 92887 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25650.201395 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21071.590317 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17522.957706 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 91125 98.10% 98.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1488 1.60% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 173 0.19% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 92887 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 604413242668 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.909243 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.287630 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 54912274056 9.09% 9.09% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 549448743612 90.91% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 47582500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4106500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 406500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 604413242668 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 75552 96.15% 96.15% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3026 3.85% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 78578 # Table walker page sizes translated +system.cpu0.itb.walker.walks 103995 # Table walker walks requested +system.cpu0.itb.walker.walksLong 103995 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2920 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70184 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 13953 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 90042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1564.791986 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9356.128105 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 89344 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 299 0.33% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 238 0.26% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 101 0.11% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 90042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 87057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26438.085553 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21999.622082 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18398.516639 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48630 55.86% 55.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 36690 42.14% 98.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 630 0.72% 98.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 790 0.91% 99.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 103 0.12% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 96 0.11% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 24 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 87057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 276399275336 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.905006 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -250074257964 -90.48% -90.48% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 526414060300 190.45% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 52102500 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6093500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 943000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 232500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 42500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::7 59000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 276399275336 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 70184 96.01% 96.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2920 3.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 73104 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108604 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108604 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 103995 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 103995 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78578 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78578 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 187182 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 96451691 # ITB inst hits -system.cpu0.itb.inst_misses 108604 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73104 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73104 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 177099 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 95374234 # ITB inst hits +system.cpu0.itb.inst_misses 103995 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1077 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 42484 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40386 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204587 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 207806 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 96560295 # ITB inst accesses -system.cpu0.itb.hits 96451691 # DTB hits -system.cpu0.itb.misses 108604 # DTB misses -system.cpu0.itb.accesses 96560295 # DTB accesses -system.cpu0.numCycles 678169162 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 95478229 # ITB inst accesses +system.cpu0.itb.hits 95374234 # DTB hits +system.cpu0.itb.misses 103995 # DTB misses +system.cpu0.itb.accesses 95478229 # DTB accesses +system.cpu0.numCycles 670757384 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 248888472 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 597668364 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 134182977 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83215197 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 388705337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13495131 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2539677 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 21156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 4430 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5365960 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 171714 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 96228071 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3656691 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 42208 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 652445982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.071952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.318616 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 244295585 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 592642803 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 133240776 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82571499 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 387821427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13413764 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2417197 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3440 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5441880 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 164758 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2028 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 95148929 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3635106 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41714 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 646873994 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.071808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.317751 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 504779765 77.37% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18600914 2.85% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18675892 2.86% 83.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13601130 2.08% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28939785 4.44% 89.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9186194 1.41% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9881419 1.51% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8590984 1.32% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40189899 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 500514392 77.37% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18314774 2.83% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18453367 2.85% 83.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13440049 2.08% 85.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 29078999 4.50% 89.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9061143 1.40% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9714650 1.50% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8499613 1.31% 93.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39797007 6.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 652445982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.197861 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.881297 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 202230502 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 323725330 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 107157055 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13964232 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5366791 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19957602 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1400195 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 652122035 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4310941 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5366791 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 210017200 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 28890111 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 254295095 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 113145299 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 40729265 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 636448025 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 83808 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2425012 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1797238 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 20704845 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 5054 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 608929978 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 980367872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 752692960 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 918645 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 510273791 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 98656187 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15296129 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13303285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78526904 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102548023 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 87419598 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13782768 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14655222 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 603808817 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15342366 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 603678166 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 829707 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 77491896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 54214041 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 352970 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 652445982 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.925254 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.646571 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 646873994 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.198642 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.883543 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 198183326 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 323426019 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105981621 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13950733 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5329290 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19638547 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1397625 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 646526277 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4318123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5329290 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 205971985 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23697587 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259101155 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111995163 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 40775442 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 631047036 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 83751 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2209243 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1613560 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 20761963 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3444 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 605295621 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 976490610 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 746368883 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 733214 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 508351996 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96943625 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15774650 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13795198 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78408950 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101681556 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86254396 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13698017 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14540360 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598113520 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15856672 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 599090036 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 857856 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 76035125 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 52627296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 360655 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 646873994 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.926131 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.649248 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 415092251 63.62% 63.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100237257 15.36% 78.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 44034564 6.75% 85.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31483239 4.83% 90.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23657330 3.63% 94.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16258445 2.49% 96.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10998020 1.69% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6466609 0.99% 99.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4218267 0.65% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 410738698 63.50% 63.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100810060 15.58% 79.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43443549 6.72% 85.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31018554 4.80% 90.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22931602 3.54% 94.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16104373 2.49% 96.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11033021 1.71% 98.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6462279 1.00% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4331858 0.67% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 652445982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 646873994 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3031745 25.47% 25.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22352 0.19% 25.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2380 0.02% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4899657 41.16% 66.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3948703 33.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2999808 25.24% 25.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22948 0.19% 25.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2663 0.02% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4871857 40.99% 66.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3988147 33.55% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408914830 67.74% 67.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1483700 0.25% 67.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67594 0.01% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 189 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 10 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 26 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 67735 0.01% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 109003987 18.06% 86.06% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84140078 13.94% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 406422040 67.84% 67.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1476912 0.25% 68.09% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65361 0.01% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 96 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 58788 0.01% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108073598 18.04% 86.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82993236 13.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 603678166 # Type of FU issued -system.cpu0.iq.rate 0.890159 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11904839 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019721 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1871435984 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 696824280 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 580857585 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1100876 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 525941 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 475487 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 614994656 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 588349 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4797344 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 599090036 # Type of FU issued +system.cpu0.iq.rate 0.893155 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11885426 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019839 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1856813329 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 690194574 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 576693438 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 984019 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 484790 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 438468 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 610449620 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 525838 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4726109 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16957941 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 22519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 718505 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 9238289 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16731454 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 21127 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 684950 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 9161643 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3918093 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8730401 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3853062 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8592397 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5366791 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15638409 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 11458161 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 619287399 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1818065 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102548023 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 87419598 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13010956 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 256814 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11089494 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 718505 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2724850 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2330540 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5055390 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 596785117 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106839289 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6007087 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5329290 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14836046 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7169747 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 614106722 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1810261 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 101681556 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86254396 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13499171 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 248453 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6830033 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 684950 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2723761 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2339558 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5063319 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 592213762 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105878130 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5990174 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136216 # number of nop insts executed -system.cpu0.iew.exec_refs 189866682 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110402162 # Number of branches executed -system.cpu0.iew.exec_stores 83027393 # Number of stores executed -system.cpu0.iew.exec_rate 0.879994 # Inst execution rate -system.cpu0.iew.wb_sent 582539449 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 581333072 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286508471 # num instructions producing a value -system.cpu0.iew.wb_consumers 497555384 # num instructions consuming a value +system.cpu0.iew.exec_nop 136530 # number of nop insts executed +system.cpu0.iew.exec_refs 187756937 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109862908 # Number of branches executed +system.cpu0.iew.exec_stores 81878807 # Number of stores executed +system.cpu0.iew.exec_rate 0.882903 # Inst execution rate +system.cpu0.iew.wb_sent 578421970 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 577131906 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 284711853 # num instructions producing a value +system.cpu0.iew.wb_consumers 494921051 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.857210 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575832 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.860418 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575267 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 83249738 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14989396 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4548973 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 638320811 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.839633 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.833868 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 81841846 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15496017 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4520537 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 632994694 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.840706 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.831217 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 441333872 69.14% 69.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97259629 15.24% 84.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33853962 5.30% 89.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15327337 2.40% 92.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10781377 1.69% 93.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6688169 1.05% 94.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6042869 0.95% 95.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4086388 0.64% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22947208 3.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 436057133 68.89% 68.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 98370072 15.54% 84.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33369017 5.27% 89.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15116509 2.39% 92.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10820224 1.71% 93.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6529796 1.03% 94.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6075579 0.96% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3929496 0.62% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22726868 3.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 638320811 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 456208771 # Number of instructions committed -system.cpu0.commit.committedOps 535955511 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 632994694 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453175477 # Number of instructions committed +system.cpu0.commit.committedOps 532162399 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 163771391 # Number of memory references committed -system.cpu0.commit.loads 85590082 # Number of loads committed -system.cpu0.commit.membars 3686850 # Number of memory barriers committed -system.cpu0.commit.branches 101715990 # Number of branches committed -system.cpu0.commit.fp_insts 455933 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 492018334 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13342246 # Number of function calls committed. +system.cpu0.commit.refs 162042855 # Number of memory references committed +system.cpu0.commit.loads 84950102 # Number of loads committed +system.cpu0.commit.membars 3716655 # Number of memory barriers committed +system.cpu0.commit.branches 101218853 # Number of branches committed +system.cpu0.commit.fp_insts 419354 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 488117298 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13243427 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 370951931 69.21% 69.21% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1123996 0.21% 69.42% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 50135 0.01% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 58016 0.01% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 85590082 15.97% 85.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 78181309 14.59% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 368889724 69.32% 69.32% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1132190 0.21% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48139 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 49491 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84950102 15.96% 85.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77092753 14.49% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 535955511 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22947208 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 532162399 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22726868 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1230638929 # The number of ROB reads -system.cpu0.rob.rob_writes 1252557383 # The number of ROB writes -system.cpu0.timesIdled 4102528 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25723180 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 48923483834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 456208771 # Number of Instructions Simulated -system.cpu0.committedOps 535955511 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.486532 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.486532 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.672706 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.672706 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 703703491 # number of integer regfile reads -system.cpu0.int_regfile_writes 414789220 # number of integer regfile writes -system.cpu0.fp_regfile_reads 851205 # number of floating regfile reads -system.cpu0.fp_regfile_writes 517790 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127713204 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128825628 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2353610328 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15112961 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10694855 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.983549 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 305873629 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10695367 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.598703 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 310.817389 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 201.166160 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.392903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 1220262369 # The number of ROB reads +system.cpu0.rob.rob_writes 1241914021 # The number of ROB writes +system.cpu0.timesIdled 4040058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23883390 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 52531652861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 453175477 # Number of Instructions Simulated +system.cpu0.committedOps 532162399 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.480127 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.480127 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.675618 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.675618 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 698520758 # number of integer regfile reads +system.cpu0.int_regfile_writes 411524007 # number of integer regfile writes +system.cpu0.fp_regfile_reads 797183 # number of floating regfile reads +system.cpu0.fp_regfile_writes 468068 # number of floating regfile writes +system.cpu0.cc_regfile_reads 128308023 # number of cc regfile reads +system.cpu0.cc_regfile_writes 129504102 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2335799510 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15629054 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10737693 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983333 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 307043958 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10738205 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.593602 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1675743000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 201.777727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 310.205606 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.394097 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.605870 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999967 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1351414929 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1351414929 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 81475453 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80033887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 161509340 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68849485 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67022058 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135871543 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201211 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202496 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403707 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171344 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 154502 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 325846 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1773976 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1825826 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3599802 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028728 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2086704 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4115432 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150324938 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 147055945 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 297380883 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150526149 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 147258441 # number of overall hits -system.cpu0.dcache.overall_hits::total 297784590 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6522961 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6552499 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 13075460 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6494487 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6576721 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13071208 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 662604 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 664801 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1327405 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 630242 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 610465 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1240707 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 318489 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 320942 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 639431 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13017448 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 13129220 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 26146668 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13680052 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13794021 # number of overall misses -system.cpu0.dcache.overall_misses::total 27474073 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112227265953 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112380964165 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 224608230118 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 258123381451 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 251959078660 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 510082460111 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 25291195259 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 24024875532 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 49316070791 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4598532454 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4591438187 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 9189970641 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 148500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 161500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 370350647404 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 364340042825 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 734690690229 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 370350647404 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 364340042825 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 734690690229 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87998414 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 86586386 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 174584800 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75343972 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 73598779 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2028729 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2086710 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4115439 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163342386 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 160185165 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 323527551 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164206201 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 161052462 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 325258663 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074126 # 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miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765616 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.804943 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.778814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.791950 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.144308 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.150854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35279.041112 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 29835.411019 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28593.641157 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 29228.139909 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13079.492784 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13139.193191 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13110.778969 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20833.333333 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 36500 # 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mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033364 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032917 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014457 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759266 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759942 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759604 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782045 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793348 # 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number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94575387722 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 92152667283 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 186728055005 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2796204500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2965118250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5761322750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2832162536 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2783504957 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5615667493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5628367036 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5748623207 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11376990243 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032815 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033059 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014995 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014475 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014733 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.761663 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755707 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.800632 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.774480 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787627 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057363 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061662 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059523 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024883 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029027 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028510 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15000.673188 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14972.371413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14986.584314 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35159.717866 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36015.262834 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35582.758692 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17078.393965 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15926.861070 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16536.642214 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 28287.454175 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27031.444341 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27673.285099 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13055.948447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13229.633878 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13146.355055 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23250 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20587.715150 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20748.222191 # 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number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 95136564 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 96213978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 191350542 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 95136564 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 96213978 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 191350542 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 95136564 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 96213978 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 191350542 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090562 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091081 # 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average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13105.901195 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13106.661525 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13107.434865 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13105.901195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13106.661525 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 82244 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 6230 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 6699 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10.675602 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.277056 # 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number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8063215 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8111594 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16174809 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8063215 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 8111594 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16174809 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8063215 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 8111594 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16174809 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94312224420 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 94761792489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 189074016909 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94312224420 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 94761792489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 189074016909 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94312224420 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 94761792489 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 189074016909 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 916338250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 595537750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1511876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 916338250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 595537750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1511876000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084567 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084567 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084567 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.412648 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.412648 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.412648 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 602016 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 607287 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1209303 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 602016 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 607287 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1209303 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 602016 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 607287 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1209303 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8013787 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8155949 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16169736 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8013787 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8155949 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16169736 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95968094429 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 97614087232 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 193582181661 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95968094429 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 97614087232 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 193582181661 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 951349751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 639066000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1590415751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 951349751 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 639066000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1590415751 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084503 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084503 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084503 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11971.882637 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1369,15 +1330,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 132595782 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89991047 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5894262 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90157022 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 64704998 # Number of BTB hits +system.cpu1.branchPred.lookups 133788555 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5908759 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 92439735 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65341745 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.769227 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17429206 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189878 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 70.685777 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17599042 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188594 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1407,95 +1368,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 890417 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 890417 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17386 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91593 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 535956 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 354461 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2058.191169 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12119.324471 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 349672 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2519 0.71% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 1342 0.38% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 424 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 149 0.04% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 114 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 10 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 354461 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 404532 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20689.820452 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16434.872295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15113.304602 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 363916 89.96% 89.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 36589 9.04% 99.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 2703 0.67% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 595 0.15% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 189 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 278 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 138 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 43 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 30 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 404532 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 334236526020 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.086173 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.625283 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 333380386520 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 477486500 0.14% 99.89% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 168839000 0.05% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 100636500 0.03% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 41145500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 20471500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 20409500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 23342000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 3487500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 317500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 334236526020 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91594 84.05% 84.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17386 15.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108980 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 890417 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 918015 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 918015 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17288 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94464 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 562013 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 356002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2214.229134 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13073.684616 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 353584 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1851 0.52% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 299 0.08% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 120 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 79 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 356002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 421643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21453.513266 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17357.718896 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16015.202358 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 415023 98.43% 98.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 5756 1.37% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 364 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 366 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 33 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 421643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 354035793664 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.135779 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.675726 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 353071895664 99.73% 99.73% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 535230500 0.15% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 190116000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 115191500 0.03% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 44312000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 22451500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 21588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 29378000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5201500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 359000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 41000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 354035793664 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94465 84.53% 84.53% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17288 15.47% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 111753 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918015 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 890417 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108980 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918015 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111753 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108980 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 999397 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111753 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1029768 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 105460349 # DTB read hits -system.cpu1.dtb.read_misses 614707 # DTB read misses -system.cpu1.dtb.write_hits 81263219 # DTB write hits -system.cpu1.dtb.write_misses 275710 # DTB write misses -system.cpu1.dtb.flush_tlb 1092 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 105548583 # DTB read hits +system.cpu1.dtb.read_misses 631805 # DTB read misses +system.cpu1.dtb.write_hits 82907544 # DTB write hits +system.cpu1.dtb.write_misses 286210 # DTB write misses +system.cpu1.dtb.flush_tlb 1083 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55487 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 238 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9789 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56278 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9625 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106075056 # DTB read accesses -system.cpu1.dtb.write_accesses 81538929 # DTB write accesses +system.cpu1.dtb.perms_faults 55021 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106180388 # DTB read accesses +system.cpu1.dtb.write_accesses 83193754 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 186723568 # DTB hits -system.cpu1.dtb.misses 890417 # DTB misses -system.cpu1.dtb.accesses 187613985 # DTB accesses +system.cpu1.dtb.hits 188456127 # DTB hits +system.cpu1.dtb.misses 918015 # DTB misses +system.cpu1.dtb.accesses 189374142 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1525,392 +1481,399 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 101825 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101825 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2978 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69124 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 13788 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 88037 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1472.687620 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8948.821118 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 87265 99.12% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 389 0.44% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 275 0.31% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 88037 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 85890 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25260.851287 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20589.361475 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17130.840101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 84234 98.07% 98.07% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1438 1.67% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 145 0.17% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 40 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 85890 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 299874193152 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.837074 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -250957583628 -83.69% -83.69% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 550779312780 183.67% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 46468000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5344000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 484000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 65500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 54500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 299874193152 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69124 95.87% 95.87% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2978 4.13% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72102 # Table walker page sizes translated +system.cpu1.itb.walker.walks 104751 # Table walker walks requested +system.cpu1.itb.walker.walksLong 104751 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2979 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 72067 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14103 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 90648 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1509.569985 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8604.112743 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 89986 99.27% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 255 0.28% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 242 0.27% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 116 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 90648 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 89149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26484.081515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22228.139492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17447.399907 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 48433 54.33% 54.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 39159 43.93% 98.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 575 0.64% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 708 0.79% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 80 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 45 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 89149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 396982969624 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.388871 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -154312061728 -38.87% -38.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 551239764852 138.86% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 48839000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5683000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 518000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 149500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::7 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::8 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::9 8500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::10 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 396982969624 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 72067 96.03% 96.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2979 3.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 75046 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101825 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101825 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104751 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104751 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72102 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72102 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 173927 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95285493 # ITB inst hits -system.cpu1.itb.inst_misses 101825 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 75046 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 75046 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 179797 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 96448537 # ITB inst hits +system.cpu1.itb.inst_misses 104751 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1092 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1083 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40874 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 42139 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205822 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 204302 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95387318 # ITB inst accesses -system.cpu1.itb.hits 95285493 # DTB hits -system.cpu1.itb.misses 101825 # DTB misses -system.cpu1.itb.accesses 95387318 # DTB accesses -system.cpu1.numCycles 677360427 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 96553288 # ITB inst accesses +system.cpu1.itb.hits 96448537 # DTB hits +system.cpu1.itb.misses 104751 # DTB misses +system.cpu1.itb.accesses 96553288 # DTB accesses +system.cpu1.numCycles 667631540 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 248549507 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 588684684 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132595782 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82134204 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 389145480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13431349 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2335492 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 20294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4597 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5447640 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 169416 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95058557 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3668998 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 40025 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 652389771 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.056521 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.304488 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 247941482 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 595071407 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133788555 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82940787 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 381163571 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13497944 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2492160 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22589 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 3825 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5325029 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 172051 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 1992 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 96222293 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3665245 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41130 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643871402 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.082515 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.328245 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 506719262 77.67% 77.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18449281 2.83% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18323109 2.81% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13434339 2.06% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28729534 4.40% 89.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8986163 1.38% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9758970 1.50% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8450464 1.30% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39538649 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 496782409 77.16% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18583795 2.89% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18517016 2.88% 82.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13597412 2.11% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28667245 4.45% 89.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9152993 1.42% 90.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9918803 1.54% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8570268 1.33% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40081461 6.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 652389771 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.195754 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.869086 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201147393 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 326816283 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105097642 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 14007460 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5318954 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19647868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1416154 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 641757938 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4369017 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5318954 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 208911045 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28047403 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 258823969 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 111174433 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 40111705 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 626286274 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 89729 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2292362 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1848085 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19940508 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 5105 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 599962292 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 966932024 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 740689310 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 881849 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 503173353 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96788934 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15525446 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13560324 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 79127309 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101049697 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85573282 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13915572 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14825014 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 593826390 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15642550 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 594476204 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 818225 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 76136612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53142905 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356951 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 652389771 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.911229 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.632553 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643871402 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200393 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.891317 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201631753 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 315887121 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 107474204 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13522341 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5353840 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 20035378 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1415024 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 649950843 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4347472 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5353840 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 209303047 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22542941 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 254388545 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 113174340 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39106401 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 634340427 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 84329 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1777036 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1562975 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19949989 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3657 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 605941232 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 974899397 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 750081260 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 811718 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 508709616 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97231611 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15188925 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13206274 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 75533982 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 102194667 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 87314859 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13957552 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14774854 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 601797044 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15287986 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 601499543 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 865295 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 76155843 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52376442 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 362406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643871402 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.934192 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.656161 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 416908971 63.90% 63.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 100667120 15.43% 79.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43571359 6.68% 86.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31041594 4.76% 90.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23116047 3.54% 94.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15866958 2.43% 96.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10833871 1.66% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6331428 0.97% 99.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4052423 0.62% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 408171960 63.39% 63.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99067431 15.39% 78.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 44002532 6.83% 85.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31313283 4.86% 90.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23144485 3.59% 94.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16264635 2.53% 96.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11075626 1.72% 98.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6519272 1.01% 99.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4312178 0.67% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 652389771 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643871402 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2996828 25.66% 25.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24624 0.21% 25.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2734 0.02% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 3 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4869636 41.69% 67.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3787065 32.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3037678 26.20% 26.20% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 24339 0.21% 26.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2694 0.02% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4607398 39.74% 66.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3921783 33.83% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 402964828 67.78% 67.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1445986 0.24% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66608 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 132 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 61370 0.01% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 107585906 18.10% 86.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82351372 13.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 408162511 67.86% 67.86% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1426997 0.24% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69303 0.01% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 134 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 22 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 70416 0.01% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 107729216 17.91% 86.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 84040920 13.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 594476204 # Type of FU issued -system.cpu1.iq.rate 0.877636 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11680890 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019649 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1852781725 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 685800777 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 571863197 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1059569 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 502092 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 457373 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 605590748 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 566345 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4749876 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 601499543 # Type of FU issued +system.cpu1.iq.rate 0.900945 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11593896 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019275 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1858238935 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 693444958 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 579923061 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1090744 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 536293 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 488146 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 612510547 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 582891 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4820885 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16757289 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 22108 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 708788 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9117452 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16648209 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 23106 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 751890 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9224511 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3937125 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8714130 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4009170 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7426024 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5318954 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15381414 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 10835277 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 609605144 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1787029 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101049697 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85573282 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13260611 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 256865 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 10466220 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 708788 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2676587 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2314011 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4990598 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 587727574 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 105451218 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5872593 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5353840 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14516681 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6539646 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 617219827 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1819635 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 102194667 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 87314859 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12911400 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 240081 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6211315 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 751890 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2725767 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2332140 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5057907 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 594561904 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 105538370 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6033124 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 136204 # number of nop insts executed -system.cpu1.iew.exec_refs 186716455 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109034476 # Number of branches executed -system.cpu1.iew.exec_stores 81265237 # Number of stores executed -system.cpu1.iew.exec_rate 0.867673 # Inst execution rate -system.cpu1.iew.wb_sent 573536970 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 572320570 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281697554 # num instructions producing a value -system.cpu1.iew.wb_consumers 489376492 # num instructions consuming a value +system.cpu1.iew.exec_nop 134797 # number of nop insts executed +system.cpu1.iew.exec_refs 188445888 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110364560 # Number of branches executed +system.cpu1.iew.exec_stores 82907518 # Number of stores executed +system.cpu1.iew.exec_rate 0.890554 # Inst execution rate +system.cpu1.iew.wb_sent 581679133 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 580411207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 286057076 # num instructions producing a value +system.cpu1.iew.wb_consumers 496538403 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.844928 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575625 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.869359 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.576103 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 81905872 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15285599 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4497270 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 638458448 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.826393 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.816586 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 81975668 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14925580 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4513358 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 629946041 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.849503 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.842378 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 442788562 69.35% 69.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 97620349 15.29% 84.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33589881 5.26% 89.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 14950626 2.34% 92.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10704317 1.68% 93.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6546690 1.03% 94.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5838446 0.91% 95.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3972340 0.62% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22447237 3.52% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433603733 68.83% 68.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96615693 15.34% 84.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33704251 5.35% 89.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15419971 2.45% 91.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10970958 1.74% 93.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6585832 1.05% 94.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6182969 0.98% 95.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3954863 0.63% 96.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22907771 3.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 638458448 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 448865132 # Number of instructions committed -system.cpu1.commit.committedOps 527617659 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 629946041 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 455165016 # Number of instructions committed +system.cpu1.commit.committedOps 535141123 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160748237 # Number of memory references committed -system.cpu1.commit.loads 84292407 # Number of loads committed -system.cpu1.commit.membars 3769330 # Number of memory barriers committed -system.cpu1.commit.branches 100442689 # Number of branches committed -system.cpu1.commit.fp_insts 439800 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 484228202 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13335340 # Number of function calls committed. +system.cpu1.commit.refs 163636805 # Number of memory references committed +system.cpu1.commit.loads 85546457 # Number of loads committed +system.cpu1.commit.membars 3765916 # Number of memory barriers committed +system.cpu1.commit.branches 101697828 # Number of branches committed +system.cpu1.commit.fp_insts 467953 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 491500354 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13521989 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 365655543 69.30% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1112211 0.21% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49677 0.01% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 51991 0.01% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84292407 15.98% 85.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76455830 14.49% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 370285651 69.19% 69.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1106053 0.21% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 52121 0.01% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 60451 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85546457 15.99% 85.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78090348 14.59% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 527617659 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22447237 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 535141123 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22907771 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1221498833 # The number of ROB reads -system.cpu1.rob.rob_writes 1232997569 # The number of ROB writes -system.cpu1.timesIdled 4096806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24970656 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 52437515063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 448865132 # Number of Instructions Simulated -system.cpu1.committedOps 527617659 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.509051 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.509051 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.662668 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.662668 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 693047790 # number of integer regfile reads -system.cpu1.int_regfile_writes 408438474 # number of integer regfile writes -system.cpu1.fp_regfile_reads 823112 # number of floating regfile reads -system.cpu1.fp_regfile_writes 494780 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126134775 # number of cc regfile reads -system.cpu1.cc_regfile_writes 127188255 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2330176021 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15424448 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40375 # Transaction distribution -system.iobus.trans_dist::ReadResp 40375 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.cpu1.rob.rob_reads 1220174232 # The number of ROB reads +system.cpu1.rob.rob_writes 1248183780 # The number of ROB writes +system.cpu1.timesIdled 4134360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23760138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 48765821681 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 455165016 # Number of Instructions Simulated +system.cpu1.committedOps 535141123 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.466790 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.466790 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.681761 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.681761 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 701277155 # number of integer regfile reads +system.cpu1.int_regfile_writes 414494210 # number of integer regfile writes +system.cpu1.fp_regfile_reads 871148 # number of floating regfile reads +system.cpu1.fp_regfile_writes 523684 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126609999 # number of cc regfile reads +system.cpu1.cc_regfile_writes 127812398 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2340278076 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15057964 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1925,13 +1888,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1946,13 +1909,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1980,71 +1943,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042399628 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607055505 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 178994733 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148389509 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.429644 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.425424 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090563453000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.541528 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.888116 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221346 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430507 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651853 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090073143000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544298 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881126 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221519 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430070 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039614 # Number of tag accesses -system.iocache.tags.data_accesses 1039614 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses -system.iocache.demand_misses::total 8849 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8809 # number of overall misses -system.iocache.overall_misses::total 8849 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1920259350 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1925744350 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28938987545 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28938987545 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1920259350 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1926083350 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1920259350 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1926083350 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1661250694 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1666322694 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19868709302 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19868709302 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1661250694 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1666675194 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1661250694 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1666675194 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2058,55 +2021,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217988.347145 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217696.625593 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271309.790979 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271309.790979 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217661.131201 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217661.131201 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 227974 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188521.413300 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188306.327721 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186273.806551 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186273.806551 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 188282.330999 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 188282.330999 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 113607 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27752 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16342 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.214687 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.951842 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1462065868 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1465626868 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23392010493 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23392010493 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1462065868 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1465809868 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1462065868 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1465809868 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201855604 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1204997604 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322073410 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322073410 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1201855604 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1205191104 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1201855604 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1205191104 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2120,292 +2083,297 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165974.102395 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165682.440425 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219305.581011 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219305.581011 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136388.516114 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136173.308170 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134272.795039 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134272.795039 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1414814 # number of replacements -system.l2c.tags.tagsinuse 65356.208679 # Cycle average of tags in use -system.l2c.tags.total_refs 31586438 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1477430 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.379313 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2484527000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35855.564521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 171.544585 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 252.706280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3390.645466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10658.750636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 169.049447 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 250.456312 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3915.870098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10691.621334 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.547112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003856 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.162640 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003822 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.163141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997257 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 354 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 353 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2774 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5014 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53845 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005402 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.950043 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 297087469 # Number of tag accesses -system.l2c.tags.data_accesses 297087469 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 549429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 200595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 8013735 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3471974 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 542581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 184113 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 8064127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3507527 # number of ReadReq hits -system.l2c.ReadReq_hits::total 24534081 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8181117 # number of Writeback hits -system.l2c.Writeback_hits::total 8181117 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347604 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 365500 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 713104 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4965 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5155 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10120 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 785554 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 813200 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1598754 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 549429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 200595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8013735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4257528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 542581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 184113 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8064127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4320727 # number of demand (read+write) hits -system.l2c.demand_hits::total 26132835 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 549429 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 200595 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8013735 # number of overall hits -system.l2c.overall_hits::cpu0.data 4257528 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 542581 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 184113 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8064127 # number of overall hits -system.l2c.overall_hits::cpu1.data 4320727 # number of overall hits -system.l2c.overall_hits::total 26132835 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2398 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 49272 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 160159 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2534 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2288 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 47310 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 159515 # number of ReadReq misses -system.l2c.ReadReq_misses::total 426096 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 279272 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 241385 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 520657 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18107 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18517 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36624 # number of UpgradeReq misses +system.l2c.tags.replacements 1412518 # number of replacements +system.l2c.tags.tagsinuse 65354.490513 # Cycle average of tags in use +system.l2c.tags.total_refs 31645259 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1474766 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.457817 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2643820000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35783.123237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 158.967100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 249.670952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3744.975731 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12205.230455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 164.981843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 255.022053 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3435.700252 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9356.818889 # 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average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 25126437764 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 25538778563 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 50665216327 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 175148007 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 3515798206 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 38109128474 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173430261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3520714460 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 37282073062 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 83165388240 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 175148007 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 3515798206 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 38109128474 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173430261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3520714460 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 37282073062 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 83165388240 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 735361248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2566401000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 493860500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2722892250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6518514998 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2597122000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2578592496 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5175714496 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 735361248 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5163523000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 493860500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5301484746 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11694229494 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.043862 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.041745 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016817 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.440910 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.400404 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.421103 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.789433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781944 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.785682 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.256599 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.267015 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.261750 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036374 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036374 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 79682.628798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77675.511291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77355.208270 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33717.092556 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34183.846403 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33934.108791 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17759.726624 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17756.082251 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17757.910111 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83846.404002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 83507.798698 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 83680.233686 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89351.153103 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89221.557305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 89285.780821 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2619,57 +2591,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 489224 # Transaction distribution -system.membus.trans_dist::ReadResp 489224 # Transaction distribution -system.membus.trans_dist::WriteReq 33860 # Transaction distribution -system.membus.trans_dist::WriteResp 33860 # Transaction distribution -system.membus.trans_dist::Writeback 1299265 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 627170 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 627170 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37411 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37412 # Transaction distribution -system.membus.trans_dist::ReadExReq 563054 # Transaction distribution -system.membus.trans_dist::ReadExResp 563054 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 483310 # Transaction distribution +system.membus.trans_dist::ReadResp 483310 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::Writeback 1301300 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 626202 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 626202 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37394 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37396 # Transaction distribution +system.membus.trans_dist::ReadExReq 566817 # Transaction distribution +system.membus.trans_dist::ReadExResp 566817 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4332246 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4462384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4797472 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4328173 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4457819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4793358 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174236076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174408348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14052800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14052800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188461148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3233 # Total snoops (count) -system.membus.snoop_fanout::samples 2961771 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174172012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174343786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14081472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2786 # Total snoops (count) +system.membus.snoop_fanout::samples 2961350 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2961771 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2961350 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2961771 # Request fanout histogram -system.membus.reqLayer0.occupancy 99708500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2961350 # Request fanout histogram +system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5504999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5469002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18802986477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11041524273 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10120184001 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6008607805 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186568267 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151555991 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2680,11 +2652,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2713,58 +2685,56 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 25574289 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25566182 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33860 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33860 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8181117 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1340428 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1233761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46747 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46754 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2162441 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2162441 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32390529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29801361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 923404 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2600212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 65715506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036485248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1208333724 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3115152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8777312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2256711436 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 667123 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37442651 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003085 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.055458 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 25599599 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25591523 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8209351 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1340869 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1234101 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46602 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46614 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2167911 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2167911 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32380531 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29914539 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 911927 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2596271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 65803268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036169984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1212884202 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3059264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 669395 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37310136 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003099 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.055581 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 37327135 99.69% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115516 0.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 37194516 99.69% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115620 0.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37442651 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 56492183787 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 37310136 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3327000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 72944134855 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 43405971950 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 537017212 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24319536063 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 15088594286 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 530670154 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1517407654 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1505035766 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16420 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16426 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index b93c1aabd..943a39f7a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.861398 # Number of seconds simulated -sim_ticks 51861397612000 # Number of ticks simulated -final_tick 51861397612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.824541 # Number of seconds simulated +sim_ticks 51824540977500 # Number of ticks simulated +final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682840 # Simulator instruction rate (inst/s) -host_op_rate 802417 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40752483757 # Simulator tick rate (ticks/s) -host_mem_usage 728928 # Number of bytes of host memory used -host_seconds 1272.59 # Real time elapsed on the host -sim_insts 868978236 # Number of instructions simulated -sim_ops 1021151568 # Number of ops (including micro ops) simulated +host_inst_rate 650287 # Simulator instruction rate (inst/s) +host_op_rate 764161 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37795835393 # Simulator tick rate (ticks/s) +host_mem_usage 728296 # Number of bytes of host memory used +host_seconds 1371.17 # Real time elapsed on the host +sim_insts 891654507 # Number of instructions simulated +sim_ops 1047794539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 110912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 113344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2519016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 22396080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 118144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 113984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2612108 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 22226264 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 390656 # Number of bytes read from this memory -system.physmem.bytes_read::total 50600508 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2519016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2612108 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5131124 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71823424 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 127104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 129344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2579072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24306544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 138752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 130240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2657396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 26223832 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 397184 # Number of bytes read from this memory +system.physmem.bytes_read::total 56689468 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2579072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2657396 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5236468 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77843520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 71844004 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 66774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 349942 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 53807 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 347295 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6104 # Number of read requests responded to by this memory -system.physmem.num_reads::total 831053 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1122241 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77864100 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1986 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 409757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6206 # Number of read requests responded to by this memory +system.physmem.num_reads::total 926193 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1216305 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124814 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 48572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 431845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 428570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 975687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 48572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 98939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1384911 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1218878 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 49765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 469016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 506012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1093873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 49765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1502059 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1385308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1384911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 48572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 431845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 428967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2360995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 831053 # Number of read requests accepted -system.physmem.writeReqs 1733697 # Number of write requests accepted -system.physmem.readBursts 831053 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1733697 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 53155264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 32128 # Total number of bytes read from write queue -system.physmem.bytesWritten 110517504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 50600508 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 110812516 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 502 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6857 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35215 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 52772 # Per bank write bursts -system.physmem.perBankRdBursts::1 58055 # Per bank write bursts -system.physmem.perBankRdBursts::2 48746 # Per bank write bursts -system.physmem.perBankRdBursts::3 51625 # Per bank write bursts -system.physmem.perBankRdBursts::4 50901 # Per bank write bursts -system.physmem.perBankRdBursts::5 53731 # Per bank write bursts -system.physmem.perBankRdBursts::6 47545 # Per bank write bursts -system.physmem.perBankRdBursts::7 46576 # Per bank write bursts -system.physmem.perBankRdBursts::8 47759 # Per bank write bursts -system.physmem.perBankRdBursts::9 90120 # Per bank write bursts -system.physmem.perBankRdBursts::10 47452 # Per bank write bursts -system.physmem.perBankRdBursts::11 51057 # Per bank write bursts -system.physmem.perBankRdBursts::12 47939 # Per bank write bursts -system.physmem.perBankRdBursts::13 45720 # Per bank write bursts -system.physmem.perBankRdBursts::14 43868 # Per bank write bursts -system.physmem.perBankRdBursts::15 46685 # Per bank write bursts -system.physmem.perBankWrBursts::0 110572 # Per bank write bursts -system.physmem.perBankWrBursts::1 116599 # Per bank write bursts -system.physmem.perBankWrBursts::2 110707 # Per bank write bursts -system.physmem.perBankWrBursts::3 112437 # Per bank write bursts -system.physmem.perBankWrBursts::4 109828 # Per bank write bursts -system.physmem.perBankWrBursts::5 113045 # Per bank write bursts -system.physmem.perBankWrBursts::6 105073 # Per bank write bursts -system.physmem.perBankWrBursts::7 102356 # Per bank write bursts -system.physmem.perBankWrBursts::8 103784 # Per bank write bursts -system.physmem.perBankWrBursts::9 107644 # Per bank write bursts -system.physmem.perBankWrBursts::10 104570 # Per bank write bursts -system.physmem.perBankWrBursts::11 108123 # Per bank write bursts -system.physmem.perBankWrBursts::12 106842 # Per bank write bursts -system.physmem.perBankWrBursts::13 106503 # Per bank write bursts -system.physmem.perBankWrBursts::14 103411 # Per bank write bursts -system.physmem.perBankWrBursts::15 105342 # Per bank write bursts +system.physmem.bw_write::total 1502456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1502059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 49765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 469016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 506409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2596329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 926193 # Number of read requests accepted +system.physmem.writeReqs 1833424 # Number of write requests accepted +system.physmem.readBursts 926193 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1833424 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59238720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37632 # Total number of bytes read from write queue +system.physmem.bytesWritten 114125056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56689468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117195044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 588 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50220 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36075 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58169 # Per bank write bursts +system.physmem.perBankRdBursts::1 57047 # Per bank write bursts +system.physmem.perBankRdBursts::2 56978 # Per bank write bursts +system.physmem.perBankRdBursts::3 51307 # Per bank write bursts +system.physmem.perBankRdBursts::4 56070 # Per bank write bursts +system.physmem.perBankRdBursts::5 62899 # Per bank write bursts +system.physmem.perBankRdBursts::6 54110 # Per bank write bursts +system.physmem.perBankRdBursts::7 52791 # Per bank write bursts +system.physmem.perBankRdBursts::8 52847 # Per bank write bursts +system.physmem.perBankRdBursts::9 102886 # Per bank write bursts +system.physmem.perBankRdBursts::10 57805 # Per bank write bursts +system.physmem.perBankRdBursts::11 59371 # Per bank write bursts +system.physmem.perBankRdBursts::12 53186 # Per bank write bursts +system.physmem.perBankRdBursts::13 52009 # Per bank write bursts +system.physmem.perBankRdBursts::14 46290 # Per bank write bursts +system.physmem.perBankRdBursts::15 51840 # Per bank write bursts +system.physmem.perBankWrBursts::0 107643 # Per bank write bursts +system.physmem.perBankWrBursts::1 108842 # Per bank write bursts +system.physmem.perBankWrBursts::2 112436 # Per bank write bursts +system.physmem.perBankWrBursts::3 109534 # Per bank write bursts +system.physmem.perBankWrBursts::4 114716 # Per bank write bursts +system.physmem.perBankWrBursts::5 117944 # Per bank write bursts +system.physmem.perBankWrBursts::6 106840 # Per bank write bursts +system.physmem.perBankWrBursts::7 109826 # Per bank write bursts +system.physmem.perBankWrBursts::8 110854 # Per bank write bursts +system.physmem.perBankWrBursts::9 118905 # Per bank write bursts +system.physmem.perBankWrBursts::10 115046 # Per bank write bursts +system.physmem.perBankWrBursts::11 114249 # Per bank write bursts +system.physmem.perBankWrBursts::12 112384 # Per bank write bursts +system.physmem.perBankWrBursts::13 111972 # Per bank write bursts +system.physmem.perBankWrBursts::14 104755 # Per bank write bursts +system.physmem.perBankWrBursts::15 107258 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 51861395055500 # Total gap between requests +system.physmem.numWrRetry 141 # Number of times write queue was full causing retry +system.physmem.totGap 51824538352500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 787937 # Read request sizes (log2) +system.physmem.readPktSize::6 883077 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1731124 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 797504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 87 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1830851 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 891893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,206 +165,186 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 57139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 93845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 98521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 113672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 117695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 104272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 102286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 99994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 96711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 93700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 91898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 87418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 86273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 85861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 84522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.307984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.321614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.078407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 235457 41.76% 41.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 139953 24.82% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 46694 8.28% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25357 4.50% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16838 2.99% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11479 2.04% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8496 1.51% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7843 1.39% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 71672 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563789 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 84234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.859653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 88.079162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 84229 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 57426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 60838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 91061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 116478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 105808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 96280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 97400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 91891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 93113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 91599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 96823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 95841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 93430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 103137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 92354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5718 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 235 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 605479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.324474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.442500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.472553 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 252649 41.73% 41.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 150060 24.78% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52055 8.60% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27939 4.61% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19251 3.18% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12886 2.13% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9838 1.62% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9006 1.49% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71795 11.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 605479 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 88964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.404208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 91.787630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 88960 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 84234 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 84234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.500463 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.372295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.059087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 108 0.13% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 80 0.09% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 54 0.06% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 121 0.14% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 46153 54.79% 55.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 30225 35.88% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2462 2.92% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1364 1.62% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 933 1.11% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 416 0.49% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 269 0.32% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 164 0.19% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 538 0.64% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 68 0.08% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 77 0.09% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 53 0.06% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 0.19% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 54 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.03% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 79 0.09% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 145 0.17% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 43 0.05% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 17 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 33 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 176 0.21% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 15 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 19 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 61 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 20 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 40 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 24 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 103 0.12% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 13 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 84234 # Writes before turning the bus around for reads -system.physmem.totQLat 10578626250 # Total ticks spent queuing -system.physmem.totMemAccLat 26151457500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4152755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12736.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::21504-22527 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 88964 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 88964 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.044108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.711925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.727362 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 349 0.39% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 86750 97.51% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 775 0.87% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 22 0.02% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 52 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 153 0.17% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 193 0.22% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 316 0.36% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 104 0.12% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 25 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 21 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 53 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 28 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 13 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 22 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 88964 # Writes before turning the bus around for reads +system.physmem.totQLat 11987590194 # Total ticks spent queuing +system.physmem.totMemAccLat 29342683944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4628025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12951.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31486.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31701.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.05 # Average write queue length when enqueuing -system.physmem.readRowHits 620179 # Number of row buffer hits during reads -system.physmem.writeRowHits 1373418 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes -system.physmem.avgGap 20220838.31 # Average gap between requests -system.physmem.pageHitRate 77.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2224749240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1213900875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3197578800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5706398160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1303736226660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29973207455250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34676620370265 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.640359 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49862520204500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem.avgWrQLen 8.43 # Average write queue length when enqueuing +system.physmem.readRowHits 697250 # Number of row buffer hits during reads +system.physmem.writeRowHits 1406079 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes +system.physmem.avgGap 18779612.66 # Average gap between requests +system.physmem.pageHitRate 77.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2300840640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1255419000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3505093800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5752820880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384927046800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1312402504095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29943494064750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34653637789965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.672359 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49812972038958 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730535300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 267111145000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 281033227292 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2037495600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1111728750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3280680000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5483499120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1287848520900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29987144039250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34674240024900 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.594461 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49885777301500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem_1.actEnergy 2276580600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1242181875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3714586200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5802341040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384927046800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1307965107960 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29947386517500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34653314361975 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.666118 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49819438757970 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730535300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243849706000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 274566508280 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -418,68 +398,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 125209 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 125209 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 19669 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90325 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walks 132927 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 132927 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20422 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96268 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 125193 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 125193 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 125193 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 110010 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22089.371421 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18317.414501 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13164.465309 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 107059 97.32% 97.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2114 1.92% 99.24% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 606 0.55% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 110 0.10% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 25 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 28 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 110010 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 3295703864 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.071233 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -234762296 -7.12% -7.12% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 3530466160 107.12% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 3295703864 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90326 82.12% 82.12% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 19669 17.88% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 109995 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125209 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::samples 132911 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 132911 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 132911 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 116706 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23749.820061 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20399.632740 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13626.974720 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 115779 99.21% 99.21% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 796 0.68% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 50 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 35 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 34 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 116706 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 17050777148 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.002177 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -37117796 -0.22% -0.22% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 17087894944 100.22% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 17050777148 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 96268 82.50% 82.50% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 20422 17.50% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 116690 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 132927 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125209 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109995 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 132927 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116690 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109995 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 235204 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116690 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 249617 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 81853035 # DTB read hits -system.cpu0.dtb.read_misses 95759 # DTB read misses -system.cpu0.dtb.write_hits 74321037 # DTB write hits -system.cpu0.dtb.write_misses 29450 # DTB write misses -system.cpu0.dtb.flush_tlb 51862 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 83832092 # DTB read hits +system.cpu0.dtb.read_misses 101357 # DTB read misses +system.cpu0.dtb.write_hits 76051604 # DTB write hits +system.cpu0.dtb.write_misses 31570 # DTB write misses +system.cpu0.dtb.flush_tlb 51833 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 71205 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 523 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 72699 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4306 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4640 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9531 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 81948794 # DTB read accesses -system.cpu0.dtb.write_accesses 74350487 # DTB write accesses +system.cpu0.dtb.perms_faults 9921 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83933449 # DTB read accesses +system.cpu0.dtb.write_accesses 76083174 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 156174072 # DTB hits -system.cpu0.dtb.misses 125209 # DTB misses -system.cpu0.dtb.accesses 156299281 # DTB accesses +system.cpu0.dtb.hits 159883696 # DTB hits +system.cpu0.dtb.misses 132927 # DTB misses +system.cpu0.dtb.accesses 160016623 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,284 +485,286 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 77027 # Table walker walks requested -system.cpu0.itb.walker.walksLong 77027 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4349 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67368 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 77027 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 77027 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 77027 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 71717 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25312.366663 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21958.347721 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 14763.140629 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 66172 92.27% 92.27% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 4523 6.31% 98.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 706 0.98% 99.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 175 0.24% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 37 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 34 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 34 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 78456 # Table walker walks requested +system.cpu0.itb.walker.walksLong 78456 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68323 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 78456 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 78456 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78456 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72653 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26725.888828 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23461.567658 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16011.465624 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 35910 49.43% 49.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 35653 49.07% 98.50% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 362 0.50% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 571 0.79% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 51 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 28 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 22 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 71717 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -294463796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -294463796 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -294463796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67368 93.94% 93.94% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4349 6.06% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 71717 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72653 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294752296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294752296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294752296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 68323 94.04% 94.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4330 5.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72653 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77027 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77027 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78456 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78456 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71717 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71717 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 148744 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 434570813 # ITB inst hits -system.cpu0.itb.inst_misses 77027 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72653 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72653 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 151109 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 446243730 # ITB inst hits +system.cpu0.itb.inst_misses 78456 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51862 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51833 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 52030 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 523 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53592 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 434647840 # ITB inst accesses -system.cpu0.itb.hits 434570813 # DTB hits -system.cpu0.itb.misses 77027 # DTB misses -system.cpu0.itb.accesses 434647840 # DTB accesses -system.cpu0.numCycles 51862348340 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 446322186 # ITB inst accesses +system.cpu0.itb.hits 446243730 # DTB hits +system.cpu0.itb.misses 78456 # DTB misses +system.cpu0.itb.accesses 446322186 # DTB accesses +system.cpu0.numCycles 51824649281 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 434316413 # Number of instructions committed -system.cpu0.committedOps 510251172 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 468762245 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 455279 # Number of float alu accesses -system.cpu0.num_func_calls 25833192 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 66107864 # number of instructions that are conditional controls -system.cpu0.num_int_insts 468762245 # number of integer instructions -system.cpu0.num_fp_insts 455279 # number of float instructions -system.cpu0.num_int_register_reads 680505745 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371520195 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 735714 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 382992 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 113236512 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 112912982 # number of times the CC registers were written -system.cpu0.num_mem_refs 156164016 # number of memory refs -system.cpu0.num_load_insts 81849666 # Number of load instructions -system.cpu0.num_store_insts 74314350 # Number of store instructions -system.cpu0.num_idle_cycles 50300563806.190483 # Number of idle cycles -system.cpu0.num_busy_cycles 1561784533.809517 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030114 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969886 # Percentage of idle cycles -system.cpu0.Branches 96959859 # Number of branches fetched +system.cpu0.committedInsts 445966277 # Number of instructions committed +system.cpu0.committedOps 524229812 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 481463261 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 467774 # Number of float alu accesses +system.cpu0.num_func_calls 26556698 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68063516 # number of instructions that are conditional controls +system.cpu0.num_int_insts 481463261 # number of integer instructions +system.cpu0.num_fp_insts 467774 # number of float instructions +system.cpu0.num_int_register_reads 701970788 # number of times the integer registers were read +system.cpu0.num_int_register_writes 382111523 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 750606 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 404844 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 116882787 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 116605188 # number of times the CC registers were written +system.cpu0.num_mem_refs 159874579 # number of memory refs +system.cpu0.num_load_insts 83829017 # Number of load instructions +system.cpu0.num_store_insts 76045562 # Number of store instructions +system.cpu0.num_idle_cycles 50231597014.033707 # Number of idle cycles +system.cpu0.num_busy_cycles 1593052266.966292 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030739 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969261 # Percentage of idle cycles +system.cpu0.Branches 99615402 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 353181248 69.18% 69.18% # Class of executed instruction -system.cpu0.op_class::IntMult 1084077 0.21% 69.39% # Class of executed instruction -system.cpu0.op_class::IntDiv 49491 0.01% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 8 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 12 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55978 0.01% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::MemRead 81849666 16.03% 85.44% # Class of executed instruction -system.cpu0.op_class::MemWrite 74314350 14.56% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 363413760 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 1135542 0.22% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 49216 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 60094 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 83829017 15.98% 85.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 76045562 14.50% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 510534837 # Class of executed instruction +system.cpu0.op_class::total 524533192 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16221 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 9866178 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.969728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 301750178 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9866690 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.582716 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.086465 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.883263 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566575 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433366 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 16327 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 10196087 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.965694 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 309323716 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10196599 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.335969 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3500850250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 229.651609 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 282.314085 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.448538 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.551395 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1256728908 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1256728908 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 76588751 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 76163346 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152752097 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70555546 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 70327464 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 140883010 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190561 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 196148 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 386709 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 172423 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 161036 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 333459 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1750003 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1777885 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3527888 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1897893 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1924897 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3822790 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147144297 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 146490810 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 293635107 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147334858 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 146686958 # number of overall hits -system.cpu0.dcache.overall_hits::total 294021816 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2557843 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2571612 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 5129455 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1050273 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1078042 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2128315 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601274 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 625393 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1226667 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 620770 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607819 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1228589 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148787 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 147781 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 296568 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1288720346 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1288720346 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 78289930 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78118799 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156408729 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72116454 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 72389955 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 144506409 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198225 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 194517 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392742 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 165535 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 168546 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 334081 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1870803 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1796237 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3667040 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2023404 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1945934 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3969338 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150406384 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 150508754 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 300915138 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150604609 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 150703271 # number of overall hits +system.cpu0.dcache.overall_hits::total 301307880 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2655491 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2654704 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 5310195 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1102314 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1104773 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2207087 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 646482 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 651674 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1298156 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 617789 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 615381 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1233170 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153457 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 150527 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 303984 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3608116 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3649654 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7257770 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4209390 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 4275047 # number of overall misses -system.cpu0.dcache.overall_misses::total 8484437 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39628260752 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 40050042255 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 79678303007 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29258978305 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 29205004656 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 58463982961 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 13856629500 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13463537506 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27320167006 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2109696250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2149698750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4259395000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 75000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 101501 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 68887239057 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 69255046911 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 138142285968 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 68887239057 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 69255046911 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 138142285968 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79146594 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 78734958 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 157881552 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71605819 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 71405506 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 143011325 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 791835 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 821541 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1613376 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 793193 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 768855 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1562048 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1898790 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1925666 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3824456 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897894 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1924898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3822792 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150752413 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 150140464 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 300892877 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 151544248 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 24499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 97499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60992790193 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 61337961589 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 122330751782 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 69935488193 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 70538281839 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 140473770032 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2674956999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3053270500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728227499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2550639000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3023463750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574102750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5225595999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6076734250 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302330249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032274 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032622 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032448 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014524 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014734 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759163 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761017 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760107 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782622 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.790551 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786524 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060022 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058193 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059101 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3739535 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3740366 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7479901 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4385256 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4391055 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8776311 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37598794000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37923223247 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 75522017247 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30337029302 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31768716886 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 62105746188 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 9761049258 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10401680524 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20162729782 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 15601809495 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 15341092999 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 30942902494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1519625500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1476118000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2995743500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67935823302 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69691940133 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 137627763435 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77696872560 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 80093620657 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 157790493217 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2993163000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2758056250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5751219250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2831783000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2786803750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5618586750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5824946000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5544860000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11369806000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032711 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032760 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032735 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014911 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014888 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014900 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.764432 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.768962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.766699 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.788676 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.784998 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786836 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058091 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023843 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024214 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024028 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027685 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028224 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027954 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13410.508275 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13497.816624 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13454.282609 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25707.961856 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24993.058039 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25345.926006 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14876.429802 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14715.638581 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.455897 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20321.680332 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20150.570308 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20237.027186 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12039.190482 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12315.565322 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12176.210796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24499 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 48749.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16968.705506 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16871.714483 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16919.934166 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16668.928151 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16555.340246 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16611.696325 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024257 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024246 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024251 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028290 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028308 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028299 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14200.098649 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14331.433565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14265.745925 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27787.498525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29033.499894 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28411.199742 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15116.512020 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15985.640642 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15552.741634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 25254.268844 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 24929.422584 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25092.162876 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12922.974547 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12845.079492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12884.474943 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18166.917358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18632.385209 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,79 +905,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13777264 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.892662 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 855737357 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13777776 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 62.109977 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 32072682250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.033427 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.859235 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535222 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464569 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999790 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13976964 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 878227495 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13977476 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.831622 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 35142475250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 257.003288 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 254.876744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.501960 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.497806 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 883292919 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 883292919 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 427701374 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 428035983 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 855737357 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 427701374 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 428035983 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 855737357 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 427701374 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 428035983 # number of overall hits -system.cpu0.icache.overall_hits::total 855737357 # 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average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1086,73 +1064,73 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 127972 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 127972 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 19780 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92740 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 127956 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.265716 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 71.272998 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 127954 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 130358 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 130358 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20442 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94115 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 130351 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.276177 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 74.962722 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 130349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 127956 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 112536 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22019.187193 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18129.081838 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13444.450617 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 109487 97.29% 97.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2144 1.91% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 659 0.59% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 117 0.10% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 32 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 27 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 112536 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 6637919892 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.174468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1158102796 -17.45% -17.45% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 7796022688 117.45% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 6637919892 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 92740 82.42% 82.42% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 19780 17.58% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 112520 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127972 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 130351 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 114564 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23894.842621 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 20601.133760 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13695.118153 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 72946 63.67% 63.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 40612 35.45% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 507 0.44% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 353 0.31% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 47 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 10 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 28 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 114564 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 26318568 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 31.814872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -811003296 -3081.49% -3081.49% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 837321864 3181.49% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 26318568 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94116 82.16% 82.16% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20442 17.84% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 114558 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 130358 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127972 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 130358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 114558 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112520 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 240492 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 114558 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 244916 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 81500118 # DTB read hits -system.cpu1.dtb.read_misses 97955 # DTB read misses -system.cpu1.dtb.write_hits 74126007 # DTB write hits -system.cpu1.dtb.write_misses 30017 # DTB write misses -system.cpu1.dtb.flush_tlb 51868 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 83582440 # DTB read hits +system.cpu1.dtb.read_misses 99281 # DTB read misses +system.cpu1.dtb.write_hits 76249670 # DTB write hits +system.cpu1.dtb.write_misses 31077 # DTB write misses +system.cpu1.dtb.flush_tlb 51825 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 72099 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 21270 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 73142 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4473 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4747 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9907 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81598073 # DTB read accesses -system.cpu1.dtb.write_accesses 74156024 # DTB write accesses +system.cpu1.dtb.perms_faults 9967 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83681721 # DTB read accesses +system.cpu1.dtb.write_accesses 76280747 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 155626125 # DTB hits -system.cpu1.dtb.misses 127972 # DTB misses -system.cpu1.dtb.accesses 155754097 # DTB accesses +system.cpu1.dtb.hits 159832110 # DTB hits +system.cpu1.dtb.misses 130358 # DTB misses +system.cpu1.dtb.accesses 159962468 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1182,135 +1160,136 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 77421 # Table walker walks requested -system.cpu1.itb.walker.walksLong 77421 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4271 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67596 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 77421 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 77421 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 77421 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71867 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24990.746796 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21538.641816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14943.355403 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 66410 92.41% 92.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4449 6.19% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 690 0.96% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 184 0.26% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 29 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 30 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71867 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1257793296 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1257793296 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1257793296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 67596 94.06% 94.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4271 5.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71867 # Table walker page sizes translated +system.cpu1.itb.walker.walks 77021 # Table walker walks requested +system.cpu1.itb.walker.walksLong 77021 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4430 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67244 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 77021 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 77021 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 77021 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71674 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27071.277590 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23813.549051 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16581.978010 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 34935 48.74% 48.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 35570 49.63% 98.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 418 0.58% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 591 0.82% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 6 0.01% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 60 0.08% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 17 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 30 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 20 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71674 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -853687296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -853687296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -853687296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 67244 93.82% 93.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4430 6.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71674 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77421 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77021 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77021 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71867 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71867 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 149288 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 434944325 # ITB inst hits -system.cpu1.itb.inst_misses 77421 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 148695 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 445961246 # ITB inst hits +system.cpu1.itb.inst_misses 77021 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51868 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51825 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53256 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21270 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 52758 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 435021746 # ITB inst accesses -system.cpu1.itb.hits 434944325 # DTB hits -system.cpu1.itb.misses 77421 # DTB misses -system.cpu1.itb.accesses 435021746 # DTB accesses -system.cpu1.numCycles 51860446884 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 446038267 # ITB inst accesses +system.cpu1.itb.hits 445961246 # DTB hits +system.cpu1.itb.misses 77021 # DTB misses +system.cpu1.itb.accesses 446038267 # DTB accesses +system.cpu1.numCycles 51824432674 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 434661823 # Number of instructions committed -system.cpu1.committedOps 510900396 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 469262912 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 444776 # Number of float alu accesses -system.cpu1.num_func_calls 25944068 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66238146 # number of instructions that are conditional controls -system.cpu1.num_int_insts 469262912 # number of integer instructions -system.cpu1.num_fp_insts 444776 # number of float instructions -system.cpu1.num_int_register_reads 683773696 # number of times the integer registers were read -system.cpu1.num_int_register_writes 372368162 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 716331 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 377944 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113908068 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113630972 # number of times the CC registers were written -system.cpu1.num_mem_refs 155618629 # number of memory refs -system.cpu1.num_load_insts 81496317 # Number of load instructions -system.cpu1.num_store_insts 74122312 # Number of store instructions -system.cpu1.num_idle_cycles 50297346072.144875 # Number of idle cycles -system.cpu1.num_busy_cycles 1563100811.855124 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030141 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969859 # Percentage of idle cycles -system.cpu1.Branches 97056682 # Number of branches fetched +system.cpu1.committedInsts 445688230 # Number of instructions committed +system.cpu1.committedOps 523564727 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 480567684 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 428483 # Number of float alu accesses +system.cpu1.num_func_calls 26273151 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68126466 # number of instructions that are conditional controls +system.cpu1.num_int_insts 480567684 # number of integer instructions +system.cpu1.num_fp_insts 428483 # number of float instructions +system.cpu1.num_int_register_reads 701499135 # number of times the integer registers were read +system.cpu1.num_int_register_writes 381123451 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 693452 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 356440 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 117557193 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117240637 # number of times the CC registers were written +system.cpu1.num_mem_refs 159825990 # number of memory refs +system.cpu1.num_load_insts 83579816 # Number of load instructions +system.cpu1.num_store_insts 76246174 # Number of store instructions +system.cpu1.num_idle_cycles 50239290608.732407 # Number of idle cycles +system.cpu1.num_busy_cycles 1585142065.267594 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030587 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969413 # Percentage of idle cycles +system.cpu1.Branches 99529261 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 354376144 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 1097996 0.21% 69.54% # Class of executed instruction -system.cpu1.op_class::IntDiv 48675 0.01% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 5 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 9 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55297 0.01% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::MemRead 81496317 15.94% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 74122312 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 362846766 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 1082718 0.21% 69.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 48965 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 50459 0.01% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::MemRead 83579816 15.95% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 76246174 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 511196757 # Class of executed instruction +system.cpu1.op_class::total 523854940 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40404 # Transaction distribution -system.iobus.trans_dist::ReadResp 40404 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40327 # Transaction distribution +system.iobus.trans_dist::ReadResp 40327 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1325,13 +1304,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1346,13 +1325,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1380,71 +1359,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042408857 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606981976 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179045538 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148423298 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.461673 # Cycle average of tags in use +system.iocache.tags.replacements 115487 # number of replacements +system.iocache.tags.tagsinuse 10.456623 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115503 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154364038000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.508099 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.953575 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219256 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653855 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13157342382000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510546 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946077 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219409 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434130 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039875 # Number of tag accesses -system.iocache.tags.data_accesses 1039875 # Number of data accesses +system.iocache.tags.tag_accesses 1039911 # Number of tag accesses +system.iocache.tags.data_accesses 1039911 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses -system.iocache.demand_misses::total 8878 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses +system.iocache.demand_misses::total 8882 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8838 # number of overall misses -system.iocache.overall_misses::total 8878 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1903038512 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1908523512 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28811758807 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28811758807 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1903038512 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1908862512 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1903038512 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1908862512 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8842 # number of overall misses +system.iocache.overall_misses::total 8882 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1565914828 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1570986828 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19799416850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19799416850 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1565914828 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1571339328 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1565914828 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1571339328 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1458,55 +1437,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 215324.565739 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 215044.902761 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270116.991740 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270116.991740 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215010.420365 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215010.420365 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 222004 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 177099.618638 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 176932.855952 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185624.173573 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185624.173573 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 177099.618638 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 176912.781806 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 177099.618638 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 176912.781806 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 107527 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27403 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16113 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.101449 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.673307 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1443371512 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1446932512 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23265154883 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23265154883 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1443371512 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1447115512 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1443371512 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1447115512 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1105053392 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1108195392 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14252856882 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14252856882 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1105053392 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1108388892 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1105053392 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1108388892 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1520,290 +1499,291 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163314.269292 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 163034.649239 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218116.279935 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218116.279935 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 163314.269292 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 163000.170309 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 163314.269292 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 163000.170309 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 124977.764307 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 124810.833652 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133623.873866 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133623.873866 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 124977.764307 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 124790.462959 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 124977.764307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 124790.462959 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1193420 # number of replacements -system.l2c.tags.tagsinuse 65274.322363 # Cycle average of tags in use -system.l2c.tags.total_refs 27445630 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1256045 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.850833 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6379783000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38399.191078 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 165.877891 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 238.258282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3135.660678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9757.187471 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 161.764164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 237.073896 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3594.762150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9584.546752 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.585925 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002531 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.047846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.148883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003617 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054852 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.146249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996007 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62385 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2427 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5459 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54075 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.951920 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 260949842 # Number of tag accesses -system.l2c.tags.data_accesses 260949842 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 229115 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 164394 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6831894 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3141009 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 232266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 162523 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6868394 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3173246 # number of ReadReq hits -system.l2c.ReadReq_hits::total 20802841 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7621991 # number of Writeback hits -system.l2c.Writeback_hits::total 7621991 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 364580 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 361785 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 726365 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4737 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4832 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9569 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 795952 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 829496 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1625448 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 229115 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 164394 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6831894 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3936961 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 232266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 162523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6868394 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4002742 # number of demand (read+write) hits -system.l2c.demand_hits::total 22428289 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 229115 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 164394 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6831894 # number of overall hits -system.l2c.overall_hits::cpu0.data 3936961 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 232266 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 162523 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6868394 # number of overall hits -system.l2c.overall_hits::cpu1.data 4002742 # number of overall hits -system.l2c.overall_hits::total 22428289 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1733 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 37545 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 128493 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1846 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1781 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 39948 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 132523 # number of ReadReq misses -system.l2c.ReadReq_misses::total 345640 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63438.076824 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63067.648467 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21579.704516 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21598.571767 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21588.947374 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.762387 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.754287 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.761269 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61075.907990 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60985.278209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61031.289289 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.231584 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.248366 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.239985 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.084925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.091507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036940 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.084925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.091507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036940 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70584.855526 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71285.881179 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70730.178710 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31502.460477 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31502.184387 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 31502.324350 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17535.115563 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17534.651061 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17534.885097 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68338.774797 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68719.459499 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 68536.009295 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69123.439889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69123.439889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1997,57 +1977,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 431429 # Transaction distribution -system.membus.trans_dist::ReadResp 431429 # Transaction distribution -system.membus.trans_dist::WriteReq 33873 # Transaction distribution -system.membus.trans_dist::WriteResp 33873 # Transaction distribution -system.membus.trans_dist::Writeback 1122241 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 608883 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 608883 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35220 # Transaction distribution +system.membus.trans_dist::ReadReq 450083 # Transaction distribution +system.membus.trans_dist::ReadResp 450083 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::Writeback 1216305 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 614546 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 614546 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36081 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35222 # Transaction distribution -system.membus.trans_dist::ReadExReq 436846 # Transaction distribution -system.membus.trans_dist::ReadExResp 436846 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 36083 # Transaction distribution +system.membus.trans_dist::ReadExReq 513152 # Transaction distribution +system.membus.trans_dist::ReadExResp 513152 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3746179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3876375 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4211316 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4043368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4173072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4508118 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147371488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 147541836 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14041536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14041536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 161583372 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3431 # Total snoops (count) -system.membus.snoop_fanout::samples 2557707 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159836512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 160006362 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14048000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3335 # Total snoops (count) +system.membus.snoop_fanout::samples 2753479 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2557707 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2753479 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2557707 # Request fanout histogram -system.membus.reqLayer0.occupancy 107352000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2753479 # Request fanout histogram +system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5560499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5172000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16960886493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10421674858 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8211852015 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5445003775 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186625462 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151621202 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2091,55 +2071,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 21612149 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21604161 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7621991 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1335253 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1228589 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 44226 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 22091229 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22083154 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7866652 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1339933 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1233169 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45378 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44228 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2062852 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2062852 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27641812 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27580079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 784917 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1183820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 57190628 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881950484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1119524728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2643752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3719680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2007838644 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 494311 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 32599559 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003544 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.059428 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 45380 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2140586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2140586 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28041212 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28486273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 793018 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1241724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 58562227 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 894731284 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1156290950 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2684984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 492069 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 33406949 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003462 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.058735 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 32484017 99.65% 99.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 33291303 99.65% 99.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115646 0.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 32599559 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 51716744749 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3993000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 33406949 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 62067119757 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 39696027226 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 454863250 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 21033645158 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 14294630789 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 457872249 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 719296500 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 748277250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 2fadfdb24..daa556624 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.121937 # Number of seconds simulated -sim_ticks 5121937205500 # Number of ticks simulated -final_tick 5121937205500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.154240 # Number of seconds simulated +sim_ticks 5154239928000 # Number of ticks simulated +final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250170 # Simulator instruction rate (inst/s) -host_op_rate 494496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3139783576 # Simulator tick rate (ticks/s) -host_mem_usage 754660 # Number of bytes of host memory used -host_seconds 1631.30 # Real time elapsed on the host -sim_insts 408103625 # Number of instructions simulated -sim_ops 806672783 # Number of ops (including micro ops) simulated +host_inst_rate 177928 # Simulator instruction rate (inst/s) +host_op_rate 351699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2247974259 # Simulator tick rate (ticks/s) +host_mem_usage 809460 # Number of bytes of host memory used +host_seconds 2292.84 # Real time elapsed on the host +sim_insts 407959851 # Number of instructions simulated +sim_ops 806389826 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1046784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10762752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11842240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9571648 # Number of bytes written to this memory -system.physmem.bytes_written::total 9571648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16356 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168168 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory +system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185035 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149557 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2101305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2312063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1868755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1868755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1868755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2101305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4180818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185035 # Number of read requests accepted -system.physmem.writeReqs 196277 # Number of write requests accepted -system.physmem.readBursts 185035 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196277 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11833600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 12404928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11842240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12561728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2419 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1772 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11869 # Per bank write bursts -system.physmem.perBankRdBursts::1 11279 # Per bank write bursts -system.physmem.perBankRdBursts::2 11900 # Per bank write bursts -system.physmem.perBankRdBursts::3 11555 # Per bank write bursts -system.physmem.perBankRdBursts::4 12140 # Per bank write bursts -system.physmem.perBankRdBursts::5 11427 # Per bank write bursts -system.physmem.perBankRdBursts::6 11446 # Per bank write bursts -system.physmem.perBankRdBursts::7 11418 # Per bank write bursts -system.physmem.perBankRdBursts::8 11156 # Per bank write bursts -system.physmem.perBankRdBursts::9 11288 # Per bank write bursts -system.physmem.perBankRdBursts::10 11167 # Per bank write bursts -system.physmem.perBankRdBursts::11 11604 # Per bank write bursts -system.physmem.perBankRdBursts::12 11474 # Per bank write bursts -system.physmem.perBankRdBursts::13 12255 # Per bank write bursts -system.physmem.perBankRdBursts::14 11757 # Per bank write bursts -system.physmem.perBankRdBursts::15 11165 # Per bank write bursts -system.physmem.perBankWrBursts::0 12900 # Per bank write bursts -system.physmem.perBankWrBursts::1 13064 # Per bank write bursts -system.physmem.perBankWrBursts::2 11983 # Per bank write bursts -system.physmem.perBankWrBursts::3 10698 # Per bank write bursts -system.physmem.perBankWrBursts::4 10899 # Per bank write bursts -system.physmem.perBankWrBursts::5 11057 # Per bank write bursts -system.physmem.perBankWrBursts::6 11263 # Per bank write bursts -system.physmem.perBankWrBursts::7 11237 # Per bank write bursts -system.physmem.perBankWrBursts::8 11985 # Per bank write bursts -system.physmem.perBankWrBursts::9 12151 # Per bank write bursts -system.physmem.perBankWrBursts::10 12710 # Per bank write bursts -system.physmem.perBankWrBursts::11 12714 # Per bank write bursts -system.physmem.perBankWrBursts::12 13328 # Per bank write bursts -system.physmem.perBankWrBursts::13 13119 # Per bank write bursts -system.physmem.perBankWrBursts::14 12767 # Per bank write bursts -system.physmem.perBankWrBursts::15 11952 # Per bank write bursts +system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185029 # Number of read requests accepted +system.physmem.writeReqs 196407 # Number of write requests accepted +system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11576 # Per bank write bursts +system.physmem.perBankRdBursts::1 11057 # Per bank write bursts +system.physmem.perBankRdBursts::2 12153 # Per bank write bursts +system.physmem.perBankRdBursts::3 11198 # Per bank write bursts +system.physmem.perBankRdBursts::4 11802 # Per bank write bursts +system.physmem.perBankRdBursts::5 11348 # Per bank write bursts +system.physmem.perBankRdBursts::6 11143 # Per bank write bursts +system.physmem.perBankRdBursts::7 11153 # Per bank write bursts +system.physmem.perBankRdBursts::8 11425 # Per bank write bursts +system.physmem.perBankRdBursts::9 11213 # Per bank write bursts +system.physmem.perBankRdBursts::10 11332 # Per bank write bursts +system.physmem.perBankRdBursts::11 11504 # Per bank write bursts +system.physmem.perBankRdBursts::12 11762 # Per bank write bursts +system.physmem.perBankRdBursts::13 12902 # Per bank write bursts +system.physmem.perBankRdBursts::14 11974 # Per bank write bursts +system.physmem.perBankRdBursts::15 11385 # Per bank write bursts +system.physmem.perBankWrBursts::0 11439 # Per bank write bursts +system.physmem.perBankWrBursts::1 10429 # Per bank write bursts +system.physmem.perBankWrBursts::2 10485 # Per bank write bursts +system.physmem.perBankWrBursts::3 9453 # Per bank write bursts +system.physmem.perBankWrBursts::4 11713 # Per bank write bursts +system.physmem.perBankWrBursts::5 11103 # Per bank write bursts +system.physmem.perBankWrBursts::6 10277 # Per bank write bursts +system.physmem.perBankWrBursts::7 10587 # Per bank write bursts +system.physmem.perBankWrBursts::8 10639 # Per bank write bursts +system.physmem.perBankWrBursts::9 10347 # Per bank write bursts +system.physmem.perBankWrBursts::10 10880 # Per bank write bursts +system.physmem.perBankWrBursts::11 10311 # Per bank write bursts +system.physmem.perBankWrBursts::12 10712 # Per bank write bursts +system.physmem.perBankWrBursts::13 11096 # Per bank write bursts +system.physmem.perBankWrBursts::14 11110 # Per bank write bursts +system.physmem.perBankWrBursts::15 9917 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5121937091000 # Total gap between requests +system.physmem.numWrRetry 48 # Number of times write queue was full causing retry +system.physmem.totGap 5154239876000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185035 # Read request sizes (log2) +system.physmem.readPktSize::6 185029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196277 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196407 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,436 +156,415 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 229 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.753643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.995922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.769329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27720 37.03% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17254 23.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7564 10.10% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4205 5.62% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3013 4.02% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2021 2.70% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1360 1.82% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1151 1.54% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10579 14.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74867 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7807 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.681312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.837786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7806 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7175 # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27722 37.68% 37.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17426 23.68% 61.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7585 10.31% 71.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4195 5.70% 77.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1416 1.92% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1303 1.77% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7807 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.827334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.378246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.718812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6359 81.45% 81.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 60 0.77% 82.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.20% 82.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 274 3.51% 85.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 187 2.40% 88.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.64% 88.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 34 0.44% 89.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.53% 89.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 177 2.27% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.22% 92.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 12 0.15% 92.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.17% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 35 0.45% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.20% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.10% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 51 0.65% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 104 1.33% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 7 0.09% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 10 0.13% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 27 0.35% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 148 1.90% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.10% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.08% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 33 0.42% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 12 0.15% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.36% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.05% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.15% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 7 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.10% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 4 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7807 # Writes before turning the bus around for reads -system.physmem.totQLat 1977045500 # Total ticks spent queuing -system.physmem.totMemAccLat 5443920500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 924500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10692.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6767 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.195508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700984 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 42.210035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6335 93.62% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 84 1.24% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.25% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 17 0.25% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.28% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 20 0.30% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 33 0.49% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 32 0.47% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.38% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 8 0.12% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 61 0.90% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 50 0.74% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.18% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.01% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.13% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 14 0.21% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads +system.physmem.totQLat 2002245948 # Total ticks spent queuing +system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29442.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing -system.physmem.readRowHits 151994 # Number of row buffer hits during reads -system.physmem.writeRowHits 151865 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes -system.physmem.avgGap 13432404.67 # Average gap between requests -system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 281753640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 153734625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 725665200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 603294480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129490880310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2959572897750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3425368148085 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764386 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4923440733500 # Time in different power states -system.physmem_0.memoryStateTime::REF 171032680000 # Time in different power states +system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing +system.physmem.readRowHits 151945 # Number of row buffer hits during reads +system.physmem.writeRowHits 129899 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes +system.physmem.avgGap 13512725.27 # Average gap between requests +system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.747042 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states +system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27462249000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 284240880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 155091750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 716547000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 652704480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129160456155 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2959862743500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3425371705845 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.765080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4923925616750 # Time in different power states -system.physmem_1.memoryStateTime::REF 171032680000 # Time in different power states +system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.766215 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states +system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26978805250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86925803 # Number of BP lookups -system.cpu.branchPred.condPredicted 86925803 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 896443 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80098191 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78212465 # Number of BTB hits +system.cpu.branchPred.lookups 86886659 # Number of BP lookups +system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.645732 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1561001 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180305 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449601109 # number of cpu cycles simulated +system.cpu.numCycles 452015949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27685322 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429319828 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86925803 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79773466 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418005810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1881156 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 145066 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 56340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 216419 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 69 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 534 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9181154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 448969 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4854 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447050138 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.052352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281515886 62.97% 62.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2210439 0.49% 63.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72204596 16.15% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1602689 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2146844 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2305649 0.52% 80.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1524322 0.34% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1908424 0.43% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81631289 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447050138 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193340 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23043701 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264854286 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150758526 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7453047 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 940578 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838760021 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 940578 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25901615 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223330945 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13194802 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154665359 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29016839 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835288144 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 480498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12432167 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 195018 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13714744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997792221 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1814468169 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1115407405 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 373 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964705167 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33087052 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 465878 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 469687 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39083891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17351329 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10177979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1302580 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1089364 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829800190 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1202669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824540368 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243435 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23398238 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36211142 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 151712 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447050138 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.844402 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418243 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23349289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262726585 58.77% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13876357 3.10% 61.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10104726 2.26% 64.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6925504 1.55% 65.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74353941 16.63% 82.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4450821 1.00% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72845421 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1198612 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 568171 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447050138 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1991949 71.90% 71.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 123 0.00% 71.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1473 0.05% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 615411 22.21% 94.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161409 5.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 289852 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796144481 96.56% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150888 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125650 0.02% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 123 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18436778 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9392596 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824540368 # Type of FU issued -system.cpu.iq.rate 1.833938 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2770367 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003360 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2099144137 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854413357 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819991210 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 827020625 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1864655 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued +system.cpu.iq.rate 1.823454 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854027763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3351077 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13836 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14513 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1751193 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224299 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72996 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 940578 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205605732 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9422457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831002859 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153624 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17351329 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10177979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 705669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415252 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8108448 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14513 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 513988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 533382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1047370 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822936172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18038480 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1469642 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27207078 # number of memory reference insts executed -system.cpu.iew.exec_branches 83328554 # Number of branches executed -system.cpu.iew.exec_stores 9168598 # Number of stores executed -system.cpu.iew.exec_rate 1.830370 # Inst execution rate -system.cpu.iew.wb_sent 822433213 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819991395 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641244168 # num instructions producing a value -system.cpu.iew.wb_consumers 1050921658 # num instructions consuming a value +system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed +system.cpu.iew.exec_branches 83301836 # Number of branches executed +system.cpu.iew.exec_stores 9170146 # Number of stores executed +system.cpu.iew.exec_rate 1.819883 # Inst execution rate +system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640992347 # num instructions producing a value +system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610173 # average fanout of values written-back +system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24200169 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050957 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 908606 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443415424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675431 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272547704 61.47% 61.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11191107 2.52% 63.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3581688 0.81% 64.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74592593 16.82% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2424395 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1607477 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 945915 0.21% 82.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71066294 16.03% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5458251 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443415424 # Number of insts commited each cycle -system.cpu.commit.committedInsts 408103625 # Number of instructions committed -system.cpu.commit.committedOps 806672783 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407959851 # Number of instructions committed +system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22427037 # Number of memory references committed -system.cpu.commit.loads 14000251 # Number of loads committed -system.cpu.commit.membars 475479 # Number of memory barriers committed -system.cpu.commit.branches 82225235 # Number of branches committed +system.cpu.commit.refs 22418298 # Number of memory references committed +system.cpu.commit.loads 13992664 # Number of loads committed +system.cpu.commit.membars 471797 # Number of memory barriers committed +system.cpu.commit.branches 82198639 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735463006 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156113 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171674 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783810008 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145072 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121556 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735203522 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155963 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144976 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121468 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -612,167 +591,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13997671 1.74% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8426786 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806672783 # Class of committed instruction -system.cpu.commit.bw_lim_events 5458251 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction +system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268751952 # The number of ROB reads -system.cpu.rob.rob_writes 1665400460 # The number of ROB writes -system.cpu.timesIdled 293768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2550971 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9794270972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 408103625 # Number of Instructions Simulated -system.cpu.committedOps 806672783 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.101684 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.101684 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907702 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907702 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092990942 # number of integer regfile reads -system.cpu.int_regfile_writes 656343554 # number of integer regfile writes -system.cpu.fp_regfile_reads 191 # number of floating regfile reads -system.cpu.cc_regfile_reads 416454943 # number of cc regfile reads -system.cpu.cc_regfile_writes 322187827 # number of cc regfile writes -system.cpu.misc_regfile_reads 265705543 # number of misc regfile reads -system.cpu.misc_regfile_writes 400219 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1658771 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995092 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19161993 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659283 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.548357 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995092 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 1270729806 # The number of ROB reads +system.cpu.rob.rob_writes 1664729387 # The number of ROB writes +system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407959851 # Number of Instructions Simulated +system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092541258 # number of integer regfile reads +system.cpu.int_regfile_writes 656084038 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.cc_regfile_reads 416293281 # number of cc regfile reads +system.cpu.cc_regfile_writes 322054452 # number of cc regfile writes +system.cpu.misc_regfile_reads 265591845 # number of misc regfile reads +system.cpu.misc_regfile_writes 400328 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1659836 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.989699 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19130413 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1660348 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.521930 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.989699 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88441081 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88441081 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11011311 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11011311 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082990 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64916 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64916 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19094301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19094301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19159217 # number of overall hits -system.cpu.dcache.overall_hits::total 19159217 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1795762 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1795762 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334107 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334107 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406359 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406359 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2129869 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2129869 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2536228 # number of overall misses -system.cpu.dcache.overall_misses::total 2536228 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26474085005 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26474085005 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12834716256 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12834716256 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39308801261 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39308801261 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39308801261 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39308801261 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12807073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12807073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8417097 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8417097 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21224170 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21224170 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21695445 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21695445 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140216 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140216 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039694 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039694 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862255 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862255 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.116901 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.116901 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14742.535484 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14742.535484 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38414.987582 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38414.987582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18455.971358 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18455.971358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.922518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15498.922518 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 371080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39978 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.282105 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 88364873 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88364873 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10981747 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10981747 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8081553 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8081553 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 64328 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 64328 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19063300 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19063300 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19127628 # number of overall hits +system.cpu.dcache.overall_hits::total 19127628 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1807734 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1807734 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334390 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334390 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406367 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406367 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2142124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2142124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2548491 # number of overall misses +system.cpu.dcache.overall_misses::total 2548491 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27237843437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27237843437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13894605384 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13894605384 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41132448821 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41132448821 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41132448821 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41132448821 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12789481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12789481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8415943 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8415943 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 470695 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 470695 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21205424 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21205424 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21676119 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21676119 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.141345 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.141345 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039733 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039733 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863334 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.863334 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101018 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101018 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117571 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117571 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19201.712329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16139.923124 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 413510 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 44186 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.358394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560107 # number of writebacks -system.cpu.dcache.writebacks::total 1560107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 826960 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 826960 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44237 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44237 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 871197 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 871197 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 871197 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 871197 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968802 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968802 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289870 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289870 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402896 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402896 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1258672 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1258672 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1661568 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1661568 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12247021519 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12247021519 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11168468751 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11168468751 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5577776251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5577776251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23415490270 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23415490270 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993266521 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993266521 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97397501000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97397501000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2571147000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2571147000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99968648000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99968648000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075646 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075646 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854906 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854906 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059304 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059304 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076586 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076586 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561658 # number of writebacks +system.cpu.dcache.writebacks::total 1561658 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 837908 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 837908 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44444 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44444 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 882352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 882352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 882352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 882352 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969826 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969826 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289946 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289946 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402900 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402900 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1259772 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1259772 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1662672 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1662672 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12862571524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12862571524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12285238213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12285238213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5938147500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5938147500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25147809737 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25147809737 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31085957237 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31085957237 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97453049000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97453049000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2592894500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2592894500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855968 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855968 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059408 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059408 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076705 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076705 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -780,58 +759,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 75411 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.808771 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 114018 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 75427 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.511634 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.808771 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988048 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988048 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 73822 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.784353 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 116295 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 73836 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.575045 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.784353 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986522 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986522 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 457557 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 457557 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114018 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 114018 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114018 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 114018 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114018 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 114018 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 76507 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 76507 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 76507 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 76507 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 76507 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 76507 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935770691 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935770691 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935770691 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 935770691 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935770691 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 935770691 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190525 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190525 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190525 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190525 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190525 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190525 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.401559 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.401559 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.401559 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.401559 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.401559 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.401559 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177422 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177422 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177422 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 457427 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 457427 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116311 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 116311 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116311 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 116311 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116311 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 116311 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74935 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 74935 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74935 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 74935 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74935 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 74935 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914897711 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914897711 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914897711 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 914897711 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914897711 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 914897711 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 191246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 191246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 191246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391825 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391825 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391825 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391825 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391825 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391825 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,180 +819,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22022 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22022 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 76507 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 76507 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 76507 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 76507 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 76507 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 76507 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 782624451 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 782624451 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 782624451 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 782624451 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 782624451 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 782624451 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.401559 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.401559 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.401559 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448952 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20337 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20337 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74935 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74935 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74935 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 74935 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74935 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 74935 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 802357975 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 802357975 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 802357975 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 802357975 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 802357975 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 802357975 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391825 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391825 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391825 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1000352 # number of replacements -system.cpu.icache.tags.tagsinuse 509.220531 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8118136 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1000864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.111128 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147684343000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.220531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994571 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1000631 # number of replacements +system.cpu.icache.tags.tagsinuse 508.729229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8114183 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1001143 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.104919 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148026169000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.729229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.993612 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.993612 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10182088 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10182088 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8118136 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8118136 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8118136 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8118136 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8118136 # number of overall hits -system.cpu.icache.overall_hits::total 8118136 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1063017 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1063017 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1063017 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1063017 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1063017 # number of overall misses -system.cpu.icache.overall_misses::total 1063017 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14764552848 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14764552848 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14764552848 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14764552848 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14764552848 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14764552848 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9181153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9181153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9181153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9181153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9181153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9181153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13889.291374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13889.291374 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13889.291374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13889.291374 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7778 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 283 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.484099 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 10182374 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10182374 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8114183 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8114183 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8114183 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8114183 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8114183 # number of overall hits +system.cpu.icache.overall_hits::total 8114183 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066954 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066954 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066954 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066954 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066954 # number of overall misses +system.cpu.icache.overall_misses::total 1066954 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14925731792 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14925731792 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14925731792 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14925731792 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14925731792 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14925731792 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9181137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9181137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9181137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9181137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9181137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9181137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116212 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116212 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116212 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13989.105240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13989.105240 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 10002 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 328 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.493902 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62082 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62082 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62082 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62082 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62082 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62082 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1000935 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1000935 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1000935 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1000935 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1000935 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1000935 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12121618509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12121618509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12121618509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12121618509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12121618509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12121618509 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109021 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109021 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109021 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65717 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65717 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65717 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65717 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65717 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65717 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001237 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1001237 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1001237 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1001237 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1001237 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1001237 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12740674547 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12740674547 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12740674547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12740674547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12740674547 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12740674547 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109054 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109054 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109054 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 14419 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.299272 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25752 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 14435 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.783997 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5101096739000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.299272 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.393704 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.393704 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 14933 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.063651 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 25583 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 14948 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.711466 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.063651 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.378978 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.378978 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 97449 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 97449 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25750 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25750 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 98613 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 98613 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25588 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25588 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25752 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25752 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25752 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25752 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15315 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 15315 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15315 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15315 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15315 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15315 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 177860992 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 177860992 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 177860992 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 177860992 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 177860992 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 177860992 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41065 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41065 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25590 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25590 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25590 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25590 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15811 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15811 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15811 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15811 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15811 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15811 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183242996 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183242996 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183242996 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 183242996 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183242996 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 183242996 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41399 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41399 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41067 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41067 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41067 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41067 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372945 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372945 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372927 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.372927 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372927 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.372927 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11613.515638 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11613.515638 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11613.515638 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41401 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41401 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41401 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41401 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381917 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381917 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381899 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.381899 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381899 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.381899 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1022,177 +1001,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3318 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3318 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15315 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15315 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15315 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 15315 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15315 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 15315 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147213024 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147213024 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147213024 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147213024 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147213024 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147213024 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372945 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372945 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372927 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372927 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9612.342409 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3310 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15811 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15811 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 15811 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15811 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159511522 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159511522 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159511522 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381917 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381917 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381899 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381899 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112445 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64830.405135 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3843138 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176455 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.779706 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112684 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176714 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.765089 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.644782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.444532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3208.377327 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768115 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048956 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.171932 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64010 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 596 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52806 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976715 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35103909 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35103909 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69111 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12768 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 984459 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1335184 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2401522 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1585447 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1585447 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154410 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154410 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69111 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12768 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 984459 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1489594 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2555932 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69111 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12768 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 984459 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1489594 # number of overall hits -system.cpu.l2cache.overall_hits::total 2555932 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 62 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16359 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35824 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52251 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1504 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1504 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133327 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133327 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16359 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169151 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185578 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16359 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169151 # number of overall misses -system.cpu.l2cache.overall_misses::total 185578 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5303750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1250815250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2830285496 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4086871996 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17716796 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17716796 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290586712 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9290586712 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5303750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1250815250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12120872208 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13377458708 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5303750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1250815250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12120872208 # 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average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1301,69 +1280,69 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3074706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3074138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287746 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287746 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 27 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2001753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6129358 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 167702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8330220 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64052352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207821235 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1029888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5836480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278739955 # 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Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8320756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64067648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207974818 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1052928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5614976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278710370 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 59545 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4387643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010865 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4339785 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47639 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4387424 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4074051871 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1505430236 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141534733 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22981484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 114826620 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225722 # Transaction distribution -system.iobus.trans_dist::ReadResp 225722 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 11033 # Transaction distribution +system.iobus.trans_dist::ReadReq 223900 # Transaction distribution +system.iobus.trans_dist::ReadResp 223900 # Transaction distribution +system.iobus.trans_dist::WriteReq 57738 # Transaction distribution +system.iobus.trans_dist::WriteResp 11018 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.trans_dist::MessageReq 1650 # Transaction distribution +system.iobus.trans_dist::MessageResp 1650 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1373,21 +1352,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1397,19 +1376,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276590 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 240285 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1421,7 +1400,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1439,54 +1418,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448363457 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460639000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52378260 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47584 # number of replacements -system.iocache.tags.tagsinuse 0.079092 # Cycle average of tags in use +system.iocache.tags.replacements 47582 # number of replacements +system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992999647000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079092 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004943 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004943 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011120 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.011120 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428751 # Number of tag accesses -system.iocache.tags.data_accesses 428751 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses -system.iocache.ReadReq_misses::total 919 # number of ReadReq misses +system.iocache.tags.tag_accesses 428724 # Number of tag accesses +system.iocache.tags.data_accesses 428724 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses +system.iocache.ReadReq_misses::total 916 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses -system.iocache.demand_misses::total 919 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses -system.iocache.overall_misses::total 919 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149123196 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149123196 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12357582001 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12357582001 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 149123196 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 149123196 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 149123196 # number of overall miss cycles -system.iocache.overall_miss_latency::total 149123196 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses +system.iocache.demand_misses::total 916 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses +system.iocache.overall_misses::total 916 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144791938 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144791938 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144791938 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1495,40 +1474,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162266.807399 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 162266.807399 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 162266.807399 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70647 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9165 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.708347 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101309696 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9928122021 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9928122021 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101309696 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101309696 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1537,79 +1516,79 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662612 # Transaction distribution -system.membus.trans_dist::ReadResp 662585 # Transaction distribution +system.membus.trans_dist::ReadReq 657690 # Transaction distribution +system.membus.trans_dist::ReadResp 657682 # Transaction distribution system.membus.trans_dist::WriteReq 13919 # Transaction distribution system.membus.trans_dist::WriteResp 13919 # Transaction distribution -system.membus.trans_dist::Writeback 149557 # Transaction distribution +system.membus.trans_dist::Writeback 149687 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2230 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1790 # Transaction distribution -system.membus.trans_dist::ReadExReq 133043 # Transaction distribution -system.membus.trans_dist::ReadExResp 133041 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 27 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476745 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141469 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141469 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1868288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242122 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550121 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20191091 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26202783 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1603 # Total snoops (count) -system.membus.snoop_fanout::samples 384714 # Request fanout histogram +system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution +system.membus.trans_dist::ReadExReq 133182 # Transaction distribution +system.membus.trans_dist::ReadExResp 133180 # Transaction distribution +system.membus.trans_dist::MessageReq 1650 # Transaction distribution +system.membus.trans_dist::MessageResp 1650 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1640 # Total snoops (count) +system.membus.snoop_fanout::samples 384867 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 384714 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 384714 # Request fanout histogram -system.membus.reqLayer0.occupancy 251770499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 384867 # Request fanout histogram +system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583267500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1992294999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 33000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3156735730 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 55013740 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 79cf4b255..fa561f06e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,154 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144107 # Number of seconds simulated -sim_ticks 5144107123500 # Number of ticks simulated -final_tick 5144107123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.134221 # Number of seconds simulated +sim_ticks 5134220888000 # Number of ticks simulated +final_tick 5134220888000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 387693 # Simulator instruction rate (inst/s) -host_op_rate 770744 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8185899527 # Simulator tick rate (ticks/s) -host_mem_usage 958064 # Number of bytes of host memory used -host_seconds 628.41 # Real time elapsed on the host -sim_insts 243630211 # Number of instructions simulated -sim_ops 484343866 # Number of ops (including micro ops) simulated +host_inst_rate 274165 # Simulator instruction rate (inst/s) +host_op_rate 545049 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5772363280 # Simulator tick rate (ticks/s) +host_mem_usage 1013712 # Number of bytes of host memory used +host_seconds 889.45 # Real time elapsed on the host +sim_insts 243855553 # Number of instructions simulated +sim_ops 484792888 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 435328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5271168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 167488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2239424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 369088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2863936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 442496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5387840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 144896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1908224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 377856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3143424 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11377408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 435328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 167488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 369088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9177088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9177088 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 82362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 36 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44749 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11436096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 442496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 377856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9176704 # Number of bytes written to this memory +system.physmem.bytes_written::total 9176704 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 84185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 29816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 49116 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177772 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143392 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143392 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 84627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1024700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 435338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 556741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2211736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 84627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32559 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1784000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1784000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1784000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 84627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1024700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 435338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 556741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3995736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88604 # Number of read requests accepted -system.physmem.writeReqs 101715 # Number of write requests accepted -system.physmem.readBursts 88604 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 101715 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5666496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6448384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5670656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6509760 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 65 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 959 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 894 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5172 # Per bank write bursts -system.physmem.perBankRdBursts::1 4675 # Per bank write bursts -system.physmem.perBankRdBursts::2 4614 # Per bank write bursts -system.physmem.perBankRdBursts::3 5517 # Per bank write bursts -system.physmem.perBankRdBursts::4 6171 # Per bank write bursts -system.physmem.perBankRdBursts::5 5192 # Per bank write bursts -system.physmem.perBankRdBursts::6 5194 # Per bank write bursts -system.physmem.perBankRdBursts::7 5097 # Per bank write bursts -system.physmem.perBankRdBursts::8 5481 # Per bank write bursts -system.physmem.perBankRdBursts::9 5563 # Per bank write bursts -system.physmem.perBankRdBursts::10 5214 # Per bank write bursts -system.physmem.perBankRdBursts::11 5694 # Per bank write bursts -system.physmem.perBankRdBursts::12 5834 # Per bank write bursts -system.physmem.perBankRdBursts::13 6887 # Per bank write bursts -system.physmem.perBankRdBursts::14 6277 # Per bank write bursts -system.physmem.perBankRdBursts::15 5957 # Per bank write bursts -system.physmem.perBankWrBursts::0 6561 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts -system.physmem.perBankWrBursts::2 5964 # Per bank write bursts -system.physmem.perBankWrBursts::3 5948 # Per bank write bursts -system.physmem.perBankWrBursts::4 7233 # Per bank write bursts -system.physmem.perBankWrBursts::5 6043 # Per bank write bursts -system.physmem.perBankWrBursts::6 6495 # Per bank write bursts -system.physmem.perBankWrBursts::7 6502 # Per bank write bursts -system.physmem.perBankWrBursts::8 5629 # Per bank write bursts -system.physmem.perBankWrBursts::9 6174 # Per bank write bursts -system.physmem.perBankWrBursts::10 5473 # Per bank write bursts -system.physmem.perBankWrBursts::11 6467 # Per bank write bursts -system.physmem.perBankWrBursts::12 6126 # Per bank write bursts -system.physmem.perBankWrBursts::13 6747 # Per bank write bursts -system.physmem.perBankWrBursts::14 6614 # Per bank write bursts -system.physmem.perBankWrBursts::15 6682 # Per bank write bursts +system.physmem.num_reads::total 178689 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143386 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143386 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1049398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 371668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 612249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2227426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1787361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1787361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1787361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 86186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1049398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 371668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 612249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4014786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 87585 # Number of read requests accepted +system.physmem.writeReqs 96690 # Number of write requests accepted +system.physmem.readBursts 87585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96690 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5601728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue +system.physmem.bytesWritten 5458112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5605440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6188160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11390 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 914 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5700 # Per bank write bursts +system.physmem.perBankRdBursts::1 5150 # Per bank write bursts +system.physmem.perBankRdBursts::2 4887 # Per bank write bursts +system.physmem.perBankRdBursts::3 5253 # Per bank write bursts +system.physmem.perBankRdBursts::4 5094 # Per bank write bursts +system.physmem.perBankRdBursts::5 4483 # Per bank write bursts +system.physmem.perBankRdBursts::6 5146 # Per bank write bursts +system.physmem.perBankRdBursts::7 4650 # Per bank write bursts +system.physmem.perBankRdBursts::8 5914 # Per bank write bursts +system.physmem.perBankRdBursts::9 5792 # Per bank write bursts +system.physmem.perBankRdBursts::10 5352 # Per bank write bursts +system.physmem.perBankRdBursts::11 5127 # Per bank write bursts +system.physmem.perBankRdBursts::12 5714 # Per bank write bursts +system.physmem.perBankRdBursts::13 6636 # Per bank write bursts +system.physmem.perBankRdBursts::14 6391 # Per bank write bursts +system.physmem.perBankRdBursts::15 6238 # Per bank write bursts +system.physmem.perBankWrBursts::0 5924 # Per bank write bursts +system.physmem.perBankWrBursts::1 5309 # Per bank write bursts +system.physmem.perBankWrBursts::2 4960 # Per bank write bursts +system.physmem.perBankWrBursts::3 5064 # Per bank write bursts +system.physmem.perBankWrBursts::4 5666 # Per bank write bursts +system.physmem.perBankWrBursts::5 4857 # Per bank write bursts +system.physmem.perBankWrBursts::6 5361 # Per bank write bursts +system.physmem.perBankWrBursts::7 4594 # Per bank write bursts +system.physmem.perBankWrBursts::8 5275 # Per bank write bursts +system.physmem.perBankWrBursts::9 5755 # Per bank write bursts +system.physmem.perBankWrBursts::10 5195 # Per bank write bursts +system.physmem.perBankWrBursts::11 4824 # Per bank write bursts +system.physmem.perBankWrBursts::12 5173 # Per bank write bursts +system.physmem.perBankWrBursts::13 6061 # Per bank write bursts +system.physmem.perBankWrBursts::14 5642 # Per bank write bursts +system.physmem.perBankWrBursts::15 5623 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5140299284500 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 5133220754000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88604 # Read request sizes (log2) +system.physmem.readPktSize::6 87585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 101715 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96690 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 81722 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -165,455 +161,450 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.485168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.308895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.181387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15726 39.13% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9443 23.50% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4063 10.11% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2232 5.55% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1531 3.81% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1042 2.59% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 702 1.75% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 613 1.53% 87.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4832 12.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40184 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.412092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 185.359125 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4132 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.366626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.429404 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.022185 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 69 1.67% 1.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 9 0.22% 1.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 3347 80.94% 82.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 165 3.99% 86.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 114 2.76% 89.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 31 0.75% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 101 2.44% 92.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.27% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 26 0.63% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 40 0.97% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 54 1.31% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 10 0.24% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 75 1.81% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.19% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 18 0.44% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 7 0.17% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.36% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.29% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 5 0.12% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.10% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4135 # Writes before turning the bus around for reads -system.physmem.totQLat 956383499 # Total ticks spent queuing -system.physmem.totMemAccLat 2616489749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 442695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10801.83 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 285.721608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.408148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 310.834116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15365 39.69% 39.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9282 23.98% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4036 10.43% 74.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2303 5.95% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1514 3.91% 83.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1118 2.89% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 653 1.69% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 582 1.50% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3855 9.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38708 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.124587 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 196.006736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3625 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3628 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3628 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.506891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.576033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 38.070070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 79 2.18% 2.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 3330 91.79% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 63 1.74% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 14 0.39% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 6 0.17% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 13 0.36% 96.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 6 0.17% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 13 0.36% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.44% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.50% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.08% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 8 0.22% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.91% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.08% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.08% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 1 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.19% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3628 # Writes before turning the bus around for reads +system.physmem.totQLat 973946232 # Total ticks spent queuing +system.physmem.totMemAccLat 2615077482 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 437635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11127.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29551.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29877.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.42 # Average write queue length when enqueuing -system.physmem.readRowHits 70796 # Number of row buffer hits during reads -system.physmem.writeRowHits 78315 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.73 # Row buffer hit rate for writes -system.physmem.avgGap 27008860.31 # Average gap between requests -system.physmem.pageHitRate 78.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 147178080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 80086875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 324729600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 329469120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94792163085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2243751115500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2589991237140 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.838461 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3691094925500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128101480000 # Time in different power states +system.physmem.avgWrQLen 10.98 # Average write queue length when enqueuing +system.physmem.readRowHits 70024 # Number of row buffer hits during reads +system.physmem.writeRowHits 64077 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 27856305.81 # Average gap between requests +system.physmem.pageHitRate 77.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 138605040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 75351375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314831400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 270442800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94326783165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2239415376750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2584559149170 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.799253 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3683386249962 # Time in different power states +system.physmem_0.memoryStateTime::REF 127820940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17513749500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17097201288 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 156612960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 365874600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 323429760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95660983305 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2237004864750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2584163561130 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.053818 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3689804823000 # Time in different power states -system.physmem_1.memoryStateTime::REF 128101480000 # Time in different power states +system.physmem_1.actEnergy 154027440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83877750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 367863600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 282191040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95207179230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2235926942250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2582039839950 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.929569 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3682087997664 # Time in different power states +system.physmem_1.memoryStateTime::REF 127820940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18778765250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18395204336 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 906748886 # number of cpu cycles simulated +system.cpu0.numCycles 861071319 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71802590 # Number of instructions committed -system.cpu0.committedOps 146381299 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134255761 # Number of integer alu accesses +system.cpu0.committedInsts 71289400 # Number of instructions committed +system.cpu0.committedOps 145467698 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133359316 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 943296 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14239563 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134255761 # number of integer instructions +system.cpu0.num_func_calls 922812 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14140303 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133359316 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 246209877 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115427878 # number of times the integer registers were written +system.cpu0.num_int_register_reads 244470794 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114705006 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83592437 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55838323 # number of times the CC registers were written -system.cpu0.num_mem_refs 13658115 # number of memory refs -system.cpu0.num_load_insts 10127652 # Number of load instructions -system.cpu0.num_store_insts 3530463 # Number of store instructions -system.cpu0.num_idle_cycles 859556134.264708 # Number of idle cycles -system.cpu0.num_busy_cycles 47192751.735292 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052046 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947954 # Percentage of idle cycles -system.cpu0.Branches 15533640 # Number of branches fetched -system.cpu0.op_class::No_OpClass 89870 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132527069 90.54% 90.60% # Class of executed instruction -system.cpu0.op_class::IntMult 58535 0.04% 90.64% # Class of executed instruction -system.cpu0.op_class::IntDiv 49919 0.03% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::MemRead 10125945 6.92% 97.59% # Class of executed instruction -system.cpu0.op_class::MemWrite 3530463 2.41% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82965986 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55469495 # number of times the CC registers were written +system.cpu0.num_mem_refs 13497529 # number of memory refs +system.cpu0.num_load_insts 10019587 # Number of load instructions +system.cpu0.num_store_insts 3477942 # Number of store instructions +system.cpu0.num_idle_cycles 817633663.650796 # Number of idle cycles +system.cpu0.num_busy_cycles 43437655.349204 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050446 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949554 # Percentage of idle cycles +system.cpu0.Branches 15408320 # Number of branches fetched +system.cpu0.op_class::No_OpClass 89223 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 131776877 90.59% 90.65% # Class of executed instruction +system.cpu0.op_class::IntMult 58105 0.04% 90.69% # Class of executed instruction +system.cpu0.op_class::IntDiv 48148 0.03% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::MemRead 10017918 6.89% 97.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 3477942 2.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146381801 # Class of executed instruction +system.cpu0.op_class::total 145468213 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1639020 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19713831 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639532 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.024060 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1637783 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999406 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19710876 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638295 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.031335 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.995226 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 275.897813 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 106.106411 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.253897 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.538863 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.207239 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.289579 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 344.626695 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.083132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.281816 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.673099 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.045084 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 235 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88616075 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88616075 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4923544 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2619910 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4021776 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11565230 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3397085 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1858074 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2831900 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8087059 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19915 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10654 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29231 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59800 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8320629 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4477984 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6853676 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19652289 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8340544 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4488638 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6882907 # number of overall hits -system.cpu0.dcache.overall_hits::total 19712089 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 358740 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 166586 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 774812 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1300138 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 129303 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 72150 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 124071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325524 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 150487 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 66279 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 189615 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406381 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 488043 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 238736 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 898883 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1625662 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 638530 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 305015 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1088498 # number of overall misses -system.cpu0.dcache.overall_misses::total 2032043 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2329828500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11922594046 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14252422546 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2798605810 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12865368 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3526388 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1930224 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2955971 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8412583 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 170402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76933 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218846 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466181 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8808672 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4716720 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7752559 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21277951 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8979074 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4793653 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7971405 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21744132 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067914 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059783 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161534 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.101057 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036667 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037379 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041973 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038695 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.883129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.861516 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866431 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871724 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055405 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050615 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.076401 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071113 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063629 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136550 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093452 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13985.740098 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15387.725082 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10962.238275 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38788.715315 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31884.062956 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20749.601827 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21481.612786 # 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number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 172473 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 384626 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 557099 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 172473 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 384626 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 557099 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2070011500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4726513433 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6796524933 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2070011500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4726513433 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6796524933 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2070011500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4726513433 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6796524933 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004257 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004257 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004257 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.851253 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25959 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25959 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 25959 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25959 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 25959 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25959 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 413296 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 575951 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 162655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 413296 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 575951 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 162655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 413296 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 575951 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2031893251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5207377551 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7239270802 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2031893251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5207377551 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7239270802 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2031893251 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5207377551 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7239270802 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004444 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004444 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004444 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12569.247735 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608020264 # number of cpu cycles simulated +system.cpu1.numCycles 2606018109 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35983855 # Number of instructions committed -system.cpu1.committedOps 69821911 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64889046 # Number of integer alu accesses +system.cpu1.committedInsts 35373738 # Number of instructions committed +system.cpu1.committedOps 68746890 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63819737 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 503439 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6569343 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64889046 # number of integer instructions +system.cpu1.num_func_calls 481772 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6496386 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63819737 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120388172 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55814326 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118130559 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54973369 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36581725 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27247591 # number of times the CC registers were written -system.cpu1.num_mem_refs 4980693 # number of memory refs -system.cpu1.num_load_insts 3049501 # Number of load instructions -system.cpu1.num_store_insts 1931192 # Number of store instructions -system.cpu1.num_idle_cycles 2477411639.002949 # Number of idle cycles -system.cpu1.num_busy_cycles 130608624.997051 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050080 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949920 # Percentage of idle cycles -system.cpu1.Branches 7257729 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34768 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64752658 92.74% 92.79% # Class of executed instruction -system.cpu1.op_class::IntMult 32117 0.05% 92.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 23661 0.03% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::MemRead 3047883 4.37% 97.23% # Class of executed instruction -system.cpu1.op_class::MemWrite 1931192 2.77% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36098608 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26881383 # number of times the CC registers were written +system.cpu1.num_mem_refs 4684980 # number of memory refs +system.cpu1.num_load_insts 2884758 # Number of load instructions +system.cpu1.num_store_insts 1800222 # Number of store instructions +system.cpu1.num_idle_cycles 2483538175.555252 # Number of idle cycles +system.cpu1.num_busy_cycles 122479933.444748 # Number of busy cycles +system.cpu1.not_idle_fraction 0.046999 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.953001 # Percentage of idle cycles +system.cpu1.Branches 7152522 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34380 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63978277 93.06% 93.11% # Class of executed instruction +system.cpu1.op_class::IntMult 29063 0.04% 93.16% # Class of executed instruction +system.cpu1.op_class::IntDiv 22112 0.03% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::MemRead 2883100 4.19% 97.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 1800222 2.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69822279 # Class of executed instruction +system.cpu1.op_class::total 68747154 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29145274 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29145274 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 322260 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26440523 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25789579 # Number of BTB hits +system.cpu2.branchPred.lookups 29503892 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29503892 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 342810 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26694805 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25976378 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.538082 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 584080 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63924 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153878746 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.308739 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 611666 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 68809 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155682865 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10764874 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 143615831 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29145274 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26373659 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141609884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 675175 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 95795 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 6373 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7380 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 61565 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 20 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 458 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3473911 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167436 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3564 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152883285 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.850280 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.030640 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11322292 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145393707 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29503892 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26588044 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142785185 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 717310 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 102884 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8624 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 60469 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 854 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3643758 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 177822 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3817 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154648109 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.849994 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.031354 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97765346 63.95% 63.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 837203 0.55% 64.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23601513 15.44% 79.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 591420 0.39% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 819374 0.54% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 838216 0.55% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 577391 0.38% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 693159 0.45% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27159663 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98977108 64.00% 64.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 881864 0.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23689941 15.32% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 607646 0.39% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 853753 0.55% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 859687 0.56% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 584791 0.38% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 755278 0.49% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27438041 17.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152883285 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189404 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.933305 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9834703 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93251994 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 21466938 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4884733 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 338239 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279965546 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 338239 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11923429 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 75993663 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4610925 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 24032799 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12877614 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278749384 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 221936 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5866894 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 51314 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4911660 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 333127303 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 607942521 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 373256279 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 196 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320819170 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12308133 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 159156 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160655 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 23900033 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6505190 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3599973 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 377004 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 316512 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276808275 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 423236 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274695170 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 101004 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8754938 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13676659 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 65243 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152883285 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.796764 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.395757 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154648109 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189513 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.933910 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10277895 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94004330 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 21519674 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4891128 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 359306 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283040141 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 359306 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12341484 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77022094 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4867618 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24062417 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12399480 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 281740718 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 206678 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5855345 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 68061 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4394741 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 336544944 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 615400877 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 377780143 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 207 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 323636169 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12908773 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 167322 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 168903 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 23920372 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6854331 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3831116 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 436605 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 369940 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 279698877 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 432383 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 277466645 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 109952 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9178493 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 14257252 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68980 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154648109 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.794181 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.395462 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90394017 59.13% 59.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5385946 3.52% 62.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3961954 2.59% 65.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3603407 2.36% 67.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22510778 14.72% 82.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2513602 1.64% 83.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23841558 15.59% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 461559 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 210464 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91599661 59.23% 59.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5400101 3.49% 62.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3869243 2.50% 65.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3752650 2.43% 67.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22658386 14.65% 82.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2693281 1.74% 84.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23975807 15.50% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 476523 0.31% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 222457 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152883285 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154648109 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1679391 85.86% 85.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 6 0.00% 85.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 133 0.01% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 216471 11.07% 96.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 59961 3.07% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1665704 85.56% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 217161 11.15% 96.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64057 3.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 81534 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264357889 96.24% 96.27% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 55368 0.02% 96.29% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50253 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 68 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6828846 2.49% 98.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3321212 1.21% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 83075 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266581381 96.08% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 59040 0.02% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 53621 0.02% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 87 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7156038 2.58% 98.73% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3533403 1.27% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274695170 # Type of FU issued -system.cpu2.iq.rate 1.785140 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1955962 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007120 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 704330322 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285990572 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273107568 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 106 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 276569466 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 697735 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 277466645 # Type of FU issued +system.cpu2.iq.rate 1.782256 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1946922 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007017 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 711637991 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289314219 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275821613 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 281 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 279330355 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 137 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 727263 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1221587 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6074 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4844 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 639616 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1301667 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5946 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5330 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 686178 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755983 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21219 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750303 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28695 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 338239 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70808815 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1780684 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277231511 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 42116 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6505190 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3599973 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 246009 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 189602 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1292389 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4844 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 181953 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 192646 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374599 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274123146 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6692505 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 521898 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 359306 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71000950 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2910946 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 280131260 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 44826 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6854348 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3831116 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 254274 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 173954 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2389293 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5330 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 193600 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 205490 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 399090 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276846611 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7005762 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 563321 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9929733 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27833627 # Number of branches executed -system.cpu2.iew.exec_stores 3237228 # Number of stores executed -system.cpu2.iew.exec_rate 1.781423 # Inst execution rate -system.cpu2.iew.wb_sent 273932637 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273107674 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213006118 # num instructions producing a value -system.cpu2.iew.wb_consumers 349346589 # num instructions consuming a value +system.cpu2.iew.exec_refs 10447548 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28131020 # Number of branches executed +system.cpu2.iew.exec_stores 3441786 # Number of stores executed +system.cpu2.iew.exec_rate 1.778273 # Inst execution rate +system.cpu2.iew.wb_sent 276647008 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275821721 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215019240 # num instructions producing a value +system.cpu2.iew.wb_consumers 352722264 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.774824 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609727 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.771690 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609599 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9088854 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357993 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325291 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 151524726 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.769617 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.649272 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9550045 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 363403 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 345846 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153217834 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.765971 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.651639 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94238602 62.19% 62.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4221946 2.79% 64.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1274040 0.84% 65.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24556134 16.21% 82.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1017367 0.67% 82.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 681486 0.45% 83.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 477034 0.31% 83.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23101810 15.25% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1956307 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95448328 62.30% 62.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4376826 2.86% 65.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1280143 0.84% 65.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24626260 16.07% 82.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 968124 0.63% 82.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 723433 0.47% 83.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 420249 0.27% 83.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23244515 15.17% 98.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2129956 1.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 151524726 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135843766 # Number of instructions committed -system.cpu2.commit.committedOps 268140656 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153217834 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137192415 # Number of instructions committed +system.cpu2.commit.committedOps 270578300 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8243960 # Number of memory references committed -system.cpu2.commit.loads 5283603 # Number of loads committed -system.cpu2.commit.membars 162116 # Number of memory barriers committed -system.cpu2.commit.branches 27422801 # Number of branches committed +system.cpu2.commit.refs 8697618 # Number of memory references committed +system.cpu2.commit.loads 5552680 # Number of loads committed +system.cpu2.commit.membars 162630 # Number of memory barriers committed +system.cpu2.commit.branches 27696347 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244944567 # Number of committed integer instructions. -system.cpu2.commit.function_calls 433353 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 47848 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259747107 96.87% 96.89% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 53065 0.02% 96.91% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48699 0.02% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5283564 1.97% 98.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2960357 1.10% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 247309305 # Number of committed integer instructions. +system.cpu2.commit.function_calls 454335 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 48751 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 261723532 96.73% 96.75% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56607 0.02% 96.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 51834 0.02% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5552622 2.05% 98.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3144938 1.16% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 268140656 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1956307 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 426769551 # The number of ROB reads -system.cpu2.rob.rob_writes 555823820 # The number of ROB writes -system.cpu2.timesIdled 116899 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 995461 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4917307163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135843766 # Number of Instructions Simulated -system.cpu2.committedOps 268140656 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.132763 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.132763 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882797 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882797 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364780652 # number of integer regfile reads -system.cpu2.int_regfile_writes 218921020 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73130 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139296056 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107100465 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89036481 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137201 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554570 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554570 # Transaction distribution +system.cpu2.rob.rob_reads 431186663 # The number of ROB reads +system.cpu2.rob.rob_writes 561693850 # The number of ROB writes +system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1034756 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4900728082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137192415 # Number of Instructions Simulated +system.cpu2.committedOps 270578300 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.134777 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.134777 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.881230 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.881230 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 368834984 # number of integer regfile reads +system.cpu2.int_regfile_writes 221067360 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73020 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140711927 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108060819 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90227595 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143035 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3553360 # Transaction distribution +system.iobus.trans_dist::ReadResp 3553360 # Transaction distribution system.iobus.trans_dist::WriteReq 57725 # Transaction distribution system.iobus.trans_dist::WriteResp 11005 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1681 # Transaction distribution -system.iobus.trans_dist::MessageResp 1681 # Transaction distribution +system.iobus.trans_dist::MessageReq 1679 # Transaction distribution +system.iobus.trans_dist::MessageResp 1679 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -1147,7 +1138,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1157,12 +1148,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7126912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7225528 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -1171,7 +1162,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541309 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1181,19 +1172,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570873 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2588568 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3569655 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6604187 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2698688 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4563000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5333000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1201,70 +1192,68 @@ system.iobus.reqLayer5.occupancy 758000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 141310000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 404000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 414000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 78000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10340000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10425000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 221126240 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 116029251 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 302697000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 300958000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28304753 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 24266250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1088000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1136000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47566 # number of replacements -system.iocache.tags.tagsinuse 0.112009 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.081409 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571390009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112009 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007001 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007001 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000597695009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081409 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005088 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005088 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428589 # Number of tag accesses -system.iocache.tags.data_accesses 428589 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 901 # number of ReadReq misses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses -system.iocache.demand_misses::total 901 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses -system.iocache.overall_misses::total 901 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132764027 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132764027 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6059046460 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6059046460 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132764027 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132764027 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132764027 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132764027 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 125652013 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 125652013 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 3845868988 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3845868988 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 125652013 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 125652013 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 125652013 # number of overall miss cycles +system.iocache.overall_miss_latency::total 125652013 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1273,325 +1262,311 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 147351.861265 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 129688.494435 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 129688.494435 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 147351.861265 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 147351.861265 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34598 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138231.037404 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 82317.401284 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 82317.401284 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138231.037404 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138231.037404 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 13512 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4497 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2030 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.693573 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.656158 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 738 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 23008 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 23008 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 738 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 738 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 738 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94361527 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 4862624466 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4862624466 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94361527 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94361527 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.819090 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.492466 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.492466 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.819090 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.819090 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127861.147696 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 211344.943759 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 211344.943759 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 745 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 745 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 21024 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 745 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 745 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 745 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 745 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86664503 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2752610998 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2752610998 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 86664503 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 86664503 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.819582 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.450000 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.450000 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.819582 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.819582 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 116328.191946 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130927.083238 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130927.083238 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104970 # number of replacements -system.l2c.tags.tagsinuse 64826.298792 # Cycle average of tags in use -system.l2c.tags.total_refs 3700737 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169148 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.878692 # Average number of references to valid blocks. +system.l2c.tags.replacements 105420 # number of replacements +system.l2c.tags.tagsinuse 64829.150073 # Cycle average of tags in use +system.l2c.tags.total_refs 3714265 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169452 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.919275 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51221.575879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1714.525389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5051.845543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 364.783966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1988.075845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.500719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 853.175626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3622.680869 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.781579 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51423.363344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134649 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1822.192254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5065.443853 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 236.253380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1546.126379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.729356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 913.877634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3810.029226 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.784658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.077085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030336 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013018 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.055278 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2747 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54646 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979279 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33928519 # Number of tag accesses -system.l2c.tags.data_accesses 33928519 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20269 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 306104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491683 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12164 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6423 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 169856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 59393 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 378835 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 595825 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2292802 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.027804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.077293 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023592 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013945 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.058136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989214 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64032 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 535 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53036 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977051 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 34034094 # Number of tag accesses +system.l2c.tags.data_accesses 34034094 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19379 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 295114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 477769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12495 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 160391 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 220397 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 66650 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 14282 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 407368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 616656 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2308529 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1548363 # number of Writeback hits -system.l2c.Writeback_hits::total 1548363 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 100 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 101 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 272 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63359 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39945 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 57961 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161265 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20269 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10934 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 306104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 555042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 169856 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 267695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 59393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 378835 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 653786 # number of demand (read+write) hits -system.l2c.demand_hits::total 2454069 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20269 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10934 # number of overall hits -system.l2c.overall_hits::cpu0.inst 306104 # number of overall hits -system.l2c.overall_hits::cpu0.data 555042 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12164 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6423 # number of overall hits -system.l2c.overall_hits::cpu1.inst 169856 # number of overall hits -system.l2c.overall_hits::cpu1.data 267695 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 59393 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13568 # number of overall hits -system.l2c.overall_hits::cpu2.inst 378835 # number of overall hits -system.l2c.overall_hits::cpu2.data 653786 # number of overall hits -system.l2c.overall_hits::total 2454069 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6803 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 17544 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2617 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5064 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 36 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5767 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 10237 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48073 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 615 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 446 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 30166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 34786 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130181 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6803 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 82773 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2617 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 36 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5767 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45023 # number of demand (read+write) misses -system.l2c.demand_misses::total 178254 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6803 # number of overall misses -system.l2c.overall_misses::cpu0.data 82773 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2617 # number of overall misses -system.l2c.overall_misses::cpu1.data 35230 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 36 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5767 # number of overall misses -system.l2c.overall_misses::cpu2.data 45023 # number of overall misses -system.l2c.overall_misses::total 178254 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 190653500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 384787000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2953999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 449712500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 795071749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1823253248 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3961367 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 5247781 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9209148 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2078566202 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2496913123 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4575479325 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 190653500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2463353202 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2953999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 449712500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3291984872 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6398732573 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 190653500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2463353202 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2953999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 449712500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3291984872 # 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number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 49565 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 87792 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 156732750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 272024750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 432457000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 959731250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1824184750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5165744 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8859994 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14025738 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1640131535 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2435332138 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4075463673 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 156732750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1912156285 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 432457000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3395063388 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5899648423 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 156732750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1912156285 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 432457000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3395063388 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5899648423 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27747826000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30174191500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 57922017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 492354000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 747099000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1239453000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28240180000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30921290500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59161470500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017208 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020791 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010677 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.821086 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.847863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.458308 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420175 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.360079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.215638 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033165 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033165 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70490.995076 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73301.096005 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 72497.605516 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20100.171206 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17862.891129 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18626.478088 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62700.953246 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66772.651294 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65072.068865 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1735,66 +1692,66 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5122083 # Transaction distribution -system.membus.trans_dist::ReadResp 5122081 # Transaction distribution -system.membus.trans_dist::WriteReq 13936 # Transaction distribution -system.membus.trans_dist::WriteResp 13936 # Transaction distribution -system.membus.trans_dist::Writeback 143392 # Transaction distribution +system.membus.trans_dist::ReadReq 5119167 # Transaction distribution +system.membus.trans_dist::ReadResp 5119165 # Transaction distribution +system.membus.trans_dist::WriteReq 13931 # Transaction distribution +system.membus.trans_dist::WriteResp 13931 # Transaction distribution +system.membus.trans_dist::Writeback 143386 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1613 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1613 # Transaction distribution -system.membus.trans_dist::ReadExReq 129914 # Transaction distribution -system.membus.trans_dist::ReadExResp 129914 # Transaction distribution -system.membus.trans_dist::MessageReq 1681 # Transaction distribution -system.membus.trans_dist::MessageResp 1681 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1652 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution +system.membus.trans_dist::ReadExReq 130721 # Transaction distribution +system.membus.trans_dist::ReadExResp 130721 # Transaction distribution +system.membus.trans_dist::MessageReq 1679 # Transaction distribution +system.membus.trans_dist::MessageResp 1679 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3041102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457338 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10629668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10774644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570873 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17560128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27220486 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6015552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33242762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 642 # Total snoops (count) -system.membus.snoop_fanout::samples 370612 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::total 10625356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10770337 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569655 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6082201 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17609408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27261264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33283596 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 789 # Total snoops (count) +system.membus.snoop_fanout::samples 371599 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370612 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 371599 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370612 # Request fanout histogram -system.membus.reqLayer0.occupancy 162893500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 371599 # Request fanout histogram +system.membus.reqLayer0.occupancy 233199000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314579500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 303775500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2176000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2272000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1055146498 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 587213160 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1088000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1136000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1708813357 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1313776839 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 29666247 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 24877750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1808,52 +1765,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7441673 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7441143 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13938 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13938 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1548363 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 23008 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291446 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291446 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7456393 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7455858 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13933 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13933 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1546722 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 21038 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1643 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1643 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 290440 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 290440 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004999 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207249 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17025096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55679680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213700038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 269360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 773664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270422742 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 67345 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4256875 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011187 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105175 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1755962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14994862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 74580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 223072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17048476 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56190016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213507600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 279632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270801176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69805 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4272022 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011152 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105014 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4209254 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4224379 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47643 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4256875 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5306709352 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4272022 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2506180983 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 318000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2510055059 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 865936683 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4923615960 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25531897 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1938409360 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26348986 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 85751327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96467647 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |