diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-20 17:18:53 -0400 |
| commit | c4e91289ae8806eb051fb1f41ece8be308f0ff85 (patch) | |
| tree | 6f35a7725cfd4072c8516ee0bb2ae799d48ce896 /tests/long/fs | |
| parent | cc6523e2d686447f90acccac20c0fb2940dc3e3b (diff) | |
| download | gem5-c4e91289ae8806eb051fb1f41ece8be308f0ff85.tar.xz | |
stats: Bump stats for filter, crossbar and config changes
This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
Diffstat (limited to 'tests/long/fs')
15 files changed, 20030 insertions, 18161 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index 9abb1e987..1996e7f30 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.883224 # Number of seconds simulated -sim_ticks 1883223940000 # Number of ticks simulated -final_tick 1883223940000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1883224346500 # Number of ticks simulated +final_tick 1883224346500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 180615 # Simulator instruction rate (inst/s) -host_op_rate 180615 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6060637883 # Simulator tick rate (ticks/s) -host_mem_usage 316396 # Number of bytes of host memory used -host_seconds 310.73 # Real time elapsed on the host -sim_insts 56122642 # Number of instructions simulated -sim_ops 56122642 # Number of ops (including micro ops) simulated +host_inst_rate 283997 # Simulator instruction rate (inst/s) +host_op_rate 283997 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9530044697 # Simulator tick rate (ticks/s) +host_mem_usage 369276 # Number of bytes of host memory used +host_seconds 197.61 # Real time elapsed on the host +sim_insts 56120453 # Number of instructions simulated +sim_ops 56120453 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 25930944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 25931648 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25931904 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1052544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4902720 # Number of bytes written to this memory +system.physmem.bytes_read::total 25932608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4903936 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7562048 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 405171 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7563264 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 405182 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 405186 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 76605 # Number of write requests responded to by this memory +system.physmem.num_reads::total 405197 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 76624 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118157 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 13769443 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 118176 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 13769813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 510 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13769952 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558905 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2603365 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1412115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4015480 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2603365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 13769443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13770323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 559041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 559041 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2604011 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1412114 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4016125 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2604011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 13769813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1412624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17785432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 405186 # Number of read requests accepted -system.physmem.writeReqs 118157 # Number of write requests accepted -system.physmem.readBursts 405186 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 118157 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25919424 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12480 # Total number of bytes read from write queue -system.physmem.bytesWritten 7560064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25931904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7562048 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 195 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 17786448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 405197 # Number of read requests accepted +system.physmem.writeReqs 118176 # Number of write requests accepted +system.physmem.readBursts 405197 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 118176 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25920704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11904 # Total number of bytes read from write queue +system.physmem.bytesWritten 7562112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25932608 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7563264 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 186 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25480 # Per bank write bursts -system.physmem.perBankRdBursts::1 25741 # Per bank write bursts -system.physmem.perBankRdBursts::2 25855 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25484 # Per bank write bursts +system.physmem.perBankRdBursts::1 25740 # Per bank write bursts +system.physmem.perBankRdBursts::2 25857 # Per bank write bursts system.physmem.perBankRdBursts::3 25788 # Per bank write bursts -system.physmem.perBankRdBursts::4 25233 # Per bank write bursts -system.physmem.perBankRdBursts::5 24956 # Per bank write bursts -system.physmem.perBankRdBursts::6 24811 # Per bank write bursts +system.physmem.perBankRdBursts::4 25237 # Per bank write bursts +system.physmem.perBankRdBursts::5 24959 # Per bank write bursts +system.physmem.perBankRdBursts::6 24814 # Per bank write bursts system.physmem.perBankRdBursts::7 24586 # Per bank write bursts system.physmem.perBankRdBursts::8 25127 # Per bank write bursts -system.physmem.perBankRdBursts::9 25280 # Per bank write bursts -system.physmem.perBankRdBursts::10 25532 # Per bank write bursts +system.physmem.perBankRdBursts::9 25284 # Per bank write bursts +system.physmem.perBankRdBursts::10 25531 # Per bank write bursts system.physmem.perBankRdBursts::11 24857 # Per bank write bursts -system.physmem.perBankRdBursts::12 24547 # Per bank write bursts -system.physmem.perBankRdBursts::13 25588 # Per bank write bursts -system.physmem.perBankRdBursts::14 25870 # Per bank write bursts +system.physmem.perBankRdBursts::12 24549 # Per bank write bursts +system.physmem.perBankRdBursts::13 25592 # Per bank write bursts +system.physmem.perBankRdBursts::14 25866 # Per bank write bursts system.physmem.perBankRdBursts::15 25740 # Per bank write bursts system.physmem.perBankWrBursts::0 7812 # Per bank write bursts -system.physmem.perBankWrBursts::1 7677 # Per bank write bursts +system.physmem.perBankWrBursts::1 7680 # Per bank write bursts system.physmem.perBankWrBursts::2 8067 # Per bank write bursts -system.physmem.perBankWrBursts::3 7744 # Per bank write bursts -system.physmem.perBankWrBursts::4 7318 # Per bank write bursts -system.physmem.perBankWrBursts::5 6954 # Per bank write bursts -system.physmem.perBankWrBursts::6 6788 # Per bank write bursts -system.physmem.perBankWrBursts::7 6406 # Per bank write bursts -system.physmem.perBankWrBursts::8 7235 # Per bank write bursts -system.physmem.perBankWrBursts::9 6889 # Per bank write bursts -system.physmem.perBankWrBursts::10 7393 # Per bank write bursts -system.physmem.perBankWrBursts::11 6865 # Per bank write bursts +system.physmem.perBankWrBursts::3 7745 # Per bank write bursts +system.physmem.perBankWrBursts::4 7320 # Per bank write bursts +system.physmem.perBankWrBursts::5 6957 # Per bank write bursts +system.physmem.perBankWrBursts::6 6792 # Per bank write bursts +system.physmem.perBankWrBursts::7 6401 # Per bank write bursts +system.physmem.perBankWrBursts::8 7236 # Per bank write bursts +system.physmem.perBankWrBursts::9 6892 # Per bank write bursts +system.physmem.perBankWrBursts::10 7391 # Per bank write bursts +system.physmem.perBankWrBursts::11 6866 # Per bank write bursts system.physmem.perBankWrBursts::12 7045 # Per bank write bursts -system.physmem.perBankWrBursts::13 8007 # Per bank write bursts +system.physmem.perBankWrBursts::13 8010 # Per bank write bursts system.physmem.perBankWrBursts::14 7989 # Per bank write bursts -system.physmem.perBankWrBursts::15 7937 # Per bank write bursts +system.physmem.perBankWrBursts::15 7955 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 1883215178500 # Total gap between requests +system.physmem.numWrRetry 7 # Number of times write queue was full causing retry +system.physmem.totGap 1883215617500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 405186 # Read request sizes (log2) +system.physmem.readPktSize::6 405197 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 118157 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402670 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 66 # What read queue length does an incoming req see +system.physmem.writePktSize::6 118176 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2242 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 68 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -147,125 +147,126 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7208 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5776 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 34 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 531.800302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 324.503879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 415.177975 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14434 22.93% 22.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10626 16.88% 39.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4984 7.92% 47.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3035 4.82% 52.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2479 3.94% 56.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2063 3.28% 59.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1365 2.17% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1615 2.57% 64.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22354 35.51% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62955 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5310 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.265725 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2898.384419 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5307 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 153 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 18 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 63140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 530.294837 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 322.585016 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.640457 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14650 23.20% 23.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10589 16.77% 39.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5075 8.04% 48.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3003 4.76% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2370 3.75% 56.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2105 3.33% 59.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1364 2.16% 62.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1607 2.55% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22377 35.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 63140 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5316 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 76.186983 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2896.748549 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5313 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5310 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5310 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.245951 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.963647 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.434666 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4660 87.76% 87.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 16 0.30% 88.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 15 0.28% 88.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 4.27% 92.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 38 0.72% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 5 0.09% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 8 0.15% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 6 0.11% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 26 0.49% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 4 0.08% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 94.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 14 0.26% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.09% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 26 0.49% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.17% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 5 0.09% 95.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.11% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 182 3.43% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.11% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.04% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.06% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.11% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 5 0.09% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.08% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.04% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 7 0.13% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.09% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5316 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5316 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.226862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.933757 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.590348 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4662 87.70% 87.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 15 0.28% 87.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 21 0.40% 88.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 225 4.23% 92.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 46 0.87% 93.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 10 0.19% 93.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 7 0.13% 93.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 7 0.13% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.36% 94.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.06% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.04% 94.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 12 0.23% 94.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 94.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.11% 94.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 29 0.55% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 14 0.26% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 95.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 12 0.23% 95.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 164 3.09% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.09% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.04% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.06% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.08% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 3 0.06% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 8 0.15% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 6 0.11% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 12 0.23% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 3 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.06% 99.94% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::224-227 3 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5310 # Writes before turning the bus around for reads -system.physmem.totQLat 2131293750 # Total ticks spent queuing -system.physmem.totMemAccLat 9724875000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5262.57 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5316 # Writes before turning the bus around for reads +system.physmem.totQLat 2156220500 # Total ticks spent queuing +system.physmem.totMemAccLat 9750176750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2025055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5323.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24012.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 24073.86 # Average memory access latency per DRAM burst system.physmem.avgRdBW 13.76 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 4.02 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 4.02 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s @@ -273,108 +274,113 @@ system.physmem.busUtil 0.14 # Da system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364467 # Number of row buffer hits during reads -system.physmem.writeRowHits 95695 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.99 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.99 # Row buffer hit rate for writes -system.physmem.avgGap 3598433.87 # Average gap between requests -system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1774121817500 # Time in different power states +system.physmem.avgWrQLen 23.67 # Average write queue length when enqueuing +system.physmem.readRowHits 364400 # Number of row buffer hits during reads +system.physmem.writeRowHits 95629 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.92 # Row buffer hit rate for writes +system.physmem.avgGap 3598228.45 # Average gap between requests +system.physmem.pageHitRate 87.93 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1774012993500 # Time in different power states system.physmem.memoryStateTime::REF 62884900000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 46214912500 # Time in different power states +system.physmem.memoryStateTime::ACT 46323736500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17814330 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 295751 # Transaction distribution -system.membus.trans_dist::ReadResp 295735 # Transaction distribution +system.membus.trans_dist::ReadReq 295760 # Transaction distribution +system.membus.trans_dist::ReadResp 295744 # Transaction distribution system.membus.trans_dist::WriteReq 9618 # Transaction distribution system.membus.trans_dist::WriteResp 9618 # Transaction distribution -system.membus.trans_dist::Writeback 76605 # Transaction distribution +system.membus.trans_dist::Writeback 76624 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 157 # Transaction distribution -system.membus.trans_dist::UpgradeResp 157 # Transaction distribution -system.membus.trans_dist::ReadExReq 116539 # Transaction distribution -system.membus.trans_dist::ReadExResp 116539 # Transaction distribution +system.membus.trans_dist::UpgradeReq 154 # Transaction distribution +system.membus.trans_dist::UpgradeResp 154 # Transaction distribution +system.membus.trans_dist::ReadExReq 116541 # Transaction distribution +system.membus.trans_dist::ReadExResp 116541 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33096 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887261 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887296 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920389 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920424 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1003681 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30833664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30877972 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33538260 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33538260 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29840000 # Layer occupancy (ticks) +system.membus.pkt_count::total 1003716 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44308 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30835584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30879892 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33540180 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 158 # Total snoops (count) +system.membus.snoop_fanout::samples 523708 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 523708 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 523708 # Request fanout histogram +system.membus.reqLayer0.occupancy 30927500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1547069500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1547261750 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 19500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3825068843 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825161596 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43112000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43114249 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.288165 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.288180 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728026235000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.288165 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.080510 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.080510 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1728025257000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.288180 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.080511 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.080511 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375533 # Number of tag accesses -system.iocache.tags.data_accesses 375533 # Number of data accesses +system.iocache.tags.tag_accesses 375525 # Number of tag accesses +system.iocache.tags.data_accesses 375525 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 1 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 1 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21132383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21132383 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21132383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21132383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21132383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21132383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41553 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41553 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000024 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000024 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122152.502890 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122152.502890 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122152.502890 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122152.502890 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122152.502890 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,30 +397,30 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12135383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12135383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2514597305 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2514597305 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12135383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12135383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12135383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12135383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512658057 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512658057 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999976 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999976 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70146.722543 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60516.877768 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60516.877768 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70146.722543 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70146.722543 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60470.207379 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60470.207379 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -428,36 +434,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 14964215 # Number of BP lookups -system.cpu.branchPred.condPredicted 12981470 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 376025 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10003487 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5188980 # Number of BTB hits +system.cpu.branchPred.lookups 14964931 # Number of BP lookups +system.cpu.branchPred.condPredicted 12983118 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 374694 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9691016 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5184483 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 51.871712 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 807651 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32040 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 53.497827 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 807557 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32108 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9238395 # DTB read hits -system.cpu.dtb.read_misses 17814 # DTB read misses +system.cpu.dtb.read_hits 9237824 # DTB read hits +system.cpu.dtb.read_misses 17804 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766068 # DTB read accesses -system.cpu.dtb.write_hits 6385066 # DTB write hits -system.cpu.dtb.write_misses 2311 # DTB write misses +system.cpu.dtb.read_accesses 766148 # DTB read accesses +system.cpu.dtb.write_hits 6384867 # DTB write hits +system.cpu.dtb.write_misses 2306 # DTB write misses system.cpu.dtb.write_acv 159 # DTB write access violations -system.cpu.dtb.write_accesses 298441 # DTB write accesses -system.cpu.dtb.data_hits 15623461 # DTB hits -system.cpu.dtb.data_misses 20125 # DTB misses +system.cpu.dtb.write_accesses 298467 # DTB write accesses +system.cpu.dtb.data_hits 15622691 # DTB hits +system.cpu.dtb.data_misses 20110 # DTB misses system.cpu.dtb.data_acv 370 # DTB access violations -system.cpu.dtb.data_accesses 1064509 # DTB accesses -system.cpu.itb.fetch_hits 4000795 # ITB hits -system.cpu.itb.fetch_misses 6874 # ITB misses -system.cpu.itb.fetch_acv 703 # ITB acv -system.cpu.itb.fetch_accesses 4007669 # ITB accesses +system.cpu.dtb.data_accesses 1064615 # DTB accesses +system.cpu.itb.fetch_hits 3999749 # ITB hits +system.cpu.itb.fetch_misses 6851 # ITB misses +system.cpu.itb.fetch_acv 647 # ITB acv +system.cpu.itb.fetch_accesses 4006600 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -470,39 +476,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 176776474 # number of cpu cycles simulated +system.cpu.numCycles 174888375 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56122642 # Number of instructions committed -system.cpu.committedOps 56122642 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2532635 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5494 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3591582755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.149825 # CPI: cycles per instruction -system.cpu.ipc 0.317478 # IPC: instructions per cycle +system.cpu.committedInsts 56120453 # Number of instructions committed +system.cpu.committedOps 56120453 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2530516 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5527 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3591560318 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.116304 # CPI: cycles per instruction +system.cpu.ipc 0.320893 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6375 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211451 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74783 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6374 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211459 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74787 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1900 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105851 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182665 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73416 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105855 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182673 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73420 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1900 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73416 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148863 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1832860357500 97.33% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80169000 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 672803000 0.04% 97.37% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49609630000 2.63% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1883222959500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981720 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73420 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148871 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1832868777500 97.33% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80360500 0.00% 97.33% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 672864500 0.04% 97.37% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 49601349000 2.63% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1883223351500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981721 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814951 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693590 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814959 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -541,7 +547,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175508 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::swpipl 175516 91.23% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6803 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -550,23 +556,23 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5125 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192390 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5869 # number of protection mode switches +system.cpu.kern.callpal::total 192398 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5867 # number of protection mode switches system.cpu.kern.mode_switch::user 1741 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 169 -system.cpu.kern.mode_switch_good::kernel 0.325439 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.325550 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080630 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.080553 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.393571 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36245351000 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4057630500 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1842919968000 97.86% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 36222818500 1.92% 1.92% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4061127000 0.22% 2.14% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1842939396000 97.86% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4175 # number of times the context was actually changed -system.cpu.tickCycles 85798616 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90977858 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 83840328 # Number of cycles that the object actually ticked +system.cpu.idleCycles 91048047 # Total number of cycles that the object has spent stopped system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -598,12 +604,10 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1436853 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51169 # Transaction distribution +system.iobus.trans_dist::WriteReq 51170 # Transaction distribution system.iobus.trans_dist::WriteResp 51170 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 1 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5092 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) @@ -620,23 +624,22 @@ system.iobus.pkt_count_system.bridge.master::total 33096 system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 116546 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705916 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2705916 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 4703000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) @@ -659,66 +662,66 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374409688 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374407689 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23478000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42012000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42013751 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 1458007 # number of replacements -system.cpu.icache.tags.tagsinuse 509.627041 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18950160 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1458518 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.992750 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31562091250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.627041 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 1457910 # number of replacements +system.cpu.icache.tags.tagsinuse 509.626980 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18940924 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1458421 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.987281 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 31560714250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.626980 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.995365 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.995365 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 386 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21867553 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21867553 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18950163 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18950163 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18950163 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18950163 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18950163 # number of overall hits -system.cpu.icache.overall_hits::total 18950163 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1458695 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1458695 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1458695 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1458695 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1458695 # number of overall misses -system.cpu.icache.overall_misses::total 1458695 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20021954296 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20021954296 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20021954296 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20021954296 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20021954296 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20021954296 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20408858 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20408858 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20408858 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20408858 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20408858 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20408858 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071474 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071474 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071474 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071474 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071474 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071474 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.936057 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13725.936057 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13725.936057 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.936057 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13725.936057 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21858119 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21858119 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18940927 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18940927 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18940927 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18940927 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18940927 # number of overall hits +system.cpu.icache.overall_hits::total 18940927 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1458596 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1458596 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1458596 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1458596 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1458596 # number of overall misses +system.cpu.icache.overall_misses::total 1458596 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20022164568 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20022164568 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20022164568 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20022164568 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20022164568 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20022164568 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20399523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20399523 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20399523 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20399523 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20399523 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20399523 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071501 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071501 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071501 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071501 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071501 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071501 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13727.011844 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13727.011844 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13727.011844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.011844 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13727.011844 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -727,143 +730,152 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458695 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1458695 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1458695 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1458695 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1458695 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1458695 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097209704 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17097209704 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097209704 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17097209704 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097209704 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17097209704 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071474 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071474 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071474 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071474 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11720.894158 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11720.894158 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11720.894158 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11720.894158 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1458596 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1458596 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1458596 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1458596 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1458596 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1458596 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17097663432 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17097663432 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17097663432 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17097663432 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17097663432 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17097663432 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071501 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071501 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071501 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071501 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11722.000768 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11722.000768 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11722.000768 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11722.000768 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 126942050 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2557486 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2557452 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2557139 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2557106 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9618 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838282 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41557 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304264 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838111 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304253 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304253 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917328 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663485 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6580813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93352512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143044180 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 236396692 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 236386772 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2673536 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2697842997 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2917133 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3662791 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6579924 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93346368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143016724 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236363092 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41947 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3734153 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011176 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105123 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3692421 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41732 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3734153 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2697404999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 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blocks. -system.cpu.l2cache.tags.avg_refs 7.370374 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 339424 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65327.181695 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2981337 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404586 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.368859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 5872511750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54484.622776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10842.127094 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831369 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.165438 # Average percentage of cache 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mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -927,86 +939,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1395422 # number of replacements +system.cpu.dcache.tags.replacements 1395163 # number of replacements system.cpu.dcache.tags.tagsinuse 511.982303 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13764943 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395934 # 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latency +system.cpu.dcache.demand_avg_miss_latency::total 29181.556999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29181.556999 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 29181.556999 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1015,64 +1027,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838282 # number of writebacks -system.cpu.dcache.writebacks::total 838282 # number of writebacks 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(read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37179857093 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37179857093 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37179857093 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423313500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423313500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2002790500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002790500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3426104000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426104000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119270 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049471 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086477 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086477 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090951 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090951 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090951 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25043.065898 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.065898 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33764.427538 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33764.427538 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11385.884019 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11385.884019 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26967.720641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26967.720641 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.inst 396694 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396694 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 396694 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396694 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 1074228 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074228 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 304237 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304237 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 17249 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17249 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 1378465 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378465 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 1378465 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378465 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 26911701750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26911701750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10289625346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10289625346 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 196226500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196226500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 37201327096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 37201327096 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 37201327096 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 37201327096 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 1423395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423395500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 2003794000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2003794000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 3427189500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3427189500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.119254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119254 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.086242 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086242 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090941 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.090941 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090941 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 25052.132089 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25052.132089 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 33821.084700 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33821.084700 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11376.108760 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11376.108760 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26987.502110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26987.502110 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 683e407e9..05acb9522 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,126 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.903124 # Number of seconds simulated -sim_ticks 1903123778500 # Number of ticks simulated -final_tick 1903123778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.905068 # Number of seconds simulated +sim_ticks 1905067807000 # Number of ticks simulated +final_tick 1905067807000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 103415 # Simulator instruction rate (inst/s) -host_op_rate 103415 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3505224116 # Simulator tick rate (ticks/s) -host_mem_usage 322696 # Number of bytes of host memory used -host_seconds 542.94 # Real time elapsed on the host -sim_insts 56148221 # Number of instructions simulated -sim_ops 56148221 # Number of ops (including micro ops) simulated +host_inst_rate 162284 # Simulator instruction rate (inst/s) +host_op_rate 162284 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5403466257 # Simulator tick rate (ticks/s) +host_mem_usage 375680 # Number of bytes of host memory used +host_seconds 352.56 # Real time elapsed on the host +sim_insts 57215334 # Number of instructions simulated +sim_ops 57215334 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 744192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24296448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 865344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24709248 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 238144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1067328 # Number of bytes read from this memory -system.physmem.bytes_read::total 26347072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 744192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 238144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 982336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5275328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 118912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 545600 # Number of bytes read from this memory +system.physmem.bytes_read::total 26240064 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 865344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 118912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 984256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5157696 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7934656 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 11628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 379632 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7817024 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386082 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16677 # Number of read requests responded to by this memory -system.physmem.num_reads::total 411673 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82427 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1858 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 8525 # Number of read requests responded to by this memory +system.physmem.num_reads::total 410001 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 80589 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123979 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 391037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12766615 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 122141 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 454233 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12970272 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 125133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 560830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13844119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 391037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 125133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2771931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1397349 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4169280 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2771931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 391037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12766615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1397853 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 125133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 560830 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18013399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 411673 # Number of read requests accepted -system.physmem.writeReqs 123979 # Number of write requests accepted -system.physmem.readBursts 411673 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 123979 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26335040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 7932928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26347072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7934656 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::cpu1.inst 62419 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 286394 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13773822 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 454233 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 62419 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 516651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2707356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1395923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4103279 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2707356 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 454233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12970272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1396427 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 62419 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 286394 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17877100 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 410001 # Number of read requests accepted +system.physmem.writeReqs 122141 # Number of write requests accepted +system.physmem.readBursts 410001 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 122141 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26227648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 12416 # Total number of bytes read from write queue +system.physmem.bytesWritten 7815104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26240064 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7817024 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 194 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 3444 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25632 # Per bank write bursts -system.physmem.perBankRdBursts::1 25720 # Per bank write bursts -system.physmem.perBankRdBursts::2 26346 # Per bank write bursts -system.physmem.perBankRdBursts::3 25660 # Per bank write bursts -system.physmem.perBankRdBursts::4 25672 # Per bank write bursts -system.physmem.perBankRdBursts::5 25150 # Per bank write bursts -system.physmem.perBankRdBursts::6 25568 # Per bank write bursts -system.physmem.perBankRdBursts::7 25491 # Per bank write bursts -system.physmem.perBankRdBursts::8 25973 # Per bank write bursts -system.physmem.perBankRdBursts::9 26167 # Per bank write bursts -system.physmem.perBankRdBursts::10 25812 # Per bank write bursts -system.physmem.perBankRdBursts::11 25687 # Per bank write bursts -system.physmem.perBankRdBursts::12 26023 # Per bank write bursts -system.physmem.perBankRdBursts::13 25844 # Per bank write bursts -system.physmem.perBankRdBursts::14 25108 # Per bank write bursts -system.physmem.perBankRdBursts::15 25632 # Per bank write bursts -system.physmem.perBankWrBursts::0 8431 # Per bank write bursts -system.physmem.perBankWrBursts::1 7989 # Per bank write bursts -system.physmem.perBankWrBursts::2 8275 # Per bank write bursts -system.physmem.perBankWrBursts::3 7382 # Per bank write bursts -system.physmem.perBankWrBursts::4 7684 # Per bank write bursts -system.physmem.perBankWrBursts::5 7400 # Per bank write bursts -system.physmem.perBankWrBursts::6 7193 # Per bank write bursts -system.physmem.perBankWrBursts::7 7021 # Per bank write bursts -system.physmem.perBankWrBursts::8 7374 # Per bank write bursts -system.physmem.perBankWrBursts::9 7755 # Per bank write bursts -system.physmem.perBankWrBursts::10 7777 # Per bank write bursts -system.physmem.perBankWrBursts::11 7454 # Per bank write bursts -system.physmem.perBankWrBursts::12 8052 # Per bank write bursts -system.physmem.perBankWrBursts::13 8097 # Per bank write bursts -system.physmem.perBankWrBursts::14 7762 # Per bank write bursts -system.physmem.perBankWrBursts::15 8306 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 6364 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25988 # Per bank write bursts +system.physmem.perBankRdBursts::1 25697 # Per bank write bursts +system.physmem.perBankRdBursts::2 25753 # Per bank write bursts +system.physmem.perBankRdBursts::3 25768 # Per bank write bursts +system.physmem.perBankRdBursts::4 25192 # Per bank write bursts +system.physmem.perBankRdBursts::5 25524 # Per bank write bursts +system.physmem.perBankRdBursts::6 25779 # Per bank write bursts +system.physmem.perBankRdBursts::7 25095 # Per bank write bursts +system.physmem.perBankRdBursts::8 25528 # Per bank write bursts +system.physmem.perBankRdBursts::9 25751 # Per bank write bursts +system.physmem.perBankRdBursts::10 25719 # Per bank write bursts +system.physmem.perBankRdBursts::11 25446 # Per bank write bursts +system.physmem.perBankRdBursts::12 25795 # Per bank write bursts +system.physmem.perBankRdBursts::13 25643 # Per bank write bursts +system.physmem.perBankRdBursts::14 25930 # Per bank write bursts +system.physmem.perBankRdBursts::15 25199 # Per bank write bursts +system.physmem.perBankWrBursts::0 8301 # Per bank write bursts +system.physmem.perBankWrBursts::1 7506 # Per bank write bursts +system.physmem.perBankWrBursts::2 7807 # Per bank write bursts +system.physmem.perBankWrBursts::3 7337 # Per bank write bursts +system.physmem.perBankWrBursts::4 6902 # Per bank write bursts +system.physmem.perBankWrBursts::5 7063 # Per bank write bursts +system.physmem.perBankWrBursts::6 7447 # Per bank write bursts +system.physmem.perBankWrBursts::7 6982 # Per bank write bursts +system.physmem.perBankWrBursts::8 7245 # Per bank write bursts +system.physmem.perBankWrBursts::9 7339 # Per bank write bursts +system.physmem.perBankWrBursts::10 7570 # Per bank write bursts +system.physmem.perBankWrBursts::11 7510 # Per bank write bursts +system.physmem.perBankWrBursts::12 8378 # Per bank write bursts +system.physmem.perBankWrBursts::13 8362 # Per bank write bursts +system.physmem.perBankWrBursts::14 8512 # Per bank write bursts +system.physmem.perBankWrBursts::15 7850 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 1903119235000 # Total gap between requests +system.physmem.totGap 1905063366000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 411673 # Read request sizes (log2) +system.physmem.readPktSize::6 410001 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 123979 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317912 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 77 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 122141 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 40469 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 73 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -161,357 +161,367 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5849 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6098 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 278 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64910 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 527.930488 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 320.008348 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.202697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14944 23.02% 23.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11454 17.65% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5213 8.03% 48.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2920 4.50% 53.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2279 3.51% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1787 2.75% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1551 2.39% 61.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1716 2.64% 64.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 23046 35.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64910 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5635 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 73.021650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2812.727565 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5632 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6416 # What write queue length does an incoming req see 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does an incoming req see +system.physmem.wrQLenPdf::42 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64430 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 528.357101 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.789036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.784578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14909 23.14% 23.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11361 17.63% 40.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5102 7.92% 48.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2869 4.45% 53.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2286 3.55% 56.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 2.62% 59.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1558 2.42% 61.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1655 2.57% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23003 35.70% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64430 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5515 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 74.305712 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2843.118152 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5512 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5635 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.996806 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.958563 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 19.289473 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4843 85.94% 85.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 143 2.54% 88.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.18% 88.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 227 4.03% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 45 0.80% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 4 0.07% 93.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 10 0.18% 93.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.18% 93.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 34 0.60% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.11% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.09% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.04% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 9 0.16% 94.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.04% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.07% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.02% 95.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 41 0.73% 95.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 13 0.23% 95.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.04% 96.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 176 3.12% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.09% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 3 0.05% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 3 0.05% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.11% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.05% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 6 0.11% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.18% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.11% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5635 # Writes before turning the bus around for reads -system.physmem.totQLat 3887945250 # Total ticks spent queuing -system.physmem.totMemAccLat 11603289000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2057425000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9448.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5515 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5515 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.141614 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.970992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 20.024334 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4751 86.15% 86.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 123 2.23% 88.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 15 0.27% 88.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 231 4.19% 92.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 39 0.71% 93.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 12 0.22% 93.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 8 0.15% 93.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 4 0.07% 93.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 23 0.42% 94.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 3 0.05% 94.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.09% 94.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.05% 94.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.09% 94.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 28 0.51% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 10 0.18% 95.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.04% 95.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 17 0.31% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 177 3.21% 99.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 3 0.05% 99.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 4 0.07% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 4 0.07% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 5 0.09% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 3 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 5 0.09% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 8 0.15% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 4 0.07% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 2 0.04% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 3 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5515 # Writes before turning the bus around for reads +system.physmem.totQLat 3875472500 # Total ticks spent queuing +system.physmem.totMemAccLat 11559353750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9456.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28198.57 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.84 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 4.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.17 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28206.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.77 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing -system.physmem.readRowHits 371100 # Number of row buffer hits during reads -system.physmem.writeRowHits 99427 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.20 # Row buffer hit rate for writes -system.physmem.avgGap 3552902.32 # Average gap between requests -system.physmem.pageHitRate 87.87 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1802319562500 # Time in different power states -system.physmem.memoryStateTime::REF 63549460000 # Time in different power states +system.physmem.avgRdQLen 1.97 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.10 # Average write queue length when enqueuing +system.physmem.readRowHits 369467 # Number of row buffer hits during reads +system.physmem.writeRowHits 98020 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.25 # Row buffer hit rate for writes +system.physmem.avgGap 3579990.62 # Average gap between requests +system.physmem.pageHitRate 87.88 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1804432107750 # Time in different power states +system.physmem.memoryStateTime::REF 63614200000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 37254262500 # Time in different power states +system.physmem.memoryStateTime::ACT 37016700250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18054612 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296849 # Transaction distribution -system.membus.trans_dist::ReadResp 296569 # Transaction distribution -system.membus.trans_dist::WriteReq 12351 # Transaction distribution -system.membus.trans_dist::WriteResp 12351 # Transaction distribution -system.membus.trans_dist::Writeback 82427 # Transaction distribution +system.membus.trans_dist::ReadReq 296853 # Transaction distribution +system.membus.trans_dist::ReadResp 296773 # Transaction distribution +system.membus.trans_dist::WriteReq 13665 # Transaction distribution +system.membus.trans_dist::WriteResp 13665 # Transaction distribution +system.membus.trans_dist::Writeback 80589 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 5284 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1479 # Transaction distribution -system.membus.trans_dist::UpgradeResp 3444 # Transaction distribution -system.membus.trans_dist::ReadExReq 122594 # Transaction distribution -system.membus.trans_dist::ReadExResp 122459 # Transaction distribution -system.membus.trans_dist::BadAddressError 280 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 39092 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 916085 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 560 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 955737 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 83294 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1039031 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 68194 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 31621440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 31689634 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 34349922 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 34349922 # Total data (bytes) -system.membus.snoop_data_through_bus 10240 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 35504996 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeReq 14563 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9639 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6364 # Transaction distribution +system.membus.trans_dist::ReadExReq 121274 # Transaction distribution +system.membus.trans_dist::ReadExResp 120582 # Transaction distribution +system.membus.trans_dist::BadAddressError 80 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 41714 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 931819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 160 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 973693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 83296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1056989 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 78682 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31396800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31475482 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 34135770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 18692 # Total snoops (count) +system.membus.snoop_fanout::samples 557285 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 557285 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 557285 # Request fanout histogram +system.membus.reqLayer0.occupancy 40450499 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1560042750 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1545398747 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 374000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 102000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3834491323 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3825672402 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43141738 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 43153245 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 345839 # number of replacements -system.l2c.tags.tagsinuse 65302.356632 # Cycle average of tags in use -system.l2c.tags.total_refs 2646364 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 411006 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.438748 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093732750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53566.898021 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4193.415796 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5564.276304 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1386.450480 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 591.316031 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.817366 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063986 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.084904 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.021156 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996435 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65167 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 225 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 6029 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 50524 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994370 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27707761 # Number of tag accesses -system.l2c.tags.data_accesses 27707761 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 751132 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 546267 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 350558 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 278844 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1926801 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 841911 # number of Writeback hits -system.l2c.Writeback_hits::total 841911 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 128 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 75 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 203 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 37 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 73 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 140399 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 48308 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 188707 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 751132 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 686666 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 350558 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 327152 # number of demand (read+write) hits -system.l2c.demand_hits::total 2115508 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 751132 # number of overall hits -system.l2c.overall_hits::cpu0.data 686666 # number of overall hits -system.l2c.overall_hits::cpu1.inst 350558 # number of overall hits -system.l2c.overall_hits::cpu1.data 327152 # number of overall hits -system.l2c.overall_hits::total 2115508 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 11641 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 272205 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3725 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1926 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289497 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2575 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 542 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3117 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 63 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 103 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 166 # number of SCUpgradeReq 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-system.l2c.ReadReq_miss_latency::cpu0.inst 889120500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17862600250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 290708250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 148179250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19190608250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 882962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1281445 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 2164407 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 245491 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187992 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 433483 # number of SCUpgradeReq miss cycles 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overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1604702959 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29525405841 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 762773 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 818472 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 354283 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 280770 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2216298 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 841911 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 841911 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2703 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 617 # number of UpgradeReq accesses(hits+misses) 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-system.l2c.demand_accesses::total 2527625 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 762773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1066474 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 354283 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 344095 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2527625 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015261 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.332577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010514 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.006860 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.130622 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.952645 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.878444 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.938855 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636364 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.735714 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.694561 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.433880 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.237142 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.393862 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015261 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.356134 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010514 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.049239 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.163045 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015261 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.356134 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010514 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.049239 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.163045 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76378.360966 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65621.866792 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78042.483221 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76936.266874 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66289.489183 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 342.897864 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2364.289668 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 694.387873 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3896.682540 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1825.165049 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 2611.343373 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82509.538600 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 96991.656722 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84283.131553 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76378.360966 # average overall miss latency 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rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783743 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.881289 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.934010 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.966278 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.949968 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.450515 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.180348 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.411506 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016570 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.316621 # mshr miss rate for demand accesses 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misses +system.iocache.WriteInvalidateReq_misses::total 2 # number of WriteInvalidateReq misses +system.iocache.demand_misses::tsunami.ide 177 # number of demand (read+write) misses +system.iocache.demand_misses::total 177 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 177 # number of overall misses +system.iocache.overall_misses::total 177 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21586383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21586383 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21586383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21586383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21586383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21586383 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 177 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 177 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41554 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41554 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::tsunami.ide 177 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 177 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 177 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 177 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.000048 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000048 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122082.188571 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122082.188571 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122082.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122082.188571 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122082.188571 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121956.966102 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 121956.966102 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 121956.966102 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 121956.966102 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 121956.966102 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -705,38 +719,38 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 41552 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::tsunami.ide 175 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 175 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 177 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 175 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 175 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 175 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12263383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12263383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2507056568 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2507056568 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12263383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12263383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12263383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12263383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 177 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 177 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 177 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 177 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12381383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12381383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2512854560 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12381383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12381383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12381383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.999952 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999952 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70076.474286 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60335.400655 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60335.400655 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70076.474286 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70076.474286 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 69951.316384 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60474.936465 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69951.316384 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 69951.316384 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -750,35 +764,35 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 13702956 # Number of BP lookups -system.cpu0.branchPred.condPredicted 11991857 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 276088 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 8588922 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4683455 # Number of BTB hits +system.cpu0.branchPred.lookups 14962614 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13045209 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 300344 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9143692 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5116520 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 54.529020 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 677984 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 15448 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 55.956828 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 756655 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 14726 # Number of incorrect RAS predictions. system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7950804 # DTB read hits -system.cpu0.dtb.read_misses 30543 # DTB read misses -system.cpu0.dtb.read_acv 546 # DTB read access violations -system.cpu0.dtb.read_accesses 683229 # DTB read accesses -system.cpu0.dtb.write_hits 5159026 # DTB write hits -system.cpu0.dtb.write_misses 6845 # DTB write misses -system.cpu0.dtb.write_acv 353 # DTB write access violations -system.cpu0.dtb.write_accesses 234573 # DTB write accesses -system.cpu0.dtb.data_hits 13109830 # DTB hits -system.cpu0.dtb.data_misses 37388 # DTB misses -system.cpu0.dtb.data_acv 899 # DTB access violations -system.cpu0.dtb.data_accesses 917802 # DTB accesses -system.cpu0.itb.fetch_hits 1312718 # ITB hits -system.cpu0.itb.fetch_misses 29261 # ITB misses -system.cpu0.itb.fetch_acv 629 # ITB acv -system.cpu0.itb.fetch_accesses 1341979 # ITB accesses +system.cpu0.dtb.read_hits 8668714 # DTB read hits +system.cpu0.dtb.read_misses 31568 # DTB read misses +system.cpu0.dtb.read_acv 533 # DTB read access violations +system.cpu0.dtb.read_accesses 683834 # DTB read accesses +system.cpu0.dtb.write_hits 5507711 # DTB write hits +system.cpu0.dtb.write_misses 6832 # DTB write misses +system.cpu0.dtb.write_acv 377 # DTB write access violations +system.cpu0.dtb.write_accesses 235007 # DTB write accesses +system.cpu0.dtb.data_hits 14176425 # DTB hits +system.cpu0.dtb.data_misses 38400 # DTB misses +system.cpu0.dtb.data_acv 910 # DTB access violations +system.cpu0.dtb.data_accesses 918841 # DTB accesses +system.cpu0.itb.fetch_hits 1355401 # ITB hits +system.cpu0.itb.fetch_misses 29256 # ITB misses +system.cpu0.itb.fetch_acv 621 # ITB acv +system.cpu0.itb.fetch_accesses 1384657 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -791,304 +805,305 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 99665250 # number of cpu cycles simulated +system.cpu0.numCycles 108456707 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 22511576 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 60582407 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 13702956 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5361439 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 70984108 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 933480 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 621 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 27412 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1463366 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 292819 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 7109889 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 200075 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 95746858 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.632735 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.928110 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 24325754 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 66694894 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 14962614 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 5873175 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 76828249 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1001726 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 825 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 30281 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1454626 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 459540 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 204 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 7777949 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 213350 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103600342 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.643771 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.943909 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 84335489 88.08% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 757900 0.79% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1598110 1.67% 90.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 658612 0.69% 91.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2290747 2.39% 93.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 510807 0.53% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 540667 0.56% 94.72% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 744782 0.78% 95.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4309744 4.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 91056774 87.89% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 810107 0.78% 88.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1760430 1.70% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 739408 0.71% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2516394 2.43% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557837 0.54% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 633248 0.61% 94.67% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 717698 0.69% 95.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4808446 4.64% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 95746858 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.137490 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.607859 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18154184 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 68366814 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7221268 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1568077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 436514 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 432928 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 30567 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 53177978 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 98719 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 436514 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18925396 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 44877173 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 16564638 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 7942906 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7000229 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 51314401 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 200370 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1702156 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 121650 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3596195 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 34369689 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 62476617 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 62360377 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 107565 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30276917 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4092764 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1298231 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 191875 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11393500 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 8037568 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5366781 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1135735 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 800748 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 45795204 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1644687 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 45103865 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 41971 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 5328763 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 2477826 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1134880 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 95746858 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.471074 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.201865 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103600342 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.137959 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.614945 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19762809 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 73625982 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8017389 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1725855 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 468306 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 492047 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 33030 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 58728782 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 102789 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 468306 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 20585060 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 48251734 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 17899835 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 8819055 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7576350 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 56729728 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 201548 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2018005 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 142949 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 3756211 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 38050244 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 69305662 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 69181835 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 114815 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 33467059 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4583177 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1358842 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 197413 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12487165 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 8791454 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5770533 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1295730 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 947864 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 50680779 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1726956 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 49798033 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 52306 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 5972660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2859786 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1187974 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103600342 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.480674 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.214257 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 76985468 80.41% 80.41% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 8252195 8.62% 89.02% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3430688 3.58% 92.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2350675 2.46% 95.06% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2374207 2.48% 97.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1175968 1.23% 98.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 779493 0.81% 99.58% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 300669 0.31% 99.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 97495 0.10% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 83011266 80.13% 80.13% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 8965198 8.65% 88.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3720190 3.59% 92.37% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2652497 2.56% 94.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2683429 2.59% 97.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1272361 1.23% 98.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 837773 0.81% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 348219 0.34% 99.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109409 0.11% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 95746858 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103600342 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 143906 17.61% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 17.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 398143 48.73% 66.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 274956 33.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 174041 19.05% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.05% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 435557 47.67% 66.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 304020 33.28% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 3780 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30829458 68.35% 68.36% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46395 0.10% 68.46% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 26948 0.06% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.52% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.53% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 8252345 18.30% 86.82% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5217820 11.57% 98.39% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 725236 1.61% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 34383436 69.05% 69.05% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 54432 0.11% 69.16% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.16% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 27661 0.06% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.22% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 8987932 18.05% 87.27% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5577936 11.20% 98.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 760973 1.53% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 45103865 # Type of FU issued -system.cpu0.iq.rate 0.452554 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 817005 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018114 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 186342910 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 52562719 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 43916640 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 470653 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 221373 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 216432 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 45663938 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 253152 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 522094 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 49798033 # Type of FU issued +system.cpu0.iq.rate 0.459151 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 913618 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018346 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 203658933 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 58161397 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 48529720 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 503398 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 236532 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 231367 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 50437037 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 270834 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 558638 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 946690 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 4799 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 15752 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 387148 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1034329 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4271 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17854 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 485625 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 13610 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 357638 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18828 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 348593 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 436514 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 41413967 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1424350 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 50298451 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 103444 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 8037568 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5366781 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1456887 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 31578 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1238658 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 15752 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 134081 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 309122 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 443203 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 44677716 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 8001376 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 426148 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 468306 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 44263410 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1515089 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 55600538 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 120472 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 8791454 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5770533 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1526368 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 47186 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1245112 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17854 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151677 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 326896 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 478573 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 49327282 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 8721913 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 470750 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 2858560 # number of nop insts executed -system.cpu0.iew.exec_refs 13178604 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7039370 # Number of branches executed -system.cpu0.iew.exec_stores 5177228 # Number of stores executed -system.cpu0.iew.exec_rate 0.448278 # Inst execution rate -system.cpu0.iew.wb_sent 44227196 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44133072 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 22691402 # num instructions producing a value -system.cpu0.iew.wb_consumers 31140086 # num instructions consuming a value +system.cpu0.iew.exec_nop 3192803 # number of nop insts executed +system.cpu0.iew.exec_refs 14249477 # number of memory reference insts executed +system.cpu0.iew.exec_branches 7854369 # Number of branches executed +system.cpu0.iew.exec_stores 5527564 # Number of stores executed +system.cpu0.iew.exec_rate 0.454811 # Inst execution rate +system.cpu0.iew.wb_sent 48871282 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 48761087 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 25232648 # num instructions producing a value +system.cpu0.iew.wb_consumers 34850080 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.442813 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.728688 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.449590 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.724034 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 5846321 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 509807 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 407712 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 94708833 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.468364 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.405169 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6529157 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 538982 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 437949 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 102449449 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.477940 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.411753 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 79035549 83.45% 83.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6314508 6.67% 90.12% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3292930 3.48% 93.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1802282 1.90% 95.50% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1366338 1.44% 96.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 489382 0.52% 97.46% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 366889 0.39% 97.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 390234 0.41% 98.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1650721 1.74% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 85074848 83.04% 83.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6905483 6.74% 89.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3794087 3.70% 93.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1998795 1.95% 95.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1509892 1.47% 96.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 553563 0.54% 97.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 413229 0.40% 97.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 408476 0.40% 98.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1791076 1.75% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 94708833 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 44358216 # Number of instructions committed -system.cpu0.commit.committedOps 44358216 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 102449449 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 48964739 # Number of instructions committed +system.cpu0.commit.committedOps 48964739 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12070511 # Number of memory references committed -system.cpu0.commit.loads 7090878 # Number of loads committed -system.cpu0.commit.membars 170277 # Number of memory barriers committed -system.cpu0.commit.branches 6663650 # Number of branches committed -system.cpu0.commit.fp_insts 213529 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 41141903 # Number of committed integer instructions. -system.cpu0.commit.function_calls 549728 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2498518 5.63% 5.63% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 28814427 64.96% 70.59% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 45393 0.10% 70.69% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.69% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 26477 0.06% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.75% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.76% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 7261155 16.37% 87.13% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 4985127 11.24% 98.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 725236 1.63% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13042033 # Number of memory references committed +system.cpu0.commit.loads 7757125 # Number of loads committed +system.cpu0.commit.membars 182252 # Number of memory barriers committed +system.cpu0.commit.branches 7421354 # Number of branches committed +system.cpu0.commit.fp_insts 228314 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 45387875 # Number of committed integer instructions. +system.cpu0.commit.function_calls 614232 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2794177 5.71% 5.71% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 32097051 65.55% 71.26% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 53183 0.11% 71.37% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 71.37% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 27190 0.06% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.42% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.43% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 7939377 16.21% 87.64% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5290905 10.81% 98.45% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 760973 1.55% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 44358216 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1650721 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 48964739 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1791076 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 143064224 # The number of ROB reads -system.cpu0.rob.rob_writes 101447849 # The number of ROB writes -system.cpu0.timesIdled 414726 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3918392 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3706577488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 41863465 # Number of Instructions Simulated -system.cpu0.committedOps 41863465 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.380721 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.380721 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.420041 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.420041 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 58777310 # number of integer regfile reads -system.cpu0.int_regfile_writes 31962259 # number of integer regfile writes -system.cpu0.fp_regfile_reads 106639 # number of floating regfile reads -system.cpu0.fp_regfile_writes 106808 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1588469 # number of misc regfile reads -system.cpu0.misc_regfile_writes 729535 # number of misc regfile writes +system.cpu0.rob.rob_reads 155949601 # The number of ROB reads +system.cpu0.rob.rob_writes 112132496 # The number of ROB writes +system.cpu0.timesIdled 444606 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 4856365 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3701678908 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 46174329 # Number of Instructions Simulated +system.cpu0.committedOps 46174329 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.348853 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.348853 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.425740 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.425740 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 65048250 # number of integer regfile reads +system.cpu0.int_regfile_writes 35377381 # number of integer regfile writes +system.cpu0.fp_regfile_reads 113752 # number of floating regfile reads +system.cpu0.fp_regfile_writes 114375 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1675774 # number of misc regfile reads +system.cpu0.misc_regfile_writes 759002 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1120,50 +1135,61 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 115690704 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2250904 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2250609 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12351 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12351 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 841911 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2231724 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231628 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13665 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13665 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 804733 # Transaction distribution system.toL2Bus.trans_dist::WriteInvalidateReq 41559 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 5326 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 1552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 6878 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 312265 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 312265 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 280 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1525692 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2740000 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 708608 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1000724 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5975024 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 48817472 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 104660497 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22674112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 39558737 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 215710818 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 215700578 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4473152 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5085967365 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeReq 14709 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 9717 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 24426 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295921 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295921 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 80 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1632137 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3219560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 626624 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 407513 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5885834 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 52223552 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 123671600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20051136 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 14868394 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 210814682 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 92075 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3391171 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012307 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110253 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3349435 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41736 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3391171 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4911486557 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 720000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3437989936 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3677796473 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4906988127 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 5655554210 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1597018302 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 1411093549 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1654443775 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1434388 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7370 # Transaction distribution -system.iobus.trans_dist::ReadResp 7370 # Transaction distribution -system.iobus.trans_dist::WriteReq 53903 # Transaction distribution -system.iobus.trans_dist::WriteResp 53903 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 10492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) +system.toL2Bus.respLayer3.occupancy 701201756 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 7369 # Transaction distribution +system.iobus.trans_dist::ReadResp 7369 # Transaction distribution +system.iobus.trans_dist::WriteReq 55215 # Transaction distribution +system.iobus.trans_dist::WriteResp 55217 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 2 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13126 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 464 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1174,30 +1200,29 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 39092 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83454 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 122546 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 41968 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 68194 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661624 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2729818 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2729818 # Total data (bytes) -system.iobus.reqLayer0.occupancy 9847000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 41714 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83458 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 52504 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 78682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2740322 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 12481000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 356000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 347000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1217,267 +1242,267 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374411689 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374418188 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 26741000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28049000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42019262 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42021755 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 762211 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.848890 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6309809 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 762721 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 8.272762 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26485928250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.848890 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.993845 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.993845 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 418 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7872808 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7872808 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6309809 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6309809 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6309809 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6309809 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6309809 # number of overall hits -system.cpu0.icache.overall_hits::total 6309809 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 800080 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 800080 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 800080 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 800080 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 800080 # number of overall misses -system.cpu0.icache.overall_misses::total 800080 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11341096711 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 11341096711 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11341096711 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 11341096711 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11341096711 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 11341096711 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7109889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7109889 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7109889 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7109889 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7109889 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7109889 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.112531 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.112531 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.112531 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.112531 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.112531 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.112531 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14174.953393 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14174.953393 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14174.953393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14174.953393 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14174.953393 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3387 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 815495 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.595712 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6922237 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 816007 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 8.483061 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 26485869250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.595712 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.995304 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 32 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 411 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 8594091 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 8594091 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6922237 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6922237 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6922237 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6922237 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6922237 # number of overall hits +system.cpu0.icache.overall_hits::total 6922237 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 855710 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 855710 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 855710 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 855710 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 855710 # number of overall misses +system.cpu0.icache.overall_misses::total 855710 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12231378721 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12231378721 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12231378721 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12231378721 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7777947 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7777947 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7777947 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7777947 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7777947 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110017 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110017 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110017 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110017 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110017 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14293.836371 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14293.836371 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14293.836371 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14293.836371 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4554 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 162 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 181 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.907407 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.160221 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 37161 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 37161 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 37161 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 37161 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 37161 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 37161 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 762919 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 762919 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 762919 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 762919 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 762919 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 762919 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9350852559 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9350852559 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9350852559 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9350852559 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9350852559 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9350852559 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.107304 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.107304 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.107304 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.107304 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12256.678047 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12256.678047 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12256.678047 # average overall mshr miss latency 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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 1069035 # number of replacements -system.cpu0.dcache.tags.tagsinuse 482.779727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9141371 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1069547 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.546956 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1223787 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.953471 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9930066 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1224299 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.110818 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 482.779727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.942929 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.942929 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.953471 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988190 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988190 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 229 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 49546788 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 49546788 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5665393 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5665393 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3152024 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3152024 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147109 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147109 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 170256 # number of StoreCondReq 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miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4788059 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4788059 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 110494148791 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 110494148791 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 110494148791 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 110494148791 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6987564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6987564 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4796305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4796305 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 163719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 163719 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 171022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 171022 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11783869 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11783869 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11783869 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11783869 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.189218 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.189218 # miss rate for ReadReq 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27356.026485 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27356.026485 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45202.008596 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45202.008596 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16085.640759 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16085.640759 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6250.729765 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6250.729765 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 37247.913936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37247.913936 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 37247.913936 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3702426 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3454 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 160595 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 88 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.054429 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 39.250000 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 53654077 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 53654077 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6167393 # number of ReadReq hits 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of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39188841077 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77581958562 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77581958562 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 288599741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 288599741 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 35650235 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 35650235 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 116770799639 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 116770799639 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 116770799639 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 116770799639 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7666040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7666040 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5094064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5094064 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 168182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 168182 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 176015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 176015 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12760104 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12760104 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12760104 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12760104 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195492 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195492 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327286 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.327286 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.113454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.113454 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.026822 # miss rate for StoreCondReq accesses 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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15124.979875 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7551.416014 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7551.416014 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36884.350220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36884.350220 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36884.350220 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 3791444 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2983 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 159835 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 87 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.720987 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 34.287356 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 568073 # number of writebacks -system.cpu0.dcache.writebacks::total 568073 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 499697 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 499697 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1402831 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1402831 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4326 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1902528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1902528 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1902528 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1902528 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 822474 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 822474 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 241450 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 241450 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 12284 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 12284 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 766 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1063924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1063924 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1063924 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1063924 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 24909734008 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 24909734008 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10782476086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10782476086 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 145144507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145144507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3254941 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3254941 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 35692210094 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 35692210094 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 35692210094 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 35692210094 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 992378000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 992378000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1672126998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1672126998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2664504998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2664504998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.117705 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.117705 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050341 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.075031 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.075031 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004479 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004479 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.090286 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.090286 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.090286 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 30286.348271 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 30286.348271 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 44657.179896 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 44657.179896 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11815.736486 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11815.736486 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4249.270235 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4249.270235 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33547.706503 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33547.706503 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 710527 # number of writebacks +system.cpu0.dcache.writebacks::total 710527 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 518299 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 518299 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1417662 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1417662 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1935961 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1935961 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1935961 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1935961 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 980348 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 980348 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 249554 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 249554 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 14638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 14638 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 4721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4721 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1229902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1229902 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1229902 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1229902 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27067717433 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27067717433 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11277928082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11277928082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 147839258 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 147839258 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 26206765 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 26206765 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38345645515 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38345645515 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38345645515 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38345645515 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1453124500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1453124500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2199080998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2199080998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3652205498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3652205498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127882 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127882 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.087037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.087037 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.026822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.026822 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.096387 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096387 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.096387 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27610.315350 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27610.315350 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45192.335454 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45192.335454 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 10099.689712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 10099.689712 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5551.104639 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5551.104639 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31177.805642 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31177.805642 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1485,35 +1510,35 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 5770916 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5004196 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 122577 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3556553 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1526133 # Number of BTB hits +system.cpu1.branchPred.lookups 4639832 # Number of BP lookups +system.cpu1.branchPred.condPredicted 4063901 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 82203 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2874870 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1132301 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 42.910453 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 301064 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7748 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 39.386164 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 224009 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7064 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 3015540 # DTB read hits -system.cpu1.dtb.read_misses 12269 # DTB read misses -system.cpu1.dtb.read_acv 5 # DTB read access violations -system.cpu1.dtb.read_accesses 293761 # DTB read accesses -system.cpu1.dtb.write_hits 1836726 # DTB write hits -system.cpu1.dtb.write_misses 2353 # DTB write misses -system.cpu1.dtb.write_acv 39 # DTB write access violations -system.cpu1.dtb.write_accesses 109652 # DTB write accesses -system.cpu1.dtb.data_hits 4852266 # DTB hits -system.cpu1.dtb.data_misses 14622 # DTB misses -system.cpu1.dtb.data_acv 44 # DTB access violations -system.cpu1.dtb.data_accesses 403413 # DTB accesses -system.cpu1.itb.fetch_hits 632341 # ITB hits -system.cpu1.itb.fetch_misses 5352 # ITB misses -system.cpu1.itb.fetch_acv 51 # ITB acv -system.cpu1.itb.fetch_accesses 637693 # ITB accesses +system.cpu1.dtb.read_hits 2413283 # DTB read hits +system.cpu1.dtb.read_misses 10075 # DTB read misses +system.cpu1.dtb.read_acv 6 # DTB read access violations +system.cpu1.dtb.read_accesses 292262 # DTB read accesses +system.cpu1.dtb.write_hits 1597058 # DTB write hits +system.cpu1.dtb.write_misses 2093 # DTB write misses +system.cpu1.dtb.write_acv 37 # DTB write access violations +system.cpu1.dtb.write_accesses 110264 # DTB write accesses +system.cpu1.dtb.data_hits 4010341 # DTB hits +system.cpu1.dtb.data_misses 12168 # DTB misses +system.cpu1.dtb.data_acv 43 # DTB access violations +system.cpu1.dtb.data_accesses 402526 # DTB accesses +system.cpu1.itb.fetch_hits 608432 # ITB hits +system.cpu1.itb.fetch_misses 5602 # ITB misses +system.cpu1.itb.fetch_acv 65 # ITB acv +system.cpu1.itb.fetch_accesses 614034 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1526,554 +1551,552 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 26335588 # number of cpu cycles simulated +system.cpu1.numCycles 19085086 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 9800268 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 22981944 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5770916 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 1827197 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14019681 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 419510 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 307 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 23776 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 208449 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 196331 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 53 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 2522136 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 89875 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 24458620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.939626 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.331670 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8490084 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 17874574 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4639832 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1356310 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 9216388 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 327612 # Number of cycles fetch has spent squashing +system.cpu1.fetch.MiscStallCycles 26792 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 219924 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 67319 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1967111 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 67009 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 18184335 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.982966 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.394246 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20375648 83.31% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 230665 0.94% 84.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 464859 1.90% 86.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 295118 1.21% 87.36% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 600413 2.45% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 204861 0.84% 90.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 257669 1.05% 91.70% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 270860 1.11% 92.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1758527 7.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15065350 82.85% 82.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 205923 1.13% 83.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 307986 1.69% 85.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 226074 1.24% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 391185 2.15% 89.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 151633 0.83% 89.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 170482 0.94% 90.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 296956 1.63% 92.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1368746 7.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 24458620 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.219130 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.872657 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 8213195 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 12716086 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 2925937 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 406668 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 196733 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 189397 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 13167 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 19294426 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 40930 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 196733 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8443455 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 3954170 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 7253500 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 3074788 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 1535972 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 18421784 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 5378 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 385976 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 36959 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 551165 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 12165906 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 21959681 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21890085 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 63650 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 10221482 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1944424 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 582778 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 59316 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 3316426 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3128488 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1940399 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 395849 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 259099 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 16224994 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 722304 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 15758531 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 26415 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2553169 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 1203962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 524576 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 24458620 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.644294 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.366216 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 18184335 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.243113 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.936573 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6979571 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 8518725 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 2274233 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 256003 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 155802 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 137194 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 8084 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 14619784 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 26597 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 155802 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7159934 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 614392 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 6924569 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 2350603 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 979033 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 13886683 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 9133 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 71770 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 16856 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 365854 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 9047331 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 16422939 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 16337871 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 78141 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 7835755 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1211576 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 562751 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 58900 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2353285 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 2494844 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1679253 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 277357 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 156260 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 12201401 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 661557 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 11978627 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 22551 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1735034 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 788886 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 473891 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 18184335 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.658733 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.375592 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 17964380 73.45% 73.45% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 2773024 11.34% 84.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 1191873 4.87% 89.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 895755 3.66% 93.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 840464 3.44% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 400907 1.64% 98.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 238226 0.97% 99.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 113179 0.46% 99.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 40812 0.17% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 13164849 72.40% 72.40% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 2231541 12.27% 84.67% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 929377 5.11% 89.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 639609 3.52% 93.30% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 582340 3.20% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 317160 1.74% 98.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 211313 1.16% 99.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 78701 0.43% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 29445 0.16% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 24458620 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 18184335 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 56470 15.54% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 15.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 184321 50.72% 66.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 122598 33.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 24291 8.14% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 162499 54.43% 62.57% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 111756 37.43% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 10371294 65.81% 65.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 24284 0.15% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 65.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 11773 0.07% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.06% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3139820 19.92% 86.00% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1865147 11.84% 97.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 340936 2.16% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 3518 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 7464610 62.32% 62.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 20078 0.17% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.51% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 12377 0.10% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1759 0.01% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 2524426 21.07% 83.71% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1623488 13.55% 97.26% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 328371 2.74% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 15758531 # Type of FU issued -system.cpu1.iq.rate 0.598374 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 363389 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.023060 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 56111313 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 19387392 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 15262127 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 254173 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 119441 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 117263 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 15982004 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 136398 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 157695 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 11978627 # Type of FU issued +system.cpu1.iq.rate 0.627643 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 298546 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.024923 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 42145115 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 14453685 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 11556214 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 317571 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 148430 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 146304 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 12102736 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 170919 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 117615 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 453605 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 1302 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 6552 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 197079 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 314973 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1097 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4259 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 145447 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 5589 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 74646 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 424 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 56672 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 196733 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 3102898 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 407577 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 17959821 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 47400 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3128488 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1940399 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 647154 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 24325 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 312873 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 6552 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 58721 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 143362 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 202083 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 15559963 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3035862 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 198568 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 155802 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 328818 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 249531 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 13597003 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 38106 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 2494844 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1679253 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 593871 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 4649 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 243688 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4259 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 37580 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 120039 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 157619 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 11824953 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 2433073 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 153674 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 1012523 # number of nop insts executed -system.cpu1.iew.exec_refs 4881099 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2446532 # Number of branches executed -system.cpu1.iew.exec_stores 1845237 # Number of stores executed -system.cpu1.iew.exec_rate 0.590834 # Inst execution rate -system.cpu1.iew.wb_sent 15420680 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 15379390 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 7566791 # num instructions producing a value -system.cpu1.iew.wb_consumers 10761562 # num instructions consuming a value +system.cpu1.iew.exec_nop 734045 # number of nop insts executed +system.cpu1.iew.exec_refs 4040076 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1766091 # Number of branches executed +system.cpu1.iew.exec_stores 1607003 # Number of stores executed +system.cpu1.iew.exec_rate 0.619591 # Inst execution rate +system.cpu1.iew.wb_sent 11733612 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 11702518 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 5498346 # num instructions producing a value +system.cpu1.iew.wb_consumers 7839453 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.583977 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.703131 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.613176 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.701369 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 2776166 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 197728 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 185190 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 23976589 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.630910 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.597118 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1874564 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 187666 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 145503 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 17835799 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.653281 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.639800 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 18550941 77.37% 77.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 2272481 9.48% 86.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1151381 4.80% 91.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 578443 2.41% 94.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 385291 1.61% 95.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 189866 0.79% 96.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 157998 0.66% 97.12% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 143488 0.60% 97.72% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 546700 2.28% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 13664737 76.61% 76.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1906046 10.69% 87.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 699754 3.92% 91.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 424730 2.38% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 316948 1.78% 95.38% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 133544 0.75% 96.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 114109 0.64% 96.77% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 155571 0.87% 97.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 420360 2.36% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 23976589 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 15127070 # Number of instructions committed -system.cpu1.commit.committedOps 15127070 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 17835799 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 11651787 # Number of instructions committed +system.cpu1.commit.committedOps 11651787 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 4418203 # Number of memory references committed -system.cpu1.commit.loads 2674883 # Number of loads committed -system.cpu1.commit.membars 66521 # Number of memory barriers committed -system.cpu1.commit.branches 2263870 # Number of branches committed -system.cpu1.commit.fp_insts 115331 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 13957396 # Number of committed integer instructions. -system.cpu1.commit.function_calls 240978 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 845832 5.59% 5.59% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 9417463 62.26% 67.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 23911 0.16% 68.01% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 68.01% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 11769 0.08% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 68.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.01% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 68.09% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 2741404 18.12% 86.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1743996 11.53% 97.75% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 340936 2.25% 100.00% # Class of committed instruction +system.cpu1.commit.refs 3713677 # Number of memory references committed +system.cpu1.commit.loads 2179871 # Number of loads committed +system.cpu1.commit.membars 62781 # Number of memory barriers committed +system.cpu1.commit.branches 1664922 # Number of branches committed +system.cpu1.commit.fp_insts 144632 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 10748857 # Number of committed integer instructions. +system.cpu1.commit.function_calls 187454 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 614300 5.27% 5.27% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 6897823 59.20% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 19873 0.17% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.64% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 12372 0.11% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.75% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.76% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 2242652 19.25% 84.01% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1534637 13.17% 97.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 328371 2.82% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 15127070 # Class of committed instruction -system.cpu1.commit.bw_lim_events 546700 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 11651787 # Class of committed instruction +system.cpu1.commit.bw_lim_events 420360 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 41251186 # The number of ROB reads -system.cpu1.rob.rob_writes 36287802 # The number of ROB writes -system.cpu1.timesIdled 194891 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1876968 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3779240330 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 14284756 # Number of Instructions Simulated -system.cpu1.committedOps 14284756 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.843615 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.843615 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.542413 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.542413 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20099122 # number of integer regfile reads -system.cpu1.int_regfile_writes 11015819 # number of integer regfile writes -system.cpu1.fp_regfile_reads 63024 # number of floating regfile reads -system.cpu1.fp_regfile_writes 62672 # number of floating regfile writes -system.cpu1.misc_regfile_reads 1065455 # number of misc regfile reads -system.cpu1.misc_regfile_writes 283847 # number of misc regfile writes -system.cpu1.icache.tags.replacements 353746 # number of replacements -system.cpu1.icache.tags.tagsinuse 504.553851 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 2153244 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 354258 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.078180 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 47615844250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 504.553851 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.985457 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.985457 # Average percentage of cache occupancy +system.cpu1.rob.rob_reads 30855147 # The number of ROB reads +system.cpu1.rob.rob_writes 27397116 # The number of ROB writes +system.cpu1.timesIdled 166983 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 900751 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3790431319 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 11041005 # Number of Instructions Simulated +system.cpu1.committedOps 11041005 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.728564 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.728564 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.578515 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.578515 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 15169687 # number of integer regfile reads +system.cpu1.int_regfile_writes 8276758 # number of integer regfile writes +system.cpu1.fp_regfile_reads 77475 # number of floating regfile reads +system.cpu1.fp_regfile_writes 77542 # number of floating regfile writes +system.cpu1.misc_regfile_reads 1124646 # number of misc regfile reads +system.cpu1.misc_regfile_writes 280447 # number of misc regfile writes +system.cpu1.icache.tags.replacements 312757 # number of replacements +system.cpu1.icache.tags.tagsinuse 471.042243 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1644085 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 313269 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 5.248157 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1879134143250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 471.042243 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.920004 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.920004 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 508 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 2876460 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 2876460 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 2153244 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 2153244 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 2153244 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 2153244 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 2153244 # number of overall hits -system.cpu1.icache.overall_hits::total 2153244 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 368891 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 368891 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 368891 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 368891 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 368891 # number of overall misses -system.cpu1.icache.overall_misses::total 368891 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5137931940 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5137931940 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5137931940 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5137931940 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5137931940 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5137931940 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 2522135 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 2522135 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 2522135 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 2522135 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 2522135 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 2522135 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.146261 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.146261 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.146261 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.146261 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.146261 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.146261 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13928.049044 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13928.049044 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13928.049044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13928.049044 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13928.049044 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1327 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 2280436 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 2280436 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1644085 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1644085 # number of ReadReq hits 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overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13529.170952 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 341 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 55 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 24 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 24.127273 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.208333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 14566 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 14566 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 14566 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 14566 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 14566 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 14566 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 354325 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 354325 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 354325 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 354325 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 354325 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 354325 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4259071697 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4259071697 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4259071697 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4259071697 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4259071697 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4259071697 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.140486 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.140486 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.140486 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.140486 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12020.240449 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12020.240449 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12020.240449 # average overall mshr miss latency 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rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.159282 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.159282 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11616.894442 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11616.894442 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11616.894442 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 360788 # number of replacements -system.cpu1.dcache.tags.tagsinuse 496.086183 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3613456 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 361109 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 10.006552 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 40126349500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 496.086183 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.968918 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.968918 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.626953 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18510307 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18510307 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220866 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220866 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1307515 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1307515 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 45364 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 45364 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 48883 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 48883 # number of StoreCondReq hits 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StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 5726098 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 22279433912 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 22279433912 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 22279433912 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 22279433912 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2745761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2745761 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1686404 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1686404 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 54261 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 54261 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 49669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 49669 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 4432165 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 4432165 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 4432165 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 4432165 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.191166 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.191166 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.224673 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.224673 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.163967 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.163967 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.015825 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.015825 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.203915 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.203915 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.203915 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.203915 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15606.214125 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15606.214125 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37181.892715 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37181.892715 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15259.243678 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15259.243678 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7285.111959 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7285.111959 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 24651.281625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24651.281625 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 24651.281625 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 560522 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 381 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 27149 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 19 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 20.646138 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 20.052632 # average number of cycles each access was blocked +system.cpu1.dcache.tags.replacements 140166 # number of replacements +system.cpu1.dcache.tags.tagsinuse 492.227589 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 3241153 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 140473 # Sample count of references to valid blocks. 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LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1705 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 543315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 543315 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 543315 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 543315 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 295391 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 295391 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 65078 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 65078 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7192 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7192 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 786 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 360469 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 360469 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 360469 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 360469 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3818838154 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3818838154 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2138006676 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2138006676 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81043507 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81043507 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4153902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4153902 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5956844830 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5956844830 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5956844830 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5956844830 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 490391500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 490391500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 941927000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 941927000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1432318500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1432318500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.107581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.107581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.038590 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.038590 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.132545 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.132545 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.015825 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.015825 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.081330 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.081330 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.081330 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12928.078899 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12928.078899 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32852.986816 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32852.986816 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11268.563265 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11268.563265 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5284.862595 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5284.862595 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16525.262450 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16525.262450 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 94206 # number of writebacks +system.cpu1.dcache.writebacks::total 94206 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165989 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 165989 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 215339 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 655 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 655 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 381328 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 381328 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 381328 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 381328 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 103394 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 103394 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 50085 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 50085 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 7484 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 7484 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 4996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 4996 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 153479 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 153479 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 153479 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 153479 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1212902508 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1212902508 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1317911046 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1317911046 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 54853004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 54853004 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 26784265 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 26784265 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2530813554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2530813554 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2530813554 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2530813554 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29140000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29140000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 708818500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 708818500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 737958500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 737958500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.046866 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.046866 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.033899 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.139090 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.139090 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100708 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100708 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.041665 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041665 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.041665 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11730.879045 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11730.879045 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26313.487990 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26313.487990 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7329.369856 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7329.369856 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5361.141914 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5361.141914 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16489.640628 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16489.640628 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2082,32 +2105,32 @@ system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 4820 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 161850 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 55184 39.67% 39.67% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 39.77% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1924 1.38% 41.15% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 16 0.01% 41.16% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 81844 58.84% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 139099 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 54289 49.07% 49.07% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.12% 49.19% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1924 1.74% 50.93% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 16 0.01% 50.94% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 54273 49.06% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 110633 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1865924468000 98.05% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 60967000 0.00% 98.05% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 531593000 0.03% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 8367000 0.00% 98.08% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 36597541500 1.92% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1903122936500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.983782 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6701 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 170162 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 59106 40.33% 40.33% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.42% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1925 1.31% 41.73% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 339 0.23% 41.96% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 85060 58.04% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 146561 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 58406 49.14% 49.14% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 131 0.11% 49.25% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1925 1.62% 50.86% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 339 0.29% 51.15% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 58067 48.85% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 118868 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1864755925000 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 61031500 0.00% 97.89% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 543238000 0.03% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 152147500 0.01% 97.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 39554606000 2.08% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1905066948000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.988157 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.663127 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.795354 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.682659 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811048 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 3.56% 3.56% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.44% 12.00% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.78% 13.78% # number of syscalls executed @@ -2139,60 +2162,60 @@ system.cpu0.kern.syscall::144 2 0.89% 99.11% # nu system.cpu0.kern.syscall::147 2 0.89% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 225 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 105 0.07% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.07% # number of callpals executed -system.cpu0.kern.callpal::swpctx 2905 1.98% 2.05% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.09% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.09% # number of callpals executed -system.cpu0.kern.callpal::swpipl 132721 90.43% 92.52% # number of callpals executed -system.cpu0.kern.callpal::rdps 6135 4.18% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.70% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.71% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.71% # number of callpals executed -system.cpu0.kern.callpal::rti 4306 2.93% 99.65% # number of callpals executed -system.cpu0.kern.callpal::callsys 382 0.26% 99.91% # number of callpals executed +system.cpu0.kern.callpal::wripir 439 0.28% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.28% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.29% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3223 2.08% 2.37% # number of callpals executed +system.cpu0.kern.callpal::tbi 50 0.03% 2.40% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 139738 90.30% 92.70% # number of callpals executed +system.cpu0.kern.callpal::rdps 6333 4.09% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.79% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.80% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.80% # number of callpals executed +system.cpu0.kern.callpal::rti 4427 2.86% 99.66% # number of callpals executed +system.cpu0.kern.callpal::callsys 382 0.25% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 146768 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 6331 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1342 # number of protection mode switches +system.cpu0.kern.callpal::total 154756 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6973 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1341 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1341 -system.cpu0.kern.mode_good::user 1342 +system.cpu0.kern.mode_good::kernel 1340 +system.cpu0.kern.mode_good::user 1341 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.211815 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.192170 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.349668 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1901148119000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1974809500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.322468 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1903068198000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1998742000 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 2906 # number of times the context was actually changed +system.cpu0.kern.swap_context 3224 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 3853 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 75635 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26441 39.26% 39.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 2.85% 42.12% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 105 0.16% 42.27% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 38878 57.73% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 67346 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25959 48.22% 48.22% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 3.57% 51.78% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 105 0.20% 51.98% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25854 48.02% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53840 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1868834322000 98.22% 98.22% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 532397000 0.03% 98.24% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 48831000 0.00% 98.25% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 33374320500 1.75% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1902789870500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.981771 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2621 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 71304 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 23839 38.11% 38.11% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1924 3.08% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 439 0.70% 41.89% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 36346 58.11% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 62548 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 23162 48.01% 48.01% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1924 3.99% 51.99% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 439 0.91% 52.90% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 22723 47.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 48248 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872982420000 98.33% 98.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 531501500 0.03% 98.36% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 197949500 0.01% 98.37% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31046317000 1.63% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904758188000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.971601 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.665003 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.799454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::31 0.625186 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771376 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.syscall::3 11 10.89% 10.89% # number of syscalls executed system.cpu1.kern.syscall::6 9 8.91% 19.80% # number of syscalls executed system.cpu1.kern.syscall::15 1 0.99% 20.79% # number of syscalls executed @@ -2208,35 +2231,35 @@ system.cpu1.kern.syscall::74 10 9.90% 97.03% # nu system.cpu1.kern.syscall::132 3 2.97% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 101 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 16 0.02% 0.02% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.03% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1334 1.92% 1.95% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 1.95% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 1.96% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62422 89.83% 91.80% # number of callpals executed -system.cpu1.kern.callpal::rdps 2621 3.77% 95.57% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 95.57% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 95.57% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 95.58% # number of callpals executed -system.cpu1.kern.callpal::rti 2896 4.17% 99.75% # number of callpals executed -system.cpu1.kern.callpal::callsys 133 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::wripir 339 0.52% 0.52% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.53% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.53% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1674 2.58% 3.11% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.11% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.13% # number of callpals executed +system.cpu1.kern.callpal::swpipl 56749 87.55% 90.68% # number of callpals executed +system.cpu1.kern.callpal::rdps 2425 3.74% 94.42% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.42% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.42% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.43% # number of callpals executed +system.cpu1.kern.callpal::rti 3435 5.30% 99.73% # number of callpals executed +system.cpu1.kern.callpal::callsys 133 0.21% 99.93% # number of callpals executed system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 69486 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1712 # number of protection mode switches +system.cpu1.kern.callpal::total 64819 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1725 # number of protection mode switches system.cpu1.kern.mode_switch::user 395 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2056 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 462 +system.cpu1.kern.mode_switch::idle 2719 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 758 system.cpu1.kern.mode_good::user 395 -system.cpu1.kern.mode_good::idle 67 -system.cpu1.kern.mode_switch_good::kernel 0.269860 # fraction of useful protection mode switches +system.cpu1.kern.mode_good::idle 363 +system.cpu1.kern.mode_switch_good::kernel 0.439420 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.032588 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.221955 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 38841912000 2.04% 2.04% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 712477500 0.04% 2.08% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1862932175500 97.92% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1335 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.133505 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.313288 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6292990000 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 709362000 0.04% 0.37% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1897439269000 99.63% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1675 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index 6fda1994e..fe03695e1 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,115 +1,115 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.860009 # Number of seconds simulated -sim_ticks 1860008936000 # Number of ticks simulated -final_tick 1860008936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.859039 # Number of seconds simulated +sim_ticks 1859038679000 # Number of ticks simulated +final_tick 1859038679000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106543 # Simulator instruction rate (inst/s) -host_op_rate 106543 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3740252336 # Simulator tick rate (ticks/s) -host_mem_usage 320492 # Number of bytes of host memory used -host_seconds 497.30 # Real time elapsed on the host -sim_insts 52983264 # Number of instructions simulated -sim_ops 52983264 # Number of ops (including micro ops) simulated +host_inst_rate 164972 # Simulator instruction rate (inst/s) +host_op_rate 164972 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5794497034 # Simulator tick rate (ticks/s) +host_mem_usage 371088 # Number of bytes of host memory used +host_seconds 320.83 # Real time elapsed on the host +sim_insts 52927600 # Number of instructions simulated +sim_ops 52927600 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24900352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24892608 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25869824 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4866048 # Number of bytes written to this memory +system.physmem.bytes_read::total 25861824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968256 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4860032 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7525376 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15133 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 389068 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7519360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388947 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404216 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 76032 # Number of write requests responded to by this memory +system.physmem.num_reads::total 404091 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 75938 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117584 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13387222 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 117490 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520837 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13390043 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13908441 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520703 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2616142 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::tsunami.ide 1429739 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4045882 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2616142 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13387222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1430255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17954322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404216 # Number of read requests accepted -system.physmem.writeReqs 117584 # Number of write requests accepted -system.physmem.readBursts 404216 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 117584 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25858752 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 11072 # Total number of bytes read from write queue -system.physmem.bytesWritten 7523328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25869824 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7525376 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 173 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_read::total 13911396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520837 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2614272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::tsunami.ide 1430486 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4044757 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2614272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520837 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13390043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1431002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17956154 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404091 # Number of read requests accepted +system.physmem.writeReqs 117490 # Number of write requests accepted +system.physmem.readBursts 404091 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 117490 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25850368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11456 # Total number of bytes read from write queue +system.physmem.bytesWritten 7517888 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25861824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7519360 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 179 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 213 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25622 # Per bank write bursts -system.physmem.perBankRdBursts::1 25451 # Per bank write bursts -system.physmem.perBankRdBursts::2 25608 # Per bank write bursts -system.physmem.perBankRdBursts::3 25528 # Per bank write bursts -system.physmem.perBankRdBursts::4 25399 # Per bank write bursts -system.physmem.perBankRdBursts::5 24757 # Per bank write bursts -system.physmem.perBankRdBursts::6 24940 # Per bank write bursts -system.physmem.perBankRdBursts::7 25074 # Per bank write bursts -system.physmem.perBankRdBursts::8 24966 # Per bank write bursts -system.physmem.perBankRdBursts::9 25053 # Per bank write bursts -system.physmem.perBankRdBursts::10 25586 # Per bank write bursts -system.physmem.perBankRdBursts::11 24884 # Per bank write bursts -system.physmem.perBankRdBursts::12 24485 # Per bank write bursts -system.physmem.perBankRdBursts::13 25285 # Per bank write bursts -system.physmem.perBankRdBursts::14 25789 # Per bank write bursts -system.physmem.perBankRdBursts::15 25616 # Per bank write bursts -system.physmem.perBankWrBursts::0 7925 # Per bank write bursts -system.physmem.perBankWrBursts::1 7509 # Per bank write bursts -system.physmem.perBankWrBursts::2 7974 # Per bank write bursts -system.physmem.perBankWrBursts::3 7525 # Per bank write bursts -system.physmem.perBankWrBursts::4 7335 # Per bank write bursts -system.physmem.perBankWrBursts::5 6682 # Per bank write bursts -system.physmem.perBankWrBursts::6 6769 # Per bank write bursts -system.physmem.perBankWrBursts::7 6701 # Per bank write bursts -system.physmem.perBankWrBursts::8 7135 # Per bank write bursts -system.physmem.perBankWrBursts::9 6719 # Per bank write bursts -system.physmem.perBankWrBursts::10 7431 # Per bank write bursts -system.physmem.perBankWrBursts::11 6970 # Per bank write bursts -system.physmem.perBankWrBursts::12 7113 # Per bank write bursts -system.physmem.perBankWrBursts::13 7882 # Per bank write bursts -system.physmem.perBankWrBursts::14 8065 # Per bank write bursts -system.physmem.perBankWrBursts::15 7817 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 193 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25747 # Per bank write bursts +system.physmem.perBankRdBursts::1 25572 # Per bank write bursts +system.physmem.perBankRdBursts::2 25523 # Per bank write bursts +system.physmem.perBankRdBursts::3 25355 # Per bank write bursts +system.physmem.perBankRdBursts::4 25392 # Per bank write bursts +system.physmem.perBankRdBursts::5 24811 # Per bank write bursts +system.physmem.perBankRdBursts::6 25029 # Per bank write bursts +system.physmem.perBankRdBursts::7 25134 # Per bank write bursts +system.physmem.perBankRdBursts::8 24968 # Per bank write bursts +system.physmem.perBankRdBursts::9 25052 # Per bank write bursts +system.physmem.perBankRdBursts::10 25439 # Per bank write bursts +system.physmem.perBankRdBursts::11 24779 # Per bank write bursts +system.physmem.perBankRdBursts::12 24568 # Per bank write bursts +system.physmem.perBankRdBursts::13 25250 # Per bank write bursts +system.physmem.perBankRdBursts::14 25688 # Per bank write bursts +system.physmem.perBankRdBursts::15 25605 # Per bank write bursts +system.physmem.perBankWrBursts::0 8041 # Per bank write bursts +system.physmem.perBankWrBursts::1 7603 # Per bank write bursts +system.physmem.perBankWrBursts::2 7894 # Per bank write bursts +system.physmem.perBankWrBursts::3 7385 # Per bank write bursts +system.physmem.perBankWrBursts::4 7327 # Per bank write bursts +system.physmem.perBankWrBursts::5 6730 # Per bank write bursts +system.physmem.perBankWrBursts::6 6858 # Per bank write bursts +system.physmem.perBankWrBursts::7 6765 # Per bank write bursts +system.physmem.perBankWrBursts::8 7133 # Per bank write bursts +system.physmem.perBankWrBursts::9 6722 # Per bank write bursts +system.physmem.perBankWrBursts::10 7301 # Per bank write bursts +system.physmem.perBankWrBursts::11 6871 # Per bank write bursts +system.physmem.perBankWrBursts::12 7190 # Per bank write bursts +system.physmem.perBankWrBursts::13 7853 # Per bank write bursts +system.physmem.perBankWrBursts::14 7964 # Per bank write bursts +system.physmem.perBankWrBursts::15 7830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 9 # Number of times write queue was full causing retry -system.physmem.totGap 1860003602000 # Total gap between requests +system.physmem.totGap 1859033424000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404216 # Read request sizes (log2) +system.physmem.readPktSize::6 404091 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 117584 # Write request sizes (log2) +system.physmem.writePktSize::6 117490 # Write request sizes (log2) system.physmem.rdQLenPdf::0 315071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 37620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42963 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 59 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -151,201 +151,215 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6916 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7965 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 16 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61090 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 546.434703 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.353089 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.871718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13232 21.66% 21.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10443 17.09% 38.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4742 7.76% 46.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2710 4.44% 50.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2446 4.00% 54.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1597 2.61% 57.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1401 2.29% 59.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1610 2.64% 62.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 22909 37.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61090 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5256 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 76.868151 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2912.510758 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5253 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5440 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6211 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 160 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 544.521149 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 334.160448 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 418.029082 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13483 22.00% 22.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10372 16.93% 38.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4758 7.76% 46.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2785 4.54% 51.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2293 3.74% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1673 2.73% 57.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1477 2.41% 60.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1592 2.60% 62.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 22847 37.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5232 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 77.198394 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2919.153555 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5229 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5256 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5256 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.365297 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.103318 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 20.103778 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4494 85.50% 85.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 124 2.36% 87.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 9 0.17% 88.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 232 4.41% 92.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 40 0.76% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 6 0.11% 93.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 12 0.23% 93.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.06% 93.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 27 0.51% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.06% 94.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.02% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.02% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 15 0.29% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.10% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.06% 94.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 31 0.59% 95.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.15% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.08% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 5 0.10% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 188 3.58% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.04% 99.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.10% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.06% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 11 0.21% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.06% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.13% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.10% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.04% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5256 # Writes before turning the bus around for reads -system.physmem.totQLat 3626109250 # Total ticks spent queuing -system.physmem.totMemAccLat 11201915500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2020215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8974.56 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5232 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5232 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.451644 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.067800 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.155033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 4469 85.42% 85.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 138 2.64% 88.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 12 0.23% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 232 4.43% 92.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 44 0.84% 93.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.04% 93.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 5 0.10% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.19% 93.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.32% 94.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.04% 94.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 94.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.04% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 7 0.13% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.06% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.08% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.02% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 28 0.54% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 15 0.29% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 15 0.29% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 171 3.27% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 6 0.11% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.02% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.04% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.04% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.10% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.02% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 6 0.11% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.08% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 11 0.21% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 2 0.04% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 7 0.13% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5232 # Writes before turning the bus around for reads +system.physmem.totQLat 3681492750 # Total ticks spent queuing +system.physmem.totMemAccLat 11254842750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2019560000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9114.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27724.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27864.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.91 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 4.04 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 13.91 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.05 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.10 # Average write queue length when enqueuing -system.physmem.readRowHits 364992 # Number of row buffer hits during reads -system.physmem.writeRowHits 95512 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.33 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.23 # Row buffer hit rate for writes -system.physmem.avgGap 3564591.03 # Average gap between requests -system.physmem.pageHitRate 88.28 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1761923491250 # Time in different power states -system.physmem.memoryStateTime::REF 62109580000 # Time in different power states +system.physmem.avgRdQLen 1.92 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.45 # Average write queue length when enqueuing +system.physmem.readRowHits 364830 # Number of row buffer hits during reads +system.physmem.writeRowHits 95269 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.09 # Row buffer hit rate for writes +system.physmem.avgGap 3564227.65 # Average gap between requests +system.physmem.pageHitRate 88.24 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1761056207000 # Time in different power states +system.physmem.memoryStateTime::REF 62077340000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 35970256750 # Time in different power states +system.physmem.memoryStateTime::ACT 35903990500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 17983494 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 296097 # Transaction distribution -system.membus.trans_dist::ReadResp 296008 # Transaction distribution -system.membus.trans_dist::WriteReq 9598 # Transaction distribution -system.membus.trans_dist::WriteResp 9598 # Transaction distribution -system.membus.trans_dist::Writeback 76032 # Transaction distribution +system.membus.trans_dist::ReadReq 296046 # Transaction distribution +system.membus.trans_dist::ReadResp 295957 # Transaction distribution +system.membus.trans_dist::WriteReq 9597 # Transaction distribution +system.membus.trans_dist::WriteResp 9597 # Transaction distribution +system.membus.trans_dist::Writeback 75938 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 207 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 213 # Transaction distribution -system.membus.trans_dist::ReadExReq 115296 # Transaction distribution -system.membus.trans_dist::ReadExResp 115296 # Transaction distribution +system.membus.trans_dist::UpgradeReq 188 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 193 # Transaction distribution +system.membus.trans_dist::ReadExReq 115222 # Transaction distribution +system.membus.trans_dist::ReadExResp 115222 # Transaction distribution system.membus.trans_dist::BadAddressError 89 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33056 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884476 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 178 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 918094 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917708 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83292 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 83292 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1001386 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44148 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30734912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 30779060 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 33439348 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33439348 # Total data (bytes) -system.membus.snoop_data_through_bus 10112 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 29284000 # Layer occupancy (ticks) +system.membus.pkt_count::total 1001000 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30720896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30765036 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2660288 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33425324 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 158 # Total snoops (count) +system.membus.snoop_fanout::samples 522030 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 522030 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 522030 # Request fanout histogram +system.membus.reqLayer0.occupancy 31457000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1484965250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1484421249 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 112000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 110500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3755505039 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3754388311 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.respLayer2.occupancy 43151211 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.268186 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.260487 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709354954000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.268186 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.079262 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.079262 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1709355301000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.260487 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078780 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078780 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 376037 # Number of tag accesses -system.iocache.tags.data_accesses 376037 # Number of data accesses +system.iocache.tags.tag_accesses 376213 # Number of tag accesses +system.iocache.tags.data_accesses 376213 # Number of data accesses system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::tsunami.ide 64 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 64 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::tsunami.ide 86 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 86 # number of WriteInvalidateReq misses system.iocache.demand_misses::tsunami.ide 173 # number of demand (read+write) misses system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses @@ -358,16 +372,16 @@ system.iocache.overall_miss_latency::tsunami.ide 21133383 system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41616 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 41616 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41638 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 41638 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::tsunami.ide 173 # number of demand (read+write) accesses system.iocache.demand_accesses::total 173 # number of demand (read+write) accesses system.iocache.overall_accesses::tsunami.ide 173 # number of overall (read+write) accesses system.iocache.overall_accesses::total 173 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.001538 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.001538 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 0.002065 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.002065 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses @@ -396,24 +410,24 @@ system.iocache.overall_mshr_misses::tsunami.ide 173 system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2528134047 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2528134047 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2529714027 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2529714027 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.998462 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.998462 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.997935 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.997935 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60842.656118 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60842.656118 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60880.680280 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60880.680280 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency @@ -431,36 +445,36 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.branchPred.lookups 17833670 # Number of BP lookups -system.cpu.branchPred.condPredicted 15506350 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 381114 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 12104225 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5926115 # Number of BTB hits +system.cpu.branchPred.lookups 17804968 # Number of BP lookups +system.cpu.branchPred.condPredicted 15499600 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 379466 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11923628 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5932721 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 48.959062 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 921355 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21398 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 49.756005 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 914118 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21281 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10317598 # DTB read hits -system.cpu.dtb.read_misses 42841 # DTB read misses -system.cpu.dtb.read_acv 498 # DTB read access violations -system.cpu.dtb.read_accesses 968680 # DTB read accesses -system.cpu.dtb.write_hits 6661505 # DTB write hits -system.cpu.dtb.write_misses 9470 # DTB write misses -system.cpu.dtb.write_acv 409 # DTB write access violations -system.cpu.dtb.write_accesses 342844 # DTB write accesses -system.cpu.dtb.data_hits 16979103 # DTB hits -system.cpu.dtb.data_misses 52311 # DTB misses -system.cpu.dtb.data_acv 907 # DTB access violations -system.cpu.dtb.data_accesses 1311524 # DTB accesses -system.cpu.itb.fetch_hits 1772041 # ITB hits -system.cpu.itb.fetch_misses 34420 # ITB misses -system.cpu.itb.fetch_acv 658 # ITB acv -system.cpu.itb.fetch_accesses 1806461 # ITB accesses +system.cpu.dtb.read_hits 10302215 # DTB read hits +system.cpu.dtb.read_misses 41309 # DTB read misses +system.cpu.dtb.read_acv 513 # DTB read access violations +system.cpu.dtb.read_accesses 965594 # DTB read accesses +system.cpu.dtb.write_hits 6646492 # DTB write hits +system.cpu.dtb.write_misses 9371 # DTB write misses +system.cpu.dtb.write_acv 419 # DTB write access violations +system.cpu.dtb.write_accesses 342338 # DTB write accesses +system.cpu.dtb.data_hits 16948707 # DTB hits +system.cpu.dtb.data_misses 50680 # DTB misses +system.cpu.dtb.data_acv 932 # DTB access violations +system.cpu.dtb.data_accesses 1307932 # DTB accesses +system.cpu.itb.fetch_hits 1774610 # ITB hits +system.cpu.itb.fetch_misses 34401 # ITB misses +system.cpu.itb.fetch_acv 653 # ITB acv +system.cpu.itb.fetch_accesses 1809011 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -473,259 +487,259 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118354133 # number of cpu cycles simulated +system.cpu.numCycles 118301061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29610053 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78304025 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17833670 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6847470 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80574615 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1256858 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1099 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 26263 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1650622 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 440507 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 235 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9057340 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272482 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112931823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.693374 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.013486 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29562966 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78094807 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17804968 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6846839 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 80553195 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1252096 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1416 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 27926 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1649882 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 450417 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9025532 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 274121 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 3 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 112872082 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.691888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.011514 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98319716 87.06% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 938849 0.83% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1975725 1.75% 89.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 910849 0.81% 90.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2798510 2.48% 92.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 647409 0.57% 93.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 732146 0.65% 94.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1011734 0.90% 95.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5596885 4.96% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 98296528 87.09% 87.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 933530 0.83% 87.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1975700 1.75% 89.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 908755 0.81% 90.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2800334 2.48% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 638924 0.57% 93.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 725896 0.64% 94.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007040 0.89% 95.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5585375 4.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112931823 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150681 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.661608 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24101711 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76820135 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9519710 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1904377 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 585889 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 591731 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42945 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68430953 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 130896 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 585889 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25024532 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47243324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20763433 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10413926 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8900717 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65988448 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 204336 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2037147 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 141186 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4759131 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 44017538 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79991288 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79809724 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169111 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38182266 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5835264 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1692739 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 242112 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13540611 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10451547 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6960595 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1482211 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1061862 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58727790 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2141622 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57666213 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7541795 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3548748 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1480432 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112931823 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.510629 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.253101 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 112872082 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.150506 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.660136 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24068860 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 76820836 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9500551 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1898196 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 583638 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 588301 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42850 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68299285 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 133126 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 583638 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24994916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 47249741 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20742683 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10385328 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8915774 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65865702 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 202022 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2036806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 141544 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4770005 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43944287 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79812474 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79631676 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168345 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38137411 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5806868 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690855 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 241233 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13548292 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10425085 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6927485 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1490397 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1054253 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58626057 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2139161 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57592696 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51229 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7502337 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3486338 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1478017 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 112872082 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.510247 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.252928 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89418441 79.18% 79.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10028401 8.88% 88.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4312192 3.82% 91.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2973812 2.63% 94.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3078524 2.73% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1589541 1.41% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1010242 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396621 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124049 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 89394835 79.20% 79.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10016384 8.87% 88.07% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4304507 3.81% 91.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 2950730 2.61% 94.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082787 2.73% 97.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1592384 1.41% 98.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1013037 0.90% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 395526 0.35% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 121892 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112931823 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 112872082 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 207021 18.24% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 552834 48.70% 66.94% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 375297 33.06% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 212963 18.82% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.82% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 545078 48.16% 66.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 373836 33.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39135351 67.87% 67.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61883 0.11% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.99% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38374 0.07% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10730394 18.61% 86.67% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6740242 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949047 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39097776 67.89% 67.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61804 0.11% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38376 0.07% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.08% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10712581 18.60% 86.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6722276 11.67% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948961 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57666213 # Type of FU issued -system.cpu.iq.rate 0.487234 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1135152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019685 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228740415 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 68094123 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55977641 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 715091 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336647 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329707 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58410087 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383992 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 639401 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57592696 # Type of FU issued +system.cpu.iq.rate 0.486832 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1131877 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019653 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 228528169 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67952558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55916727 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 712410 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 328997 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58334880 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 382407 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 639606 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1358213 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3975 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20004 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 581979 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1340629 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4088 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20047 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 553798 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18257 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 542602 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18287 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 539247 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 585889 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44309531 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 608680 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64580146 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145680 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10451547 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6960595 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1891521 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42330 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 362520 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20004 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 191994 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 411566 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 603560 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 57078103 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10388088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 588109 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 583638 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 44307486 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 616008 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64468948 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 145079 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10425085 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6927485 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1890835 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 42893 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 369751 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20047 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 190429 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410127 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 600556 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 57009373 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10371242 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 583322 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3710734 # number of nop insts executed -system.cpu.iew.exec_refs 17074164 # number of memory reference insts executed -system.cpu.iew.exec_branches 8987700 # Number of branches executed -system.cpu.iew.exec_stores 6686076 # Number of stores executed -system.cpu.iew.exec_rate 0.482265 # Inst execution rate -system.cpu.iew.wb_sent 56446206 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56307348 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28961590 # num instructions producing a value -system.cpu.iew.wb_consumers 40346871 # num instructions consuming a value +system.cpu.iew.exec_nop 3703730 # number of nop insts executed +system.cpu.iew.exec_refs 17042240 # number of memory reference insts executed +system.cpu.iew.exec_branches 8981920 # Number of branches executed +system.cpu.iew.exec_stores 6670998 # Number of stores executed +system.cpu.iew.exec_rate 0.481901 # Inst execution rate +system.cpu.iew.wb_sent 56380366 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56245724 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28936691 # num instructions producing a value +system.cpu.iew.wb_consumers 40310167 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475753 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717815 # average fanout of values written-back +system.cpu.iew.wb_rate 0.475446 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.717851 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8290413 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661190 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549582 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111493844 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503831 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.456125 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8239182 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661144 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 548042 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 111437316 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.503568 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.455315 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91848046 82.38% 82.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7822356 7.02% 89.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4123652 3.70% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2157766 1.94% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1851713 1.66% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 614180 0.55% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 473259 0.42% 97.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 509141 0.46% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2093731 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 91810154 82.39% 82.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7802563 7.00% 89.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4132031 3.71% 93.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2155493 1.93% 95.03% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1853584 1.66% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 616181 0.55% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 467348 0.42% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 515869 0.46% 98.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2084093 1.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111493844 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56174099 # Number of instructions committed -system.cpu.commit.committedOps 56174099 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 111437316 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56116260 # Number of instructions committed +system.cpu.commit.committedOps 56116260 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15471950 # Number of memory references committed -system.cpu.commit.loads 9093334 # Number of loads committed -system.cpu.commit.membars 226345 # Number of memory barriers committed -system.cpu.commit.branches 8441019 # Number of branches committed -system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 52023449 # Number of committed integer instructions. -system.cpu.commit.function_calls 740634 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3198108 5.69% 5.69% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36220301 64.48% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60671 0.11% 70.28% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.28% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.35% # Class of committed instruction +system.cpu.commit.refs 15458143 # Number of memory references committed +system.cpu.commit.loads 9084456 # Number of loads committed +system.cpu.commit.membars 226334 # Number of memory barriers committed +system.cpu.commit.branches 8434463 # Number of branches committed +system.cpu.commit.fp_insts 324518 # Number of committed floating point instructions. +system.cpu.commit.int_insts 51967854 # Number of committed integer instructions. +system.cpu.commit.function_calls 739911 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3195933 5.70% 5.70% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36178550 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60663 0.11% 70.27% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 38089 0.07% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 70.34% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 3636 0.01% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 70.35% # Class of committed instruction @@ -748,30 +762,30 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9319679 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6384570 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949047 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9310790 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6379639 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948960 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56174099 # Class of committed instruction -system.cpu.commit.bw_lim_events 2093731 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56116260 # Class of committed instruction +system.cpu.commit.bw_lim_events 2084093 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173614429 # The number of ROB reads -system.cpu.rob.rob_writes 130369620 # The number of ROB writes -system.cpu.timesIdled 576556 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5422310 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3601657297 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52983264 # Number of Instructions Simulated -system.cpu.committedOps 52983264 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.233802 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.233802 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447667 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447667 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74755796 # number of integer regfile reads -system.cpu.int_regfile_writes 40630218 # number of integer regfile writes -system.cpu.fp_regfile_reads 167440 # number of floating regfile reads -system.cpu.fp_regfile_writes 167913 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030226 # number of misc regfile reads -system.cpu.misc_regfile_writes 939431 # number of misc regfile writes +system.cpu.rob.rob_reads 173459156 # The number of ROB reads +system.cpu.rob.rob_writes 130141826 # The number of ROB writes +system.cpu.timesIdled 576115 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5428979 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599776298 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52927600 # Number of Instructions Simulated +system.cpu.committedOps 52927600 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.235149 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.235149 # CPI: Total CPI of All Threads +system.cpu.ipc 0.447398 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.447398 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74648651 # number of integer regfile reads +system.cpu.int_regfile_writes 40584029 # number of integer regfile writes +system.cpu.fp_regfile_reads 166982 # number of floating regfile reads +system.cpu.fp_regfile_writes 167600 # number of floating regfile writes +system.cpu.misc_regfile_reads 2029015 # number of misc regfile reads +system.cpu.misc_regfile_writes 939371 # number of misc regfile writes system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -803,13 +817,12 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.iobus.throughput 1454701 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 7103 # Transaction distribution system.iobus.trans_dist::ReadResp 7103 # Transaction distribution -system.iobus.trans_dist::WriteReq 51086 # Transaction distribution -system.iobus.trans_dist::WriteResp 51150 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 64 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5052 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 51063 # Transaction distribution +system.iobus.trans_dist::WriteResp 51149 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 86 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5050 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -821,28 +834,27 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33054 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 116506 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 20208 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 44148 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2705756 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2705756 # Total data (bytes) -system.iobus.reqLayer0.occupancy 4663000 # Layer occupancy (ticks) +system.iobus.pkt_count::total 116504 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20200 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 44140 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2705748 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 4661000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -864,250 +876,259 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 374510641 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 374547621 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 23458000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer1.occupancy 42014789 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.throughput 114654995 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2149538 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2149432 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 9598 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 845214 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2147499 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2147393 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 842679 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41561 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 94 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 122 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 302210 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 302210 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 81 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 26 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 107 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301934 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301934 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 89 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074480 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3693292 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5767772 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66377344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 144210036 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 210587380 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 210577396 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 2681920 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 2503268997 # Layer occupancy (ticks) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2074254 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3686339 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5760593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66370688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143907436 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 210278124 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42060 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3326850 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012545 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111298 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3285116 98.75% 98.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41734 1.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3326850 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2498300996 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1560084006 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1559854344 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2193039668 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2189806641 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.icache.tags.replacements 1036559 # number of replacements -system.cpu.icache.tags.tagsinuse 509.401978 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7968978 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1037067 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.684150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26427286250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.401978 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 1036451 # number of replacements +system.cpu.icache.tags.tagsinuse 509.402237 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7937240 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1036959 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.654343 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 26422155250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.402237 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.994926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.994926 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 136 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10094673 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10094673 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7968979 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7968979 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7968979 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7968979 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7968979 # number of overall hits -system.cpu.icache.overall_hits::total 7968979 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1088360 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1088360 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1088360 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1088360 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1088360 # number of overall misses -system.cpu.icache.overall_misses::total 1088360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15140469933 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15140469933 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15140469933 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15140469933 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15140469933 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15140469933 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9057339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9057339 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9057339 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9057339 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9057339 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9057339 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120163 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120163 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120163 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120163 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120163 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120163 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13911.270106 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13911.270106 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13911.270106 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13911.270106 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13911.270106 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4471 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10062742 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10062742 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7937241 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7937241 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7937241 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7937241 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7937241 # number of overall hits +system.cpu.icache.overall_hits::total 7937241 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1088289 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1088289 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1088289 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1088289 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1088289 # number of overall misses +system.cpu.icache.overall_misses::total 1088289 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15130440508 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15130440508 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15130440508 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15130440508 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15130440508 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15130440508 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9025530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9025530 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9025530 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9025530 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9025530 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9025530 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120579 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.120579 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.120579 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.120579 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.120579 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.120579 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13902.961904 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13902.961904 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13902.961904 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13902.961904 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13902.961904 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 4627 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 200 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 203 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.355000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.793103 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51026 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51026 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51026 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51026 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51026 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51026 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037334 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1037334 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1037334 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1037334 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1037334 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1037334 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12446794989 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12446794989 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12446794989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12446794989 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12446794989 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12446794989 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114530 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114530 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114530 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.830646 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.830646 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.830646 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.830646 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51077 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51077 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51077 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51077 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51077 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51077 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1037212 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1037212 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1037212 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1037212 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1037212 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1037212 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12445124401 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12445124401 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12445124401 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12445124401 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12445124401 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12445124401 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114920 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114920 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114920 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114920 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11998.631332 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11998.631332 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11998.631332 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11998.631332 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 338424 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65337.415563 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2581710 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403590 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.396863 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5538438750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53805.196085 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5357.724352 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6174.495125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.821002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081752 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.094215 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996970 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3497 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55433 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994354 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 27024459 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 27024459 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1022012 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 831240 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1853252 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 845214 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 845214 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186775 # 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+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 364867750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 364867750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 402005 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 402005 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 117662073503 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 117662073503 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 117662073503 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 117662073503 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9063858 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9063858 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6143245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6143245 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209580 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209580 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215741 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215741 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15207103 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15207103 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15207103 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15207103 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.196037 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.196037 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318310 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318310 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111094 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111094 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000121 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.245432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.245432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.245432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.245432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22232.053199 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 22232.053199 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39969.742100 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39969.742100 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15670.993858 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15670.993858 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15461.730769 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15461.730769 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31525.310365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31525.310365 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31525.310365 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 3999248 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1376 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 180044 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 22 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.212615 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 62.545455 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 845214 # number of writebacks -system.cpu.dcache.writebacks::total 845214 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 683673 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 683673 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664672 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664672 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5215 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5215 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2348345 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2348345 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2348345 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2348345 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1097777 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1097777 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291406 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291406 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18220 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18220 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1389183 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1389183 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1389183 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1389183 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27531600277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27531600277 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11750999106 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11750999106 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 207629251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 207629251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 383994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 383994 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39282599383 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39282599383 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39282599383 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39282599383 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423287000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1997974498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1997974498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3421261498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3421261498 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120953 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120953 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047397 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047397 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086828 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086828 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091248 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25079.410734 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25079.410734 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40325.178981 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40325.178981 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11395.677881 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.677881 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13714.071429 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13714.071429 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28277.483516 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28277.483516 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 842679 # number of writebacks +system.cpu.dcache.writebacks::total 842679 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 680758 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 680758 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664340 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664340 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5292 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5292 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2345098 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2345098 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2345098 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2345098 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1096091 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1096091 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291116 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 291116 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17991 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17991 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 26 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 26 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1387207 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1387207 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1387207 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1387207 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27515724784 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27515724784 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11792803134 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11792803134 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204517750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204517750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 349995 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 349995 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39308527918 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 39308527918 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39308527918 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 39308527918 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423597000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423597000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999614498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999614498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423211498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423211498 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047388 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085843 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085843 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000121 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091221 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091221 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091221 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25103.503983 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25103.503983 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40508.948783 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40508.948783 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11367.781113 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11367.781113 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13461.346154 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13461.346154 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28336.454414 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28336.454414 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1367,28 +1388,28 @@ system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6443 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211008 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74663 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6442 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210986 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74656 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1880 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105564 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182238 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73296 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105550 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182216 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73289 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1880 1.27% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73296 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148603 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1818262027500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61927000 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 526143500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41157993000 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1860008091000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73289 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148588 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817327743500 97.76% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 61881000 0.00% 97.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 521765000 0.03% 97.79% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 41126450000 2.21% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1859037839500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694328 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815434 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694353 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815450 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1424,32 +1445,32 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed +system.cpu.kern.callpal::swpctx 4178 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175121 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6784 3.53% 96.97% # number of callpals executed +system.cpu.kern.callpal::swpipl 175101 91.22% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.98% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.98% # number of callpals executed -system.cpu.kern.callpal::rti 5105 2.66% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191967 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches +system.cpu.kern.callpal::total 191946 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches system.cpu.kern.mode_good::kernel 1910 system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326496 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326440 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.394302 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29080060000 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2655672500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1828272350500 98.29% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.kern.mode_ticks::kernel 29097785000 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2655967500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1827284079000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4179 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index 6a79f5850..85c742feb 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,134 +1,134 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.841612 # Number of seconds simulated -sim_ticks 1841612285000 # Number of ticks simulated -final_tick 1841612285000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1841612450000 # Number of ticks simulated +final_tick 1841612450000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 168459 # Simulator instruction rate (inst/s) -host_op_rate 168459 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4750760669 # Simulator tick rate (ticks/s) -host_mem_usage 319468 # Number of bytes of host memory used -host_seconds 387.65 # Real time elapsed on the host -sim_insts 65302548 # Number of instructions simulated -sim_ops 65302548 # Number of ops (including micro ops) simulated +host_inst_rate 222430 # Simulator instruction rate (inst/s) +host_op_rate 222430 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6273480939 # Simulator tick rate (ticks/s) +host_mem_usage 370816 # Number of bytes of host memory used +host_seconds 293.56 # Real time elapsed on the host +sim_insts 65295558 # Number of instructions simulated +sim_ops 65295558 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 475840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 19999104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 476096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20002240 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2248128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 298624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2645376 # Number of bytes read from this memory -system.physmem.bytes_read::total 25815040 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 475840 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 2248832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 298304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2641344 # Number of bytes read from this memory +system.physmem.bytes_read::total 25814784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 476096 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 298624 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4825408 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 298304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 921408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4825792 # Number of bytes written to this memory system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory -system.physmem.bytes_written::total 7484736 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7435 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 312486 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7485120 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7439 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 312535 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4666 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 41334 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403360 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 75397 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 35138 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4661 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41271 # Number of read requests responded to by this memory +system.physmem.num_reads::total 403356 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 75403 # Number of write requests responded to by this memory system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116949 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 258382 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10859563 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 116955 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 258521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10861265 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 79826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1220739 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 162154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1436446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14017630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 258382 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1221121 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 161980 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1434256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14017490 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 258521 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 79826 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 162154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 500362 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2620208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 161980 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 500327 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2620417 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::tsunami.ide 1444022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4064230 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2620208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258382 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10859563 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 4064438 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2620417 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10861265 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1444543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 79826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1220739 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 162154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1436446 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18081860 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83439 # Number of read requests accepted -system.physmem.writeReqs 46740 # Number of write requests accepted -system.physmem.readBursts 83439 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 46740 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5337024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3072 # Total number of bytes read from write queue -system.physmem.bytesWritten 2989888 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5340096 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2991360 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 48 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.data 1221121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 161980 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1434256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18081928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 83382 # Number of read requests accepted +system.physmem.writeReqs 46694 # Number of write requests accepted +system.physmem.readBursts 83382 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 46694 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5333696 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2752 # Total number of bytes read from write queue +system.physmem.bytesWritten 2986816 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5336448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2988416 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 43 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 52 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5256 # Per bank write bursts -system.physmem.perBankRdBursts::1 5087 # Per bank write bursts -system.physmem.perBankRdBursts::2 5115 # Per bank write bursts -system.physmem.perBankRdBursts::3 5179 # Per bank write bursts -system.physmem.perBankRdBursts::4 5173 # Per bank write bursts -system.physmem.perBankRdBursts::5 5205 # Per bank write bursts -system.physmem.perBankRdBursts::6 5267 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 55 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5371 # Per bank write bursts +system.physmem.perBankRdBursts::1 5100 # Per bank write bursts +system.physmem.perBankRdBursts::2 5085 # Per bank write bursts +system.physmem.perBankRdBursts::3 5221 # Per bank write bursts +system.physmem.perBankRdBursts::4 5159 # Per bank write bursts +system.physmem.perBankRdBursts::5 5196 # Per bank write bursts +system.physmem.perBankRdBursts::6 5274 # Per bank write bursts system.physmem.perBankRdBursts::7 5273 # Per bank write bursts -system.physmem.perBankRdBursts::8 5423 # Per bank write bursts +system.physmem.perBankRdBursts::8 5416 # Per bank write bursts system.physmem.perBankRdBursts::9 5013 # Per bank write bursts -system.physmem.perBankRdBursts::10 5464 # Per bank write bursts -system.physmem.perBankRdBursts::11 5273 # Per bank write bursts -system.physmem.perBankRdBursts::12 4813 # Per bank write bursts -system.physmem.perBankRdBursts::13 5124 # Per bank write bursts -system.physmem.perBankRdBursts::14 5602 # Per bank write bursts -system.physmem.perBankRdBursts::15 5124 # Per bank write bursts -system.physmem.perBankWrBursts::0 2825 # Per bank write bursts -system.physmem.perBankWrBursts::1 2787 # Per bank write bursts -system.physmem.perBankWrBursts::2 2858 # Per bank write bursts -system.physmem.perBankWrBursts::3 3069 # Per bank write bursts -system.physmem.perBankWrBursts::4 3024 # Per bank write bursts -system.physmem.perBankWrBursts::5 2822 # Per bank write bursts -system.physmem.perBankWrBursts::6 3224 # Per bank write bursts -system.physmem.perBankWrBursts::7 2821 # Per bank write bursts -system.physmem.perBankWrBursts::8 3331 # Per bank write bursts -system.physmem.perBankWrBursts::9 2683 # Per bank write bursts -system.physmem.perBankWrBursts::10 3131 # Per bank write bursts -system.physmem.perBankWrBursts::11 2953 # Per bank write bursts -system.physmem.perBankWrBursts::12 2475 # Per bank write bursts -system.physmem.perBankWrBursts::13 2748 # Per bank write bursts -system.physmem.perBankWrBursts::14 3227 # Per bank write bursts -system.physmem.perBankWrBursts::15 2739 # Per bank write bursts +system.physmem.perBankRdBursts::10 5453 # Per bank write bursts +system.physmem.perBankRdBursts::11 5267 # Per bank write bursts +system.physmem.perBankRdBursts::12 4696 # Per bank write bursts +system.physmem.perBankRdBursts::13 5103 # Per bank write bursts +system.physmem.perBankRdBursts::14 5623 # Per bank write bursts +system.physmem.perBankRdBursts::15 5089 # Per bank write bursts +system.physmem.perBankWrBursts::0 2944 # Per bank write bursts +system.physmem.perBankWrBursts::1 2803 # Per bank write bursts +system.physmem.perBankWrBursts::2 2831 # Per bank write bursts +system.physmem.perBankWrBursts::3 3111 # Per bank write bursts +system.physmem.perBankWrBursts::4 3010 # Per bank write bursts +system.physmem.perBankWrBursts::5 2812 # Per bank write bursts +system.physmem.perBankWrBursts::6 3230 # Per bank write bursts +system.physmem.perBankWrBursts::7 2824 # Per bank write bursts +system.physmem.perBankWrBursts::8 3325 # Per bank write bursts +system.physmem.perBankWrBursts::9 2680 # Per bank write bursts +system.physmem.perBankWrBursts::10 3123 # Per bank write bursts +system.physmem.perBankWrBursts::11 2945 # Per bank write bursts +system.physmem.perBankWrBursts::12 2356 # Per bank write bursts +system.physmem.perBankWrBursts::13 2727 # Per bank write bursts +system.physmem.perBankWrBursts::14 3249 # Per bank write bursts +system.physmem.perBankWrBursts::15 2699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1840600008500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 1840600173500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83439 # Read request sizes (log2) +system.physmem.readPktSize::6 83382 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 46740 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 66354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7773 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1810 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see +system.physmem.writePktSize::6 46694 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 66361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 7479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -156,137 +156,124 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 79 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 56 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 44 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1853 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 3486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 3386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1019 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 21530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 386.758569 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 220.447203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 381.120515 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7019 32.60% 32.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4847 22.51% 55.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1849 8.59% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1051 4.88% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 911 4.23% 72.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 506 2.35% 75.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 375 1.74% 76.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 418 1.94% 78.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4554 21.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 21530 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2040 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 40.873529 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1027.655163 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2038 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 21619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 384.870346 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 218.868855 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 380.663334 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7130 32.98% 32.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4830 22.34% 55.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1852 8.57% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1050 4.86% 68.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 916 4.24% 72.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 498 2.30% 75.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 396 1.83% 77.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 403 1.86% 78.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4544 21.02% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 21619 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2039 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 40.867092 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1027.907354 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 2037 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2040 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2040 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 22.900490 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.614282 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.575456 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 33 1.62% 1.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.34% 1.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 2.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 5 0.25% 2.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1695 83.09% 85.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 37 1.81% 87.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 5 0.25% 87.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 107 5.25% 92.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7 0.34% 92.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.10% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.05% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 3 0.15% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 8 0.39% 93.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 1 0.05% 93.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.05% 93.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 2 0.10% 93.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.05% 93.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.10% 94.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.10% 94.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.39% 94.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.15% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.15% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.10% 94.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 78 3.82% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.05% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.10% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.05% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 7 0.34% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.10% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 3 0.15% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.05% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.15% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.05% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.20% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2040 # Writes before turning the bus around for reads -system.physmem.totQLat 869064750 # Total ticks spent queuing -system.physmem.totMemAccLat 2432646000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 416955000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10421.57 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2039 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2039 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.888180 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.579378 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.470267 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-7 42 2.06% 2.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-15 4 0.20% 2.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-23 1722 84.45% 86.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-31 114 5.59% 92.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-39 19 0.93% 93.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-47 3 0.15% 93.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-55 5 0.25% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-63 2 0.10% 93.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-71 2 0.10% 93.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-79 3 0.15% 93.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-87 15 0.74% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-95 5 0.25% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-103 79 3.87% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-119 5 0.25% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-127 1 0.05% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-135 5 0.25% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-143 5 0.25% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-151 3 0.15% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-159 1 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-183 1 0.05% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-231 2 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-263 1 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2039 # Writes before turning the bus around for reads +system.physmem.totQLat 882163500 # Total ticks spent queuing +system.physmem.totMemAccLat 2444769750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 416695000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10585.24 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29171.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29335.24 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.62 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s @@ -296,258 +283,267 @@ system.physmem.busUtil 0.04 # Da system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 71609 # Number of row buffer hits during reads -system.physmem.writeRowHits 36969 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.09 # Row buffer hit rate for writes -system.physmem.avgGap 14138993.30 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 1766589196000 # Time in different power states +system.physmem.avgWrQLen 8.38 # Average write queue length when enqueuing +system.physmem.readRowHits 71513 # Number of row buffer hits during reads +system.physmem.writeRowHits 36876 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.81 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.97 # Row buffer hit rate for writes +system.physmem.avgGap 14150190.45 # Average gap between requests +system.physmem.pageHitRate 83.35 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 1766563042250 # Time in different power states system.physmem.memoryStateTime::REF 61495460000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 13527240250 # Time in different power states +system.physmem.memoryStateTime::ACT 13553394000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 18112095 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 44765 # Transaction distribution -system.membus.trans_dist::ReadResp 44760 # Transaction distribution -system.membus.trans_dist::WriteReq 3528 # Transaction distribution -system.membus.trans_dist::WriteResp 3528 # Transaction distribution -system.membus.trans_dist::Writeback 29460 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 17280 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 17280 # Transaction distribution -system.membus.trans_dist::UpgradeReq 50 # Transaction distribution +system.membus.trans_dist::ReadReq 294949 # Transaction distribution +system.membus.trans_dist::ReadResp 294942 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::Writeback 75403 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution +system.membus.trans_dist::UpgradeReq 148 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 52 # Transaction distribution -system.membus.trans_dist::ReadExReq 41656 # Transaction distribution -system.membus.trans_dist::ReadExResp 41656 # Transaction distribution -system.membus.trans_dist::BadAddressError 5 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 12900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 196412 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 209322 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 34645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 34645 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 243967 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 15792 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 7224576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 7240368 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1106880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 1106880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 8347248 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 33351936 # Total data (bytes) -system.membus.snoop_data_through_bus 3520 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 11434500 # Layer occupancy (ticks) +system.membus.trans_dist::UpgradeResp 150 # Transaction distribution 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999702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30639616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30685184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2666880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2666880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33352064 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 55 # Total snoops (count) +system.membus.snoop_fanout::samples 520629 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request 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miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71577.157811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 64740.895465 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62242.054854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55259.687891 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63284.488307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 64163.570439 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60309.584911 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -666,14 +662,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.254802 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254811 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693889914000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.254802 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078425 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078425 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693889963000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254811 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078426 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078426 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -731,8 +727,8 @@ system.iocache.overall_mshr_misses::tsunami.ide 70 system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039320090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039320090 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 1039517841 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1039517841 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles @@ -747,8 +743,8 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60145.838542 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60145.838542 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 60157.282465 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60157.282465 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency @@ -770,22 +766,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4820184 # DTB read hits +system.cpu0.dtb.read_hits 4820532 # DTB read hits system.cpu0.dtb.read_misses 5970 # DTB read misses system.cpu0.dtb.read_acv 109 # DTB read access violations -system.cpu0.dtb.read_accesses 427969 # DTB read accesses -system.cpu0.dtb.write_hits 3428698 # DTB write hits +system.cpu0.dtb.read_accesses 427970 # DTB read accesses +system.cpu0.dtb.write_hits 3430087 # DTB write hits system.cpu0.dtb.write_misses 674 # DTB write misses system.cpu0.dtb.write_acv 81 # DTB write access violations system.cpu0.dtb.write_accesses 164325 # DTB write accesses -system.cpu0.dtb.data_hits 8248882 # DTB hits +system.cpu0.dtb.data_hits 8250619 # DTB hits system.cpu0.dtb.data_misses 6644 # DTB misses system.cpu0.dtb.data_acv 190 # DTB access violations -system.cpu0.dtb.data_accesses 592294 # DTB accesses -system.cpu0.itb.fetch_hits 2727685 # ITB hits +system.cpu0.dtb.data_accesses 592295 # DTB accesses +system.cpu0.itb.fetch_hits 2728150 # ITB hits system.cpu0.itb.fetch_misses 3015 # ITB misses system.cpu0.itb.fetch_acv 97 # ITB acv -system.cpu0.itb.fetch_accesses 2730700 # ITB accesses +system.cpu0.itb.fetch_accesses 2731165 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -798,87 +794,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929885466 # number of cpu cycles simulated +system.cpu0.numCycles 929887646 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30965233 # Number of instructions committed -system.cpu0.committedOps 30965233 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28877959 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 164894 # Number of float alu accesses -system.cpu0.num_func_calls 798570 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3871145 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28877959 # number of integer instructions -system.cpu0.num_fp_insts 164894 # number of float instructions -system.cpu0.num_int_register_reads 39995093 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21215374 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85232 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86749 # number of times the floating registers were written -system.cpu0.num_mem_refs 8278255 # number of memory refs -system.cpu0.num_load_insts 4840998 # Number of load instructions -system.cpu0.num_store_insts 3437257 # Number of store instructions -system.cpu0.num_idle_cycles 908001022.276160 # Number of idle cycles -system.cpu0.num_busy_cycles 21884443.723840 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023535 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976465 # Percentage of idle cycles -system.cpu0.Branches 4926958 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1578460 5.10% 5.10% # Class of executed instruction -system.cpu0.op_class::IntAlu 20418617 65.93% 71.02% # Class of executed instruction -system.cpu0.op_class::IntMult 31850 0.10% 71.13% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.13% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12902 0.04% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1598 0.01% 71.17% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.17% # Class of executed instruction -system.cpu0.op_class::MemRead 4971884 16.05% 87.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 3440357 11.11% 98.33% # Class of executed instruction -system.cpu0.op_class::IprAccess 516399 1.67% 100.00% # Class of executed instruction +system.cpu0.committedInsts 30964546 # Number of instructions committed +system.cpu0.committedOps 30964546 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 28877269 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 164895 # Number of float alu accesses +system.cpu0.num_func_calls 798898 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3870413 # number of instructions that are conditional controls +system.cpu0.num_int_insts 28877269 # number of integer instructions +system.cpu0.num_fp_insts 164895 # number of float instructions +system.cpu0.num_int_register_reads 39993375 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21214284 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 85263 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 86719 # number of times the floating registers were written +system.cpu0.num_mem_refs 8280000 # number of memory refs +system.cpu0.num_load_insts 4841351 # Number of load instructions +system.cpu0.num_store_insts 3438649 # Number of store instructions +system.cpu0.num_idle_cycles 908004121.642144 # Number of idle cycles +system.cpu0.num_busy_cycles 21883524.357856 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023534 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976466 # Percentage of idle cycles +system.cpu0.Branches 4926659 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1578204 5.10% 5.10% # Class of executed instruction +system.cpu0.op_class::IntAlu 20416117 65.92% 71.01% # Class of executed instruction +system.cpu0.op_class::IntMult 31858 0.10% 71.12% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12902 0.04% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1598 0.01% 71.16% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.16% # Class of executed instruction +system.cpu0.op_class::MemRead 4972343 16.05% 87.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 3441751 11.11% 98.33% # Class of executed instruction +system.cpu0.op_class::IprAccess 516607 1.67% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30972067 # Class of executed instruction +system.cpu0.op_class::total 30971380 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6423 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211353 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6422 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211354 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 74794 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105680 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182555 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105681 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182556 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 73427 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 73427 49.30% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 148935 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1818769989500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 39220500 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357294000 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22445011500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1841611515500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1818780188000 98.76% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 39182000 0.00% 98.76% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 357649000 0.02% 98.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22434661500 1.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841611680500 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694805 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815836 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694798 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815832 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -917,7 +913,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175298 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175299 91.20% 93.41% # number of callpals executed system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed @@ -926,20 +922,20 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.95% # nu system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192209 # number of callpals executed +system.cpu0.kern.callpal::total 192210 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1738 # number of protection mode switches system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1906 -system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::kernel 1907 +system.cpu0.kern.mode_good::user 1738 system.cpu0.kern.mode_good::idle 169 -system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.322020 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29707694000 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2577107000 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1809326710000 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.391059 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29705567000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2577814500 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809328294500 98.25% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 4175 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -972,459 +968,479 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.throughput 112481926 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 825463 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 825443 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 3528 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 3528 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 385263 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17281 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 33 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 137914 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 137914 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 5 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 903973 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1415042 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 2319015 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 28925888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 57212080 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 86137968 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 204476224 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 2671872 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2218881500 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 2062606 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2062584 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835833 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17283 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 38 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 8 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302707 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302707 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 7 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1928849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657196 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5586045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61721856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142735808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204457664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 41925 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3235706 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012896 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112826 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3193978 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41728 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3235706 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2218971499 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2036319024 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2034366165 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2306325269 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2306919756 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.throughput 1470003 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 2992 # Transaction distribution -system.iobus.trans_dist::ReadResp 2992 # Transaction distribution -system.iobus.trans_dist::WriteReq 20808 # Transaction distribution -system.iobus.trans_dist::WriteResp 20808 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 2342 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 54 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 7420 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 2926 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 12900 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 34700 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 47600 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.cchip.pio 9368 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.pchip.pio 560 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.io.pio 55 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.uart.pio 3710 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ide.pio 2083 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 16 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 15792 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.tsunami.ide.dma::total 1107376 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1123168 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2707176 # Total data (bytes) +system.iobus.trans_dist::ReadReq 7317 # Transaction distribution +system.iobus.trans_dist::ReadResp 7317 # Transaction distribution +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 27090 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 24272 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18256 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 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Layer utilization (%) system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer29.occupancy 155677802 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9372000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 9370000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17532750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17534501 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.icache.tags.replacements 964098 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.196429 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 40281211 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964609 # Sample count of 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system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 42226967 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 42226967 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30459275 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7343645 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2478291 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 40281211 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30459275 # number of demand (read+write) hits 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0.023774 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016557 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016660 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.121807 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023774 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016557 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016660 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.121807 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023774 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.221136 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14055.887056 # average ReadReq miss latency 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overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997287463 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5522548963 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010954 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.010954 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016660 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116081 # mshr miss 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cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5519265825 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1521699500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3997566325 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5519265825 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010946 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010946 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016628 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116194 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010946 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.905420 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.128051 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12208.173233 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.905420 # average overall mshr miss latency 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cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4706833 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1149993 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3079872 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8936698 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3304057 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 852599 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1993016 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149672 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123864 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20936 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58967 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203767 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123317 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20808 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55205 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199330 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8010890 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 2002592 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5072888 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15086370 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8010890 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 2002592 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5072888 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15086370 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151074 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082508 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183103 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.153289 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049890 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051112 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.315634 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136183 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075656 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100592 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130361 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.094049 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000163 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109341 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069141 # miss rate for demand accesses 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# average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 26271.400519 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.249763 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16519.708469 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8074.645116 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 15889.111111 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 15889.111111 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27788.790498 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25280.859334 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15406.369391 # average overall miss latency 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of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15086537 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8012457 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2001359 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5072721 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15086537 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151014 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.083075 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.183212 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.153375 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049897 # miss rate for WriteReq accesses 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WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32417.691581 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26312.493264 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13186.696811 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16710.453847 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8144.152281 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16312.750000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16312.750000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27746.165837 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25302.006423 # average overall miss latency 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fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835818 # number of writebacks -system.cpu0.dcache.writebacks::total 835818 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 296217 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 296217 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534994 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 534994 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1640 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1640 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 831211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 831211 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 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cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320834500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419662000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740496500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 570803000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762371000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333174000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082508 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086925 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040574 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051112 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047199 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022383 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100592 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102549 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040011 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000163 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000045 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069141 # mshr miss rate for demand accesses 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31067.517737 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32535.542482 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.774929 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12049.776914 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11824.788544 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 13888.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 13888.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25674.260736 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20463.018083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21905.420811 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835833 # number of writebacks +system.cpu0.dcache.writebacks::total 835833 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 297087 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 297087 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 534212 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 534212 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1624 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1624 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 831299 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 831299 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 831299 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 831299 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 95497 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 267360 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 362857 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43579 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 93950 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 137529 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2101 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6057 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8158 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 8 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 139076 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 361310 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 500386 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 139076 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 361310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 500386 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2008989000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4477810640 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6486799640 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1555821240 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2924918842 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4480740082 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23501750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 73479753 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96981503 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 114498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 114498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3564810240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7402729482 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10967539722 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3564810240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7402729482 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10967539722 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249745500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342957000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 592702500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320247000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 420262500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740509500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569992500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 763219500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1333212000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.083075 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086781 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040600 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051159 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047167 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022366 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100695 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.103022 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040066 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000145 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033168 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069491 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071226 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033168 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21037.194886 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16748.244464 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17877.013920 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35701.168912 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31132.717850 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32580.329109 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11185.982865 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12131.377415 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11887.901814 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14312.250000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14312.250000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25632.102160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20488.581777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21918.158626 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1439,22 +1455,22 @@ system.cpu1.dtb.fetch_hits 0 # IT system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1168812 # DTB read hits -system.cpu1.dtb.read_misses 1325 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141647 # DTB read accesses -system.cpu1.dtb.write_hits 873733 # DTB write hits -system.cpu1.dtb.write_misses 170 # DTB write misses +system.cpu1.dtb.read_hits 1168269 # DTB read hits +system.cpu1.dtb.read_misses 1330 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 141659 # DTB read accesses +system.cpu1.dtb.write_hits 872893 # DTB write hits +system.cpu1.dtb.write_misses 171 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57095 # DTB write accesses -system.cpu1.dtb.data_hits 2042545 # DTB hits -system.cpu1.dtb.data_misses 1495 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 198742 # DTB accesses -system.cpu1.itb.fetch_hits 849434 # ITB hits -system.cpu1.itb.fetch_misses 664 # ITB misses +system.cpu1.dtb.write_accesses 57101 # DTB write accesses +system.cpu1.dtb.data_hits 2041162 # DTB hits +system.cpu1.dtb.data_misses 1501 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 198760 # DTB accesses +system.cpu1.itb.fetch_hits 849127 # ITB hits +system.cpu1.itb.fetch_misses 665 # ITB misses system.cpu1.itb.fetch_acv 34 # ITB acv -system.cpu1.itb.fetch_accesses 850098 # ITB accesses +system.cpu1.itb.fetch_accesses 849792 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -1467,64 +1483,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953402608 # number of cpu cycles simulated +system.cpu1.numCycles 953403050 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7466514 # Number of instructions committed -system.cpu1.committedOps 7466514 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6940405 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43972 # Number of float alu accesses -system.cpu1.num_func_calls 203873 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 905018 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6940405 # number of integer instructions -system.cpu1.num_fp_insts 43972 # number of float instructions -system.cpu1.num_int_register_reads 9656232 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5062933 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23750 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written -system.cpu1.num_mem_refs 2049510 # number of memory refs -system.cpu1.num_load_insts 1173515 # Number of load instructions -system.cpu1.num_store_insts 875995 # Number of store instructions -system.cpu1.num_idle_cycles 923975227.132686 # Number of idle cycles -system.cpu1.num_busy_cycles 29427380.867314 # Number of busy cycles +system.cpu1.committedInsts 7463992 # Number of instructions committed +system.cpu1.committedOps 7463992 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 6937939 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 43895 # Number of float alu accesses +system.cpu1.num_func_calls 203449 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 905325 # number of instructions that are conditional controls +system.cpu1.num_int_insts 6937939 # number of integer instructions +system.cpu1.num_fp_insts 43895 # number of float instructions +system.cpu1.num_int_register_reads 9652072 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5060714 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 23736 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 24066 # number of times the floating registers were written +system.cpu1.num_mem_refs 2048141 # number of memory refs +system.cpu1.num_load_insts 1172984 # Number of load instructions +system.cpu1.num_store_insts 875157 # Number of store instructions +system.cpu1.num_idle_cycles 923975246.943285 # Number of idle cycles +system.cpu1.num_busy_cycles 29427803.056715 # Number of busy cycles system.cpu1.not_idle_fraction 0.030866 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969134 # Percentage of idle cycles -system.cpu1.Branches 1173577 # Number of branches fetched -system.cpu1.op_class::No_OpClass 399506 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4845173 64.88% 70.23% # Class of executed instruction -system.cpu1.op_class::IntMult 8216 0.11% 70.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5112 0.07% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::MemRead 1201694 16.09% 86.51% # Class of executed instruction -system.cpu1.op_class::MemWrite 877208 11.75% 98.25% # Class of executed instruction -system.cpu1.op_class::IprAccess 130346 1.75% 100.00% # Class of executed instruction +system.cpu1.Branches 1173357 # Number of branches fetched +system.cpu1.op_class::No_OpClass 399705 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 4844088 64.89% 70.24% # Class of executed instruction +system.cpu1.op_class::IntMult 8214 0.11% 70.35% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5110 0.07% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 70.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 70.43% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.43% # Class of executed instruction +system.cpu1.op_class::MemRead 1201071 16.09% 86.52% # Class of executed instruction +system.cpu1.op_class::MemWrite 876369 11.74% 98.26% # Class of executed instruction +system.cpu1.op_class::IprAccess 130183 1.74% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7468065 # Class of executed instruction +system.cpu1.op_class::total 7465550 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1542,35 +1558,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9007020 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8266685 # Number of conditional branches predicted +system.cpu2.branchPred.lookups 9020137 # Number of BP lookups +system.cpu2.branchPred.condPredicted 8282573 # Number of conditional branches predicted system.cpu2.branchPred.condIncorrect 125563 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 6913379 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 4889018 # Number of BTB hits +system.cpu2.branchPred.BTBLookups 6965204 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 4892106 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 70.718212 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 301119 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7670 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 70.236364 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 299658 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7807 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3485225 # DTB read hits -system.cpu2.dtb.read_misses 12620 # DTB read misses +system.cpu2.dtb.read_hits 3485260 # DTB read hits +system.cpu2.dtb.read_misses 12402 # DTB read misses system.cpu2.dtb.read_acv 152 # DTB read access violations -system.cpu2.dtb.read_accesses 227645 # DTB read accesses -system.cpu2.dtb.write_hits 2140940 # DTB write hits -system.cpu2.dtb.write_misses 2817 # DTB write misses -system.cpu2.dtb.write_acv 139 # DTB write access violations -system.cpu2.dtb.write_accesses 85106 # DTB write accesses -system.cpu2.dtb.data_hits 5626165 # DTB hits -system.cpu2.dtb.data_misses 15437 # DTB misses -system.cpu2.dtb.data_acv 291 # DTB access violations -system.cpu2.dtb.data_accesses 312751 # DTB accesses -system.cpu2.itb.fetch_hits 539657 # ITB hits -system.cpu2.itb.fetch_misses 5944 # ITB misses -system.cpu2.itb.fetch_acv 165 # ITB acv -system.cpu2.itb.fetch_accesses 545601 # ITB accesses +system.cpu2.dtb.read_accesses 227268 # DTB read accesses +system.cpu2.dtb.write_hits 2138350 # DTB write hits +system.cpu2.dtb.write_misses 2805 # DTB write misses +system.cpu2.dtb.write_acv 140 # DTB write access violations +system.cpu2.dtb.write_accesses 85115 # DTB write accesses +system.cpu2.dtb.data_hits 5623610 # DTB hits +system.cpu2.dtb.data_misses 15207 # DTB misses +system.cpu2.dtb.data_acv 292 # DTB access violations +system.cpu2.dtb.data_accesses 312383 # DTB accesses +system.cpu2.itb.fetch_hits 538601 # ITB hits +system.cpu2.itb.fetch_misses 5813 # ITB misses +system.cpu2.itb.fetch_acv 166 # ITB acv +system.cpu2.itb.fetch_accesses 544414 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1583,259 +1599,259 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 29515720 # number of cpu cycles simulated +system.cpu2.numCycles 29513686 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9404916 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 35474807 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9007020 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5190137 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18003717 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 410566 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 517 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 9775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1999 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 235781 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 98995 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 442 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2822037 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92550 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 27961187 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.268716 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.388099 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9389582 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 35469274 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 9020137 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 5191764 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 18021119 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 410530 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 647 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1948 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 228650 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 98931 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 387 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2818143 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 92772 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 27955647 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.268770 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.388372 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20241670 72.39% 72.39% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312691 1.12% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 474251 1.70% 75.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3278987 11.73% 86.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 837934 3.00% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 194435 0.70% 90.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 239683 0.86% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 437644 1.57% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1943892 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20239272 72.40% 72.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 311789 1.12% 73.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 473018 1.69% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3278988 11.73% 86.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 836372 2.99% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 194449 0.70% 90.62% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 239819 0.86% 91.48% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 437682 1.57% 93.05% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1944258 6.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 27961187 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.305160 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.201895 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7704419 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13193149 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6090024 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 535254 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 192290 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 176132 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13346 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 32094888 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 42715 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 192290 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7987526 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4830275 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6354829 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6312082 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2038145 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 31271508 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68877 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 405466 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 55957 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 963204 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 20931686 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 38638449 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 38578281 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56251 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 19026086 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1905600 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 533120 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63723 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3942739 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3510198 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2234995 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 462280 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329256 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 28739879 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 680947 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 28391596 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 17529 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2438506 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1151582 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 487021 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 27961187 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.015393 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.594251 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 27955647 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.305626 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.201791 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7697914 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 13194592 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6089531 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 535341 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 192357 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 175638 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13257 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 32098439 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42458 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 192357 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7981444 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4806689 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6360452 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6310892 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2057913 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 31276153 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 68586 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 406035 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 57262 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 980638 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 20937225 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 38641604 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 38581458 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56230 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 19023888 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1913337 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 532654 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63537 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3939185 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3509523 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2229292 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 463055 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 331167 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 28745476 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 680921 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 28394222 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16375 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2445259 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1154216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487025 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 27955647 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.015688 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.594887 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17574861 62.85% 62.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2788082 9.97% 72.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1379347 4.93% 77.76% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4037262 14.44% 92.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1018579 3.64% 95.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 572705 2.05% 97.89% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 385941 1.38% 99.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 155733 0.56% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48677 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17573743 62.86% 62.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2782129 9.95% 72.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1379697 4.94% 77.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4038946 14.45% 92.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1015784 3.63% 95.83% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 573145 2.05% 97.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 387606 1.39% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 155412 0.56% 99.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 49185 0.18% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 27961187 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 27955647 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 82533 21.35% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 178965 46.29% 67.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 125088 32.36% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 83781 21.60% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.60% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179225 46.21% 67.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 124810 32.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 2456 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 22261960 78.41% 78.42% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21111 0.07% 78.49% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.49% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20516 0.07% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.57% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3614417 12.73% 91.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2165470 7.63% 98.93% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 304438 1.07% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 22268545 78.43% 78.43% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21109 0.07% 78.51% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 78.51% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20518 0.07% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 78.58% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1228 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 78.59% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3613635 12.73% 91.31% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2162330 7.62% 98.93% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 304401 1.07% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 28391596 # Type of FU issued -system.cpu2.iq.rate 0.961914 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 386586 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.013616 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 84894790 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 31745632 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27810644 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 253704 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119619 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 117118 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 28639647 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 136079 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206810 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 28394222 # Type of FU issued +system.cpu2.iq.rate 0.962070 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 387816 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.013658 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 84894498 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 31757890 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27813110 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253784 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119651 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117192 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 28643478 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136104 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 207211 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 438537 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1486 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6057 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 183313 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 438819 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1413 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6020 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 178766 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5003 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 177760 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5023 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 176307 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 192290 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4010862 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 349296 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 30806306 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 54542 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3510198 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2234995 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 606167 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15566 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 285460 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6057 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62858 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 135105 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197963 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 28193561 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3506622 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 198035 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 192357 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4003600 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 328635 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 30811270 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 51966 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3509523 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2229292 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606230 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15640 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 265026 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6020 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63511 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 134698 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 198209 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 28196871 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3506429 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 197351 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1385480 # number of nop insts executed -system.cpu2.iew.exec_refs 5655108 # number of memory reference insts executed -system.cpu2.iew.exec_branches 5954900 # Number of branches executed -system.cpu2.iew.exec_stores 2148486 # Number of stores executed -system.cpu2.iew.exec_rate 0.955205 # Inst execution rate -system.cpu2.iew.wb_sent 27969918 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27927762 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15888662 # num instructions producing a value -system.cpu2.iew.wb_consumers 19538696 # num instructions consuming a value +system.cpu2.iew.exec_nop 1384873 # number of nop insts executed +system.cpu2.iew.exec_refs 5652310 # number of memory reference insts executed +system.cpu2.iew.exec_branches 5956275 # Number of branches executed +system.cpu2.iew.exec_stores 2145881 # Number of stores executed +system.cpu2.iew.exec_rate 0.955383 # Inst execution rate +system.cpu2.iew.wb_sent 27971955 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27930302 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15891558 # num instructions producing a value +system.cpu2.iew.wb_consumers 19546280 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.946200 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.813189 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.946351 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.813022 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2672008 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 193926 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180997 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 27494343 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.021637 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.858517 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2680068 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 193896 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181086 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 27486207 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.021790 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.858200 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18377188 66.84% 66.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2251123 8.19% 75.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1180007 4.29% 79.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 3743706 13.62% 92.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 543464 1.98% 94.91% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 201872 0.73% 95.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 166281 0.60% 96.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 179533 0.65% 96.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 851169 3.10% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18368842 66.83% 66.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2248676 8.18% 75.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1182960 4.30% 79.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 3745017 13.63% 92.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 544035 1.98% 94.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201250 0.73% 95.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 165260 0.60% 96.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 179807 0.65% 96.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 850360 3.09% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 27494343 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 28089240 # Number of instructions committed -system.cpu2.commit.committedOps 28089240 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 27486207 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 28085126 # Number of instructions committed +system.cpu2.commit.committedOps 28085126 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5123343 # Number of memory references committed -system.cpu2.commit.loads 3071661 # Number of loads committed -system.cpu2.commit.membars 68272 # Number of memory barriers committed -system.cpu2.commit.branches 5784239 # Number of branches committed -system.cpu2.commit.fp_insts 115390 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 26574373 # Number of committed integer instructions. -system.cpu2.commit.function_calls 240380 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1220895 4.35% 4.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 21328709 75.93% 80.28% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.35% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20067 0.07% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.42% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.42% # Class of committed instruction +system.cpu2.commit.refs 5121230 # Number of memory references committed +system.cpu2.commit.loads 3070704 # Number of loads committed +system.cpu2.commit.membars 68250 # Number of memory barriers committed +system.cpu2.commit.branches 5783973 # Number of branches committed +system.cpu2.commit.fp_insts 115466 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 26570607 # Number of committed integer instructions. +system.cpu2.commit.function_calls 240322 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1220562 4.35% 4.35% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 21327099 75.94% 80.28% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20651 0.07% 80.36% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 80.36% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20069 0.07% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 80.43% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::FloatDiv 1228 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 80.43% # Class of committed instruction @@ -1858,30 +1874,30 @@ system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 80.43% system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 80.43% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 80.43% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3139933 11.18% 91.61% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2053319 7.31% 98.92% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 304438 1.08% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3138954 11.18% 91.61% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2052162 7.31% 98.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 304401 1.08% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 28089240 # Class of committed instruction -system.cpu2.commit.bw_lim_events 851169 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 28085126 # Class of committed instruction +system.cpu2.commit.bw_lim_events 850360 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 57327258 # The number of ROB reads -system.cpu2.rob.rob_writes 61989353 # The number of ROB writes -system.cpu2.timesIdled 175568 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1554533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1746289037 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 26870801 # Number of Instructions Simulated -system.cpu2.committedOps 26870801 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.098431 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.098431 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.910389 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.910389 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 36957190 # number of integer regfile reads -system.cpu2.int_regfile_writes 19824047 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70953 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70972 # number of floating regfile writes -system.cpu2.misc_regfile_reads 3637810 # number of misc regfile reads -system.cpu2.misc_regfile_writes 273227 # number of misc regfile writes +system.cpu2.rob.rob_reads 57323983 # The number of ROB reads +system.cpu2.rob.rob_writes 61998256 # The number of ROB writes +system.cpu2.timesIdled 175445 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1558039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1746293269 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 26867020 # Number of Instructions Simulated +system.cpu2.committedOps 26867020 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.098510 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.098510 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.910324 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.910324 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 36957336 # number of integer regfile reads +system.cpu2.int_regfile_writes 19827241 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70923 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71075 # number of floating regfile writes +system.cpu2.misc_regfile_reads 3638892 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273174 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu2.kern.inst.hwrei 0 # number of hwrei instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index ad6f569ba..59143a518 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,174 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.145505 # Number of seconds simulated -sim_ticks 1145504982000 # Number of ticks simulated -final_tick 1145504982000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.658500 # Number of seconds simulated +sim_ticks 2658500429500 # Number of ticks simulated +final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113120 # Simulator instruction rate (inst/s) -host_op_rate 136231 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2095202848 # Simulator tick rate (ticks/s) -host_mem_usage 413760 # Number of bytes of host memory used -host_seconds 546.73 # Real time elapsed on the host -sim_insts 61845931 # Number of instructions simulated -sim_ops 74481224 # Number of ops (including micro ops) simulated +host_inst_rate 100914 # Simulator instruction rate (inst/s) +host_op_rate 121517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4256503307 # Simulator tick rate (ticks/s) +host_mem_usage 437672 # Number of bytes of host memory used +host_seconds 624.57 # Real time elapsed on the host +sim_insts 63028509 # Number of instructions simulated +sim_ops 75896503 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 223 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 391 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 615 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 223 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 391 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 615 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 223 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 391 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 615 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 7004988 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3603320 # Number of bytes read from this memory -system.physmem.bytes_read::total 60941044 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 751104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 270784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1021888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4281152 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory +system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7308496 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 109512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56320 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457305 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66893 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823729 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43938393 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 112 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 6115196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3145617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53200156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 655697 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 236388 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 892085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3737349 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 14841 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 2627962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6380152 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3737349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43938393 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 112 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 6130037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 5773579 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59580308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6457305 # Number of read requests accepted -system.physmem.writeReqs 823729 # Number of write requests accepted -system.physmem.readBursts 6457305 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823729 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 413239936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 27584 # Total number of bytes read from write queue -system.physmem.bytesWritten 7320448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 60941044 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7308496 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 431 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709326 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12284 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 403300 # Per bank write bursts -system.physmem.perBankRdBursts::1 403658 # Per bank write bursts -system.physmem.perBankRdBursts::2 403038 # Per bank write bursts -system.physmem.perBankRdBursts::3 403410 # Per bank write bursts -system.physmem.perBankRdBursts::4 406147 # Per bank write bursts -system.physmem.perBankRdBursts::5 403703 # Per bank write bursts -system.physmem.perBankRdBursts::6 403511 # Per bank write bursts -system.physmem.perBankRdBursts::7 403334 # Per bank write bursts -system.physmem.perBankRdBursts::8 403656 # Per bank write bursts -system.physmem.perBankRdBursts::9 404136 # Per bank write bursts -system.physmem.perBankRdBursts::10 403079 # Per bank write bursts -system.physmem.perBankRdBursts::11 402530 # Per bank write bursts -system.physmem.perBankRdBursts::12 403635 # Per bank write bursts -system.physmem.perBankRdBursts::13 403544 # Per bank write bursts -system.physmem.perBankRdBursts::14 403293 # Per bank write bursts -system.physmem.perBankRdBursts::15 402900 # Per bank write bursts -system.physmem.perBankWrBursts::0 6991 # Per bank write bursts -system.physmem.perBankWrBursts::1 7395 # Per bank write bursts -system.physmem.perBankWrBursts::2 6850 # Per bank write bursts -system.physmem.perBankWrBursts::3 7056 # Per bank write bursts -system.physmem.perBankWrBursts::4 7584 # Per bank write bursts -system.physmem.perBankWrBursts::5 7290 # Per bank write bursts -system.physmem.perBankWrBursts::6 7311 # Per bank write bursts -system.physmem.perBankWrBursts::7 7141 # Per bank write bursts -system.physmem.perBankWrBursts::8 7309 # Per bank write bursts -system.physmem.perBankWrBursts::9 7743 # Per bank write bursts -system.physmem.perBankWrBursts::10 6877 # Per bank write bursts -system.physmem.perBankWrBursts::11 6465 # Per bank write bursts -system.physmem.perBankWrBursts::12 7382 # Per bank write bursts -system.physmem.perBankWrBursts::13 7153 # Per bank write bursts -system.physmem.perBankWrBursts::14 7067 # Per bank write bursts -system.physmem.perBankWrBursts::15 6768 # Per bank write bursts +system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 825078 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46147592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 120 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 252267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1885334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 241 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 189481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 1942075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50417182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82597 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1632054 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 1133021 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2771469 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1632054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46147592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 258662 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1885334 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 241 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1322502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 1942075 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53188651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15512856 # Number of read requests accepted +system.physmem.writeReqs 825078 # Number of write requests accepted +system.physmem.readBursts 15512856 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825078 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 992706816 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 115968 # Total number of bytes read from write queue +system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134034100 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7367952 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1812 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709689 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15707 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 969471 # Per bank write bursts +system.physmem.perBankRdBursts::1 969246 # Per bank write bursts +system.physmem.perBankRdBursts::2 969043 # Per bank write bursts +system.physmem.perBankRdBursts::3 969564 # Per bank write bursts +system.physmem.perBankRdBursts::4 971813 # Per bank write bursts +system.physmem.perBankRdBursts::5 969510 # Per bank write bursts +system.physmem.perBankRdBursts::6 969103 # Per bank write bursts +system.physmem.perBankRdBursts::7 968972 # Per bank write bursts +system.physmem.perBankRdBursts::8 969597 # Per bank write bursts +system.physmem.perBankRdBursts::9 969588 # Per bank write bursts +system.physmem.perBankRdBursts::10 969467 # Per bank write bursts +system.physmem.perBankRdBursts::11 968939 # Per bank write bursts +system.physmem.perBankRdBursts::12 969138 # Per bank write bursts +system.physmem.perBankRdBursts::13 969444 # Per bank write bursts +system.physmem.perBankRdBursts::14 969295 # Per bank write bursts +system.physmem.perBankRdBursts::15 968854 # Per bank write bursts +system.physmem.perBankWrBursts::0 7363 # Per bank write bursts +system.physmem.perBankWrBursts::1 7345 # Per bank write bursts +system.physmem.perBankWrBursts::2 6989 # Per bank write bursts +system.physmem.perBankWrBursts::3 7254 # Per bank write bursts +system.physmem.perBankWrBursts::4 7419 # Per bank write bursts +system.physmem.perBankWrBursts::5 7425 # Per bank write bursts +system.physmem.perBankWrBursts::6 7374 # Per bank write bursts +system.physmem.perBankWrBursts::7 7152 # Per bank write bursts +system.physmem.perBankWrBursts::8 7408 # Per bank write bursts +system.physmem.perBankWrBursts::9 7360 # Per bank write bursts +system.physmem.perBankWrBursts::10 7357 # Per bank write bursts +system.physmem.perBankWrBursts::11 7062 # Per bank write bursts +system.physmem.perBankWrBursts::12 6947 # Per bank write bursts +system.physmem.perBankWrBursts::13 7077 # Per bank write bursts +system.physmem.perBankWrBursts::14 7057 # Per bank write bursts +system.physmem.perBankWrBursts::15 6784 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1145502120500 # Total gap between requests +system.physmem.totGap 2658500409000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) -system.physmem.readPktSize::3 6291481 # Read request sizes (log2) +system.physmem.readPktSize::3 15335449 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 165765 # Read request sizes (log2) +system.physmem.readPktSize::6 177348 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 756836 # Write request sizes (log2) +system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66893 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 558286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 398741 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 399967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 444496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 405001 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 431562 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1118263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1083915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1408608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 55788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 45494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 41962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 40334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8421 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7962 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 7851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67794 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1046196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1019688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 986842 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1094338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 993106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1055542 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2738032 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2641383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3439999 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 128528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 110050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 101603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 98027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18942 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see @@ -186,31 +180,31 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6584 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6659 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6656 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6657 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7285 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see @@ -235,456 +229,585 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 460787 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 912.700193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 781.910252 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.668132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24338 5.28% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21658 4.70% 9.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5935 1.29% 11.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2553 0.55% 11.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2424 0.53% 12.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1615 0.35% 12.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4021 0.87% 13.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 977 0.21% 13.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 397266 86.21% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 460787 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 970.665664 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 26177.869763 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6645 99.89% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.50733e+06-1.57286e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6652 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6652 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.195129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.166489 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.984981 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2678 40.26% 40.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 22 0.33% 40.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3930 59.08% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 20 0.30% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6652 # Writes before turning the bus around for reads -system.physmem.totQLat 165525335000 # Total ticks spent queuing -system.physmem.totMemAccLat 286591722500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 32284370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25635.52 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1037696 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.760762 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 885.523874 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 219.463963 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 32040 3.09% 3.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21332 2.06% 5.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9404 0.91% 6.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2470 0.24% 6.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3075 0.30% 6.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2164 0.21% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8825 0.85% 7.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1075 0.10% 7.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957311 92.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1037696 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6640 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2336.000602 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97357.467769 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6632 99.88% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 3 0.05% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6640 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6640 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.375452 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.330517 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281391 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2518 37.92% 37.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 36 0.54% 38.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3683 55.47% 93.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads +system.physmem.totQLat 403478953250 # Total ticks spent queuing +system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44385.52 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.75 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 6.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 53.20 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 6.38 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.87 # Data bus utilization in percentage -system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.81 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.84 # Average write queue length when enqueuing -system.physmem.readRowHits 6016106 # Number of row buffer hits during reads -system.physmem.writeRowHits 94363 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.17 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.48 # Row buffer hit rate for writes -system.physmem.avgGap 157326.85 # Average gap between requests -system.physmem.pageHitRate 92.99 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 907058635500 # Time in different power states -system.physmem.memoryStateTime::REF 38250680000 # Time in different power states +system.physmem.busUtil 2.94 # Data bus utilization in percentage +system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing +system.physmem.readRowHits 14503444 # Number of row buffer hits during reads +system.physmem.writeRowHits 85277 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes +system.physmem.avgGap 162719.50 # Average gap between requests +system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states +system.physmem.memoryStateTime::REF 88773100000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 200188472000 # Time in different power states +system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 61688542 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7506218 # Transaction distribution -system.membus.trans_dist::ReadResp 7506218 # Transaction distribution -system.membus.trans_dist::WriteReq 767823 # Transaction distribution -system.membus.trans_dist::WriteResp 767823 # Transaction distribution -system.membus.trans_dist::Writeback 66893 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33061 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17229 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12284 # Transaction distribution -system.membus.trans_dist::ReadExReq 137868 # Transaction distribution -system.membus.trans_dist::ReadExResp 137512 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382652 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 16692425 # Transaction distribution +system.membus.trans_dist::ReadResp 16692425 # Transaction distribution +system.membus.trans_dist::WriteReq 768873 # Transaction distribution +system.membus.trans_dist::WriteResp 768873 # Transaction distribution +system.membus.trans_dist::Writeback 67794 # Transaction distribution +system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution +system.membus.trans_dist::ReadExReq 15268 # Transaction distribution +system.membus.trans_dist::ReadExResp 8420 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11272 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 874 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1975193 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4370017 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12582912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 12582912 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16952929 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389988 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 22544 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1748 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17917892 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20332884 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 50331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 70664532 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 70664532 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1775897999 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.reqLayer1.occupancy 16500 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 68805 # Total snoops (count) +system.membus.snoop_fanout::samples 327203 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 327203 # Request fanout histogram +system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 10198500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 781000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8866177000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4931588399 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 15569082998 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 73238 # number of replacements -system.l2c.tags.tagsinuse 53823.910561 # Cycle average of tags in use -system.l2c.tags.total_refs 2398257 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 138408 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.327445 # Average number of references to valid blocks. +system.l2c.tags.replacements 92212 # number of replacements +system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use +system.l2c.tags.total_refs 396364 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38958.946929 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.880846 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.001294 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8788.881914 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.740937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6066.458640 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.594466 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000029 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.134108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000118 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.092567 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821288 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65164 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8664 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53947 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994324 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 23040420 # Number of tag accesses -system.l2c.tags.data_accesses 23040420 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 22272 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 6564 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 949144 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 22723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5189 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 959680 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1965572 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 575172 # number of Writeback hits -system.l2c.Writeback_hits::total 575172 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 954 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 1026 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1980 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 203 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 94 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 297 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 58656 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 50708 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109364 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22272 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 6564 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 1007800 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 22723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 1010388 # number of demand (read+write) hits -system.l2c.demand_hits::total 2074936 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22272 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 6564 # number of overall hits -system.l2c.overall_hits::cpu0.inst 1007800 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 22723 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5189 # number of overall hits -system.l2c.overall_hits::cpu1.inst 1010388 # number of overall hits -system.l2c.overall_hits::total 2074936 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 6 # number of ReadReq misses +system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.038184 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.449355 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000086 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.031121 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200258 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.174408 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5122526 # Number of tag accesses +system.l2c.tags.data_accesses 5122526 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 183 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 37 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 15214 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88074 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 233 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 19471 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76181 # number of ReadReq hits +system.l2c.ReadReq_hits::total 199443 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 215065 # number of Writeback hits +system.l2c.Writeback_hits::total 215065 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 3153 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 2020 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5173 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 94 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 2198 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 2398 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4596 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 37 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 17412 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 88074 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 21869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 76181 # number of demand (read+write) hits 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-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 157813376970 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 26394184094 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 184207561064 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.016636 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010088 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.012983 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.836448 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.798349 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818698 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.773942 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.761421 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770124 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.611822 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.483194 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.561182 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.073956 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000269 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000305 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097198 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000396 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.053569 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.073956 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 506972323 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6123836438 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 666250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 130500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 505005546 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7789791392 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14926797449 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12572348996 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155062093246 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167634442242 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125655500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721437217 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16847092717 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13698004496 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170783530463 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184481534959 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.216258 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.143937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.454953 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.713858 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.733860 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.722016 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.917616 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837405 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.874745 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.644221 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.655707 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.650308 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 57884.169884 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62303.885481 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59566.167086 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10018.723099 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10015.890202 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10017.436081 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10062.861871 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10007.663333 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10046.219095 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 56549.376777 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 58549.292491 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57227.311883 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86416.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56746.911592 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59191.361374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57592.222128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -701,67 +824,53 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 163445997 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 3265310 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3265309 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767823 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767823 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 575172 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 32693 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17526 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 50219 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 260531 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 260531 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1555911 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3285118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16087 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52607 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1583939 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2567940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 13476 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 53641 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 9128719 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 49766528 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 43750900 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26264 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 89112 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 50661248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 38001760 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 90928 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 182407496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 182407496 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4820708 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5144551012 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3505001405 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2792622052 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9525491 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30330496 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 3566573438 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1934335367 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 8290992 # Layer occupancy (ticks) -system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 30912744 # Layer occupancy (ticks) -system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46024799 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7474816 # Transaction distribution -system.iobus.trans_dist::ReadResp 7474816 # Transaction distribution -system.iobus.trans_dist::WriteReq 7966 # Transaction distribution -system.iobus.trans_dist::WriteResp 7966 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30566 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8038 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 171019 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution +system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution +system.iobus.trans_dist::WriteReq 8084 # Transaction distribution +system.iobus.trans_dist::WriteResp 8084 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 498 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -778,54 +887,53 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382652 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12582912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 12582912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14965564 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40335 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16076 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1464 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 273 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389988 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 50331648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 50331648 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 52721636 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 52721636 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21429000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4025000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 372000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 299000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.1 # Layer utilization (%) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) @@ -856,21 +964,21 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 6291456000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374686000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 15862213002 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) -system.cpu0.branchPred.lookups 6670288 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4756995 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 639495 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4605007 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3289427 # Number of BTB hits +system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) +system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.cpu0.branchPred.lookups 7247667 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.431531 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 870926 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 69312 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -894,25 +1002,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7193152 # DTB read hits -system.cpu0.dtb.read_misses 17493 # DTB read misses -system.cpu0.dtb.write_hits 6058571 # DTB write hits -system.cpu0.dtb.write_misses 1416 # DTB write misses +system.cpu0.dtb.read_hits 6449421 # DTB read hits +system.cpu0.dtb.read_misses 22629 # DTB read misses +system.cpu0.dtb.write_hits 5803237 # DTB write hits +system.cpu0.dtb.write_misses 1880 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1942 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1486 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 207 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 320 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7210645 # DTB read accesses -system.cpu0.dtb.write_accesses 6059987 # DTB write accesses +system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6472050 # DTB read accesses +system.cpu0.dtb.write_accesses 5805117 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 13251723 # DTB hits -system.cpu0.dtb.misses 18909 # DTB misses -system.cpu0.dtb.accesses 13270632 # DTB accesses +system.cpu0.dtb.hits 12252658 # DTB hits +system.cpu0.dtb.misses 24509 # DTB misses +system.cpu0.dtb.accesses 12277167 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -934,8 +1042,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 12268451 # ITB inst hits -system.cpu0.itb.inst_misses 4809 # ITB inst misses +system.cpu0.itb.inst_hits 13306402 # ITB inst hits +system.cpu0.itb.inst_misses 3981 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -944,82 +1052,83 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1294 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2809 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 12273260 # ITB inst accesses -system.cpu0.itb.hits 12268451 # DTB hits -system.cpu0.itb.misses 4809 # DTB misses -system.cpu0.itb.accesses 12273260 # DTB accesses -system.cpu0.numCycles 431172708 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses +system.cpu0.itb.hits 13306402 # DTB hits +system.cpu0.itb.misses 3981 # DTB misses +system.cpu0.itb.accesses 13310383 # DTB accesses +system.cpu0.numCycles 86779776 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29878954 # Number of instructions committed -system.cpu0.committedOps 36403873 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1704985 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 39450 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 1859905219 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 14.430649 # CPI: cycles per instruction -system.cpu0.ipc 0.069297 # IPC: instructions per cycle +system.cpu0.committedInsts 29469177 # Number of instructions committed +system.cpu0.committedOps 35692469 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 1968048 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 41085 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5234632408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.944764 # CPI: cycles per instruction +system.cpu0.ipc 0.339586 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 50317 # number of quiesce instructions executed -system.cpu0.tickCycles 351703818 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 79468890 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 775463 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.771777 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 11489502 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 775975 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 14.806536 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10202297000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.771777 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997601 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997601 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 47499 # number of quiesce instructions executed +system.cpu0.tickCycles 68210329 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 18569447 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 669895 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.780265 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 12632215 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 670407 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.842606 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6077782000 # Cycle when the warmup percentage was hit. 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12265480 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 12265480 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12265480 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.063265 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.063265 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.063265 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.063265 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.063265 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.063265 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13775.939724 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13775.939724 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13775.939724 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13775.939724 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13775.939724 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 27275662 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 27275662 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 12632215 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 12632215 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 12632215 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 12632215 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 12632215 # number of overall hits +system.cpu0.icache.overall_hits::total 12632215 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 670411 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 670411 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 670411 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 670411 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 670411 # number of overall misses +system.cpu0.icache.overall_misses::total 670411 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5588337897 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5588337897 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5588337897 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5588337897 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5588337897 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5588337897 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 13302626 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 13302626 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 13302626 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 13302626 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 13302626 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 13302626 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050397 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050397 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050397 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050397 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050397 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050397 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8335.689446 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8335.689446 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8335.689446 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8335.689446 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1028,125 +1137,465 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 775978 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 775978 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 775978 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 775978 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 775978 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 775978 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9133730845 # number of ReadReq MSHR miss cycles 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overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11770.605410 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11770.605410 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 670411 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 670411 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 670411 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 670411 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 670411 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 670411 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4581839103 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4581839103 # number of ReadReq MSHR miss cycles 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overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 331184 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.308279 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11419092 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 331547 # Sample count of references to valid blocks. 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miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3832963977 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 15354005377 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 15354005377 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 89150250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 89150250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 47371188 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 47371188 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 19186969354 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 19186969354 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 19186969354 # number of overall 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(read+write) accesses -system.cpu0.dcache.demand_accesses::total 11656490 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 11656490 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11656490 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.043661 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.043661 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.053657 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.053657 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.053041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.046176 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046176 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.048646 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.048646 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.048646 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048646 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 15024.455547 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15024.455547 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 49222.599227 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 49222.599227 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 10429.369443 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10429.369443 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 6367.951069 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6367.951069 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33836.766666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 33836.766666 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33836.766666 # average overall miss latency +system.cpu0.toL2Bus.trans_dist::ReadReq 1297449 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1098949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10915 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 277394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309853 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 48681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 54656 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 145161 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 136933 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1345495 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1384854 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13521 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 67392 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 2811262 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43053120 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45712112 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22348 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 121316 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 88908896 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 663093 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2014813 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.294791 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1420865 70.52% 70.52% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 593948 29.48% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2014813 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 66915000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 1010138647 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 706064108 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 7935497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 37067990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6505286 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 197873 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6075585 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2087 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 227641 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 451994 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu0.l2cache.tags.replacements 185568 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16045.943959 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1211197 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 201780 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5120960000 # Cycle when the warmup percentage was hit. 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Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.979367 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8308 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7886 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 36 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 61 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 933 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5734 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1544 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1527 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5465 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 648 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.507080 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.481323 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 22965812 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 22965812 # Number of data accesses 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number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1269500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1269500 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 847496588 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 847496588 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10873500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3613500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2174439269 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 2188926269 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10873500 # number of overall miss cycles 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accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5587 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1066751 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1102667 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.016717 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.030965 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052776 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.051525 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.910708 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.910708 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.929208 # miss rate for SCUpgradeReq accesses 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miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21446.745562 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 20887.283237 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26888.402857 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26812.506116 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16529.886177 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16529.886177 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19831.976186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19831.976186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst inf # average SCUpgradeFailReq miss latency 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29772.564784 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 29694.448470 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 1346 # number of cycles access was blocked +system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 39.588235 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.l2cache.fast_writes 0 # number of fast writes performed +system.cpu0.l2cache.cache_copies 0 # number of cache copies performed +system.cpu0.l2cache.writebacks::writebacks 114944 # number of writebacks +system.cpu0.l2cache.writebacks::total 114944 # number of writebacks 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overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1542727376 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8587835748 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 10140290124 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14160332496 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14160332496 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1312896000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1312896000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 15473228496 # number of overall MSHR uncacheable cycles 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25844.133976 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22170.951644 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average overall mshr miss latency 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Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11412864 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 364132 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.342656 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.092728 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924009 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.924009 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 24359055 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 24359055 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 5804369 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5804369 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275244 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275244 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147463 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147463 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146615 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146615 # number of StoreCondReq hits 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StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 254636964 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1359500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1359500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 7894557407 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7894557407 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 7894557407 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7894557407 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113968 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6113968 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5552195 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5552195 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157631 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157631 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157506 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157506 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 11666163 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11666163 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 11666163 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11666163 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050638 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.050638 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049881 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049881 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064505 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064505 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069147 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069147 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050278 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.050278 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050278 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11955.328076 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15140.583677 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23380.494353 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23380.494353 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1155,72 +1604,76 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 307170 # number of writebacks -system.cpu0.dcache.writebacks::total 307170 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 50178 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 50178 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 144238 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 144238 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 22 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 22 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 194416 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 194416 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 194416 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 194416 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 204937 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 204937 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 167692 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 167692 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 8526 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8526 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 7439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7439 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 372629 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 372629 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 372629 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 372629 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2523643558 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2523643558 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 7293302576 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7293302576 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 71695750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71695750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 32490812 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 32490812 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9816946134 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9816946134 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9816946134 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9816946134 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 170796523752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 170796523752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1513122000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1513122000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 172309645752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 172309645752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.035073 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035073 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.028846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.028846 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.052905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.052905 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.046176 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.046176 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031968 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.031968 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031968 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12314.240757 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12314.240757 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 43492.251127 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43492.251127 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 8409.072250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8409.072250 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 4367.631671 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4367.631671 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 26345.094273 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26345.094273 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks +system.cpu0.dcache.writebacks::total 277395 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1228,15 +1681,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 6159330 # Number of BP lookups -system.cpu1.branchPred.condPredicted 4534606 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 426160 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3924244 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3043762 # Number of BTB hits +system.cpu1.branchPred.lookups 7015971 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 77.563016 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 713205 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 64399 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1260,25 +1713,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6763605 # DTB read hits -system.cpu1.dtb.read_misses 17087 # DTB read misses -system.cpu1.dtb.write_hits 5563764 # DTB write hits -system.cpu1.dtb.write_misses 2456 # DTB write misses +system.cpu1.dtb.read_hits 7897430 # DTB read hits +system.cpu1.dtb.read_misses 21135 # DTB read misses +system.cpu1.dtb.write_hits 6047519 # DTB write hits +system.cpu1.dtb.write_misses 2176 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1713 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1918 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 260 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6780692 # DTB read accesses -system.cpu1.dtb.write_accesses 5566220 # DTB write accesses +system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7918565 # DTB read accesses +system.cpu1.dtb.write_accesses 6049695 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12327369 # DTB hits -system.cpu1.dtb.misses 19543 # DTB misses -system.cpu1.dtb.accesses 12346912 # DTB accesses +system.cpu1.dtb.hits 13944949 # DTB hits +system.cpu1.dtb.misses 23311 # DTB misses +system.cpu1.dtb.accesses 13968260 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1300,8 +1753,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 11206823 # ITB inst hits -system.cpu1.itb.inst_misses 4156 # ITB inst misses +system.cpu1.itb.inst_hits 14225149 # ITB inst hits +system.cpu1.itb.inst_misses 5020 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1310,84 +1763,81 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1190 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2956 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 11210979 # ITB inst accesses -system.cpu1.itb.hits 11206823 # DTB hits -system.cpu1.itb.misses 4156 # DTB misses -system.cpu1.itb.accesses 11210979 # DTB accesses -system.cpu1.numCycles 147611080 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses +system.cpu1.itb.hits 14225149 # DTB hits +system.cpu1.itb.misses 5020 # DTB misses +system.cpu1.itb.accesses 14230169 # DTB accesses +system.cpu1.numCycles 502333604 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 31966977 # Number of instructions committed -system.cpu1.committedOps 38077351 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1608279 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 39953 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 2144312243 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 4.617611 # CPI: cycles per instruction -system.cpu1.ipc 0.216562 # IPC: instructions per cycle +system.cpu1.committedInsts 33559332 # Number of instructions committed +system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 14.968522 # CPI: cycles per instruction +system.cpu1.ipc 0.066807 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40481 # number of quiesce instructions executed -system.cpu1.tickCycles 117794272 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 29816808 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 791766 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.612166 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 10411414 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 792278 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.141112 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 82581306250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.612166 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938696 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938696 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 45430 # number of quiesce instructions executed +system.cpu1.tickCycles 438569606 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 63763998 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 776883 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.132911 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13444222 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 777395 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 17.293939 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 68940011500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.132911 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974869 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974869 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 11995971 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 11995971 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 10411414 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 10411414 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 10411414 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 10411414 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 10411414 # number of overall hits -system.cpu1.icache.overall_hits::total 10411414 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 792279 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 792279 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 792279 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 792279 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 792279 # number of overall misses -system.cpu1.icache.overall_misses::total 792279 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10606605688 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10606605688 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10606605688 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10606605688 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10606605688 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10606605688 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 11203693 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 11203693 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 11203693 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 11203693 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 11203693 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 11203693 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.070716 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.070716 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.070716 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.070716 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.070716 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.070716 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13387.462861 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13387.462861 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13387.462861 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13387.462861 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13387.462861 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 29220629 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 29220629 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13444222 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13444222 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13444222 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13444222 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13444222 # number of overall hits +system.cpu1.icache.overall_hits::total 13444222 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 777395 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 777395 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 777395 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 777395 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 777395 # number of overall misses +system.cpu1.icache.overall_misses::total 777395 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6473834509 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6473834509 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6473834509 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6473834509 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6473834509 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6473834509 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 14221617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 14221617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 14221617 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 14221617 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 14221617 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 14221617 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054663 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.054663 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054663 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.054663 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054663 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.054663 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8327.599880 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8327.599880 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8327.599880 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8327.599880 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1396,128 +1846,468 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 792279 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 792279 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 792279 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 792279 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 792279 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 792279 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 9020137312 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 9020137312 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 9020137312 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 9020137312 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 9020137312 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 9020137312 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5771250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5771250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5771250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5771250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.070716 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.070716 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.070716 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.070716 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11385.051619 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11385.051619 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11385.051619 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 777395 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 777395 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 777395 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 777395 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 777395 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 777395 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5306001991 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5306001991 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5306001991 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5306001991 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5306001991 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5306001991 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7443500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7443500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7443500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7443500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054663 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.054663 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.054663 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6825.361613 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 300206 # number of replacements -system.cpu1.dcache.tags.tagsinuse 447.094079 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 10899911 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 300718 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 36.246287 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 76416861250 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 447.094079 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.873231 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.873231 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 350 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 45736548 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 45736548 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 6288103 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6288103 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 4421998 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4421998 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 78443 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78443 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 79055 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 79055 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 10710101 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 10710101 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 10710101 # number of overall hits -system.cpu1.dcache.overall_hits::total 10710101 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 241320 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 241320 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 223635 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 223635 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 10750 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10750 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 10087 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10087 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 464955 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 464955 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 464955 # number of overall misses -system.cpu1.dcache.overall_misses::total 464955 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 3586794993 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3586794993 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 8773828993 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 8773828993 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 90116500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 90116500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 50277799 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 50277799 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 12360623986 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12360623986 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 12360623986 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12360623986 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 6529423 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 6529423 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 4645633 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 4645633 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 89193 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 89193 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 89142 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 89142 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 11175056 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 11175056 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 11175056 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 11175056 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.036959 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.036959 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.048139 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.048139 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.120525 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.120525 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.113157 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113157 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.041607 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041607 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.041607 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.041607 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14863.231365 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14863.231365 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 39232.807892 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39232.807892 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 8382.930233 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8382.930233 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 4984.415485 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 4984.415485 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26584.559766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 26584.559766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 26584.559766 # average overall miss latency +system.cpu1.toL2Bus.trans_dist::ReadReq 2372884 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 2161619 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 757958 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 757958 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 242023 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 269237 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 145739 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1554692 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4766762 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17488 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67601 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6406543 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49741696 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44501144 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30140 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 121260 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 607829 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2003123 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1446836 72.23% 72.23% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2003123 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2275243689 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 1167104009 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 2025335762 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 9955994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 37292239 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6843055 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163843 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6478033 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2741 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 196423 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 563857 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time +system.cpu1.l2cache.tags.replacements 179577 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15624.309787 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1195829 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 195022 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2581358397500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4477.438103 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.594175 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.081575 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2724.649779 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8398.546154 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.273281 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001379 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000066 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.166299 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.512607 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.953632 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9457 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5975 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2071 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1611 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5775 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2329 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 929 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2717 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.577209 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364685 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23391503 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23391503 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29831 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7391 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 925413 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 962635 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 242023 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 242023 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits 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ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 484 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 144 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 85705 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 86333 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 484 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 144 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 85705 # number of overall misses +system.cpu1.l2cache.overall_misses::total 86333 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10993750 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3129500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1532483424 # number of ReadReq miss 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(read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3129500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2546523635 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2560646885 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10993750 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3129500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2546523635 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2560646885 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30315 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7535 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 986902 # 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number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1697350263 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10135528743 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 11842604756 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 174928342748 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174928342748 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 28797063287 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 28797063287 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 203725406035 # number of overall MSHR uncacheable cycles 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overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21047.968342 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42646.546375 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 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286173083 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 767000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 767000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4494234446 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4494234446 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4494234446 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4494234446 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183748244745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183748244745 # number of ReadReq MSHR uncacheable cycles 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14608.420345 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14608.420345 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 15888.942956 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15888.942956 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20975.817855 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20975.817855 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -1615,10 +2409,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 722335941002 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 722335941002 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 722335941002 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 722335941002 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 8849a7b1f..c758d0203 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.566439 # Number of seconds simulated -sim_ticks 2566439177500 # Number of ticks simulated -final_tick 2566439177500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.566404 # Number of seconds simulated +sim_ticks 2566404096500 # Number of ticks simulated +final_tick 2566404096500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109798 # Simulator instruction rate (inst/s) -host_op_rate 132178 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4650508258 # Simulator tick rate (ticks/s) -host_mem_usage 408644 # Number of bytes of host memory used -host_seconds 551.86 # Real time elapsed on the host -sim_insts 60593470 # Number of instructions simulated -sim_ops 72944147 # Number of ops (including micro ops) simulated +host_inst_rate 108919 # Simulator instruction rate (inst/s) +host_op_rate 131120 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4613194748 # Simulator tick rate (ticks/s) +host_mem_usage 411228 # Number of bytes of host memory used +host_seconds 556.32 # Real time elapsed on the host +sim_insts 60593541 # Number of instructions simulated +sim_ops 72944224 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 256 # Number of bytes read from this memory @@ -26,119 +26,119 @@ system.realview.nvmem.bw_inst_read::total 100 # I system.realview.nvmem.bw_total::cpu.inst 100 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 100 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1664 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10079960 # Number of bytes read from this memory -system.physmem.bytes_read::total 131191960 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1001344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1001344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3811328 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 10080024 # Number of bytes read from this memory +system.physmem.bytes_read::total 131192344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1001408 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1001408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3810496 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6827400 # Number of bytes written to this memory +system.physmem.bytes_written::total 6826568 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 26 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 157525 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15296364 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59552 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 157526 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15296370 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59539 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813570 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47190103 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813557 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47190748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3927605 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51118281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 390169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 390169 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1485065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.inst 1175197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2660262 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1485065 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47190103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3927684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51119130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 390199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 390199 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1484761 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.inst 1175213 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2659974 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1484761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47190748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5102802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53778543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15296364 # Number of read requests accepted -system.physmem.writeReqs 813570 # Number of write requests accepted -system.physmem.readBursts 15296364 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813570 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 978868736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 98560 # Total number of bytes read from write queue -system.physmem.bytesWritten 6836224 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131191960 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6827400 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1540 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706728 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4670 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955903 # Per bank write bursts -system.physmem.perBankRdBursts::1 955584 # Per bank write bursts +system.physmem.bw_total::cpu.inst 5102897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53779104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15296370 # Number of read requests accepted +system.physmem.writeReqs 813557 # Number of write requests accepted +system.physmem.readBursts 15296370 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 978862336 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 105344 # Total number of bytes read from write queue +system.physmem.bytesWritten 6837568 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131192344 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6826568 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1646 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706692 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4678 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 955907 # Per bank write bursts +system.physmem.perBankRdBursts::1 955585 # Per bank write bursts system.physmem.perBankRdBursts::2 955711 # Per bank write bursts -system.physmem.perBankRdBursts::3 955912 # Per bank write bursts -system.physmem.perBankRdBursts::4 957606 # Per bank write bursts -system.physmem.perBankRdBursts::5 955733 # Per bank write bursts -system.physmem.perBankRdBursts::6 955604 # Per bank write bursts -system.physmem.perBankRdBursts::7 955438 # Per bank write bursts -system.physmem.perBankRdBursts::8 956293 # Per bank write bursts -system.physmem.perBankRdBursts::9 955954 # Per bank write bursts -system.physmem.perBankRdBursts::10 955536 # Per bank write bursts -system.physmem.perBankRdBursts::11 955097 # Per bank write bursts -system.physmem.perBankRdBursts::12 956286 # Per bank write bursts -system.physmem.perBankRdBursts::13 955995 # Per bank write bursts -system.physmem.perBankRdBursts::14 956150 # Per bank write bursts -system.physmem.perBankRdBursts::15 956022 # Per bank write bursts -system.physmem.perBankWrBursts::0 6610 # Per bank write bursts -system.physmem.perBankWrBursts::1 6419 # Per bank write bursts -system.physmem.perBankWrBursts::2 6537 # Per bank write bursts -system.physmem.perBankWrBursts::3 6577 # Per bank write bursts -system.physmem.perBankWrBursts::4 6482 # Per bank write bursts -system.physmem.perBankWrBursts::5 6744 # Per bank write bursts -system.physmem.perBankWrBursts::6 6779 # Per bank write bursts -system.physmem.perBankWrBursts::7 6682 # Per bank write bursts -system.physmem.perBankWrBursts::8 7031 # Per bank write bursts -system.physmem.perBankWrBursts::9 6794 # Per bank write bursts -system.physmem.perBankWrBursts::10 6476 # Per bank write bursts -system.physmem.perBankWrBursts::11 6093 # Per bank write bursts -system.physmem.perBankWrBursts::12 7096 # Per bank write bursts -system.physmem.perBankWrBursts::13 6664 # Per bank write bursts -system.physmem.perBankWrBursts::14 6987 # Per bank write bursts -system.physmem.perBankWrBursts::15 6845 # Per bank write bursts +system.physmem.perBankRdBursts::3 955918 # Per bank write bursts +system.physmem.perBankRdBursts::4 957666 # Per bank write bursts +system.physmem.perBankRdBursts::5 955713 # Per bank write bursts +system.physmem.perBankRdBursts::6 955586 # Per bank write bursts +system.physmem.perBankRdBursts::7 955417 # Per bank write bursts +system.physmem.perBankRdBursts::8 956298 # Per bank write bursts +system.physmem.perBankRdBursts::9 955963 # Per bank write bursts +system.physmem.perBankRdBursts::10 955537 # Per bank write bursts +system.physmem.perBankRdBursts::11 955091 # Per bank write bursts +system.physmem.perBankRdBursts::12 956282 # Per bank write bursts +system.physmem.perBankRdBursts::13 955994 # Per bank write bursts +system.physmem.perBankRdBursts::14 956147 # Per bank write bursts +system.physmem.perBankRdBursts::15 955909 # Per bank write bursts +system.physmem.perBankWrBursts::0 6629 # Per bank write bursts +system.physmem.perBankWrBursts::1 6411 # Per bank write bursts +system.physmem.perBankWrBursts::2 6529 # Per bank write bursts +system.physmem.perBankWrBursts::3 6576 # Per bank write bursts +system.physmem.perBankWrBursts::4 6489 # Per bank write bursts +system.physmem.perBankWrBursts::5 6741 # Per bank write bursts +system.physmem.perBankWrBursts::6 6778 # Per bank write bursts +system.physmem.perBankWrBursts::7 6680 # Per bank write bursts +system.physmem.perBankWrBursts::8 7055 # Per bank write bursts +system.physmem.perBankWrBursts::9 6798 # Per bank write bursts +system.physmem.perBankWrBursts::10 6471 # Per bank write bursts +system.physmem.perBankWrBursts::11 6090 # Per bank write bursts +system.physmem.perBankWrBursts::12 7091 # Per bank write bursts +system.physmem.perBankWrBursts::13 6663 # Per bank write bursts +system.physmem.perBankWrBursts::14 6989 # Per bank write bursts +system.physmem.perBankWrBursts::15 6847 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2566437420000 # Total gap between requests +system.physmem.totGap 2566402308000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 157520 # Read request sizes (log2) +system.physmem.readPktSize::6 157526 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59552 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1111382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 958419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 963594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1074014 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973771 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1037292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691805 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2600171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3390697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 109522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19262 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59539 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1111407 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 958360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 963566 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1076065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1039000 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2689873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2594671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3384839 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 130586 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 112191 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 100054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18516 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 177 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -167,25 +167,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6205 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 6203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -216,44 +216,47 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1014534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.583959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.812030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 204.103928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21965 2.17% 2.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22634 2.23% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8771 0.86% 5.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2477 0.24% 5.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2600 0.26% 5.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1707 0.17% 5.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8766 0.86% 6.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1031 0.10% 6.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 944583 93.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1014534 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6199 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2467.302629 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 115861.516346 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6194 99.92% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6199 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6199 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.231166 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.203067 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.975146 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2381 38.41% 38.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 18 0.29% 38.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3787 61.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 12 0.19% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6199 # Writes before turning the bus around for reads -system.physmem.totQLat 394563558000 # Total ticks spent queuing -system.physmem.totMemAccLat 681341508000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76474120000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25797.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1014578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.536840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 905.616961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 204.240777 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22129 2.18% 2.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22531 2.22% 4.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8793 0.87% 5.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2465 0.24% 5.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2547 0.25% 5.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1763 0.17% 5.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8722 0.86% 6.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 969 0.10% 6.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 944659 93.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1014578 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6201 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2466.490405 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 89690.748368 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6195 99.90% 99.90% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6.02931e+06-6.29146e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6201 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6201 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.228995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.200624 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.980358 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2397 38.66% 38.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.21% 38.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3771 60.81% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 16 0.26% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6201 # Writes before turning the bus around for reads +system.physmem.totQLat 395011426750 # Total ticks spent queuing +system.physmem.totMemAccLat 681787501750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76473620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25826.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44547.20 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44576.65 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.66 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.12 # Average system read bandwidth in MiByte/s @@ -262,62 +265,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.00 # Data bus utilization in percentage system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.61 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.40 # Average write queue length when enqueuing -system.physmem.readRowHits 14297661 # Number of row buffer hits during reads -system.physmem.writeRowHits 89445 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.27 # Average write queue length when enqueuing +system.physmem.readRowHits 14297539 # Number of row buffer hits during reads +system.physmem.writeRowHits 89444 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.72 # Row buffer hit rate for writes -system.physmem.avgGap 159307.76 # Average gap between requests +system.physmem.writeRowHitRate 83.70 # Row buffer hit rate for writes +system.physmem.avgGap 159305.64 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2209628504250 # Time in different power states -system.physmem.memoryStateTime::REF 85698860000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2209544766500 # Time in different power states +system.physmem.memoryStateTime::REF 85697820000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 271106544500 # Time in different power states +system.physmem.memoryStateTime::ACT 271160177250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54713053 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16348871 # Transaction distribution -system.membus.trans_dist::ReadResp 16348871 # Transaction distribution +system.membus.trans_dist::ReadReq 16348869 # Transaction distribution +system.membus.trans_dist::ReadResp 16348869 # Transaction distribution system.membus.trans_dist::WriteReq 763365 # Transaction distribution system.membus.trans_dist::WriteResp 763365 # Transaction distribution -system.membus.trans_dist::Writeback 59552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4670 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4670 # Transaction distribution -system.membus.trans_dist::ReadExReq 131585 # Transaction distribution -system.membus.trans_dist::ReadExResp 131585 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383068 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 59539 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4678 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4678 # Transaction distribution +system.membus.trans_dist::ReadExReq 131592 # Transaction distribution +system.membus.trans_dist::ReadExResp 131592 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383066 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 8 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3800 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892024 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278902 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1892039 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4278915 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34556534 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390502 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908832 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19307194 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140417722 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140417722 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1781248000 # Layer occupancy (ticks) +system.membus.pkt_count::total 34556547 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390498 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16908384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19306742 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140417270 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 219423 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 219423 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 219423 # Request fanout histogram +system.membus.reqLayer0.occupancy 1783264500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 6000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3519500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3414000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17618629000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17618330500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4827707725 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4827152764 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37448813750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37437958000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -325,13 +337,12 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48121550 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322172 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322172 # Transaction distribution +system.iobus.trans_dist::ReadReq 16322171 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322171 # Transaction distribution system.iobus.trans_dist::WriteReq 8178 # Transaction distribution system.iobus.trans_dist::WriteResp 8178 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 524 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -353,41 +364,40 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383068 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383066 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660700 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390502 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501030 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501030 # Total data (bytes) +system.iobus.pkt_count::total 32660698 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15884 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390498 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123501026 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3976000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 524000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -431,22 +441,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374890000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374888000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38181688250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38185527000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 12541574 # Number of BP lookups -system.cpu.branchPred.condPredicted 9090690 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1061681 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8536244 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6183587 # Number of BTB hits +system.cpu.branchPred.lookups 12550628 # Number of BP lookups +system.cpu.branchPred.condPredicted 9093116 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1061685 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8575859 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6183324 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.439202 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1558068 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 139509 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.101512 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1560078 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 139853 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -470,25 +480,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 13629654 # DTB read hits -system.cpu.dtb.read_misses 33608 # DTB read misses -system.cpu.dtb.write_hits 11376786 # DTB write hits -system.cpu.dtb.write_misses 3775 # DTB write misses +system.cpu.dtb.read_hits 13629467 # DTB read hits +system.cpu.dtb.read_misses 33605 # DTB read misses +system.cpu.dtb.write_hits 11376627 # DTB write hits +system.cpu.dtb.write_misses 3703 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3449 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1586 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 251 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3447 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1539 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 252 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 593 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 13663262 # DTB read accesses -system.cpu.dtb.write_accesses 11380561 # DTB write accesses +system.cpu.dtb.read_accesses 13663072 # DTB read accesses +system.cpu.dtb.write_accesses 11380330 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 25006440 # DTB hits -system.cpu.dtb.misses 37383 # DTB misses -system.cpu.dtb.accesses 25043823 # DTB accesses +system.cpu.dtb.hits 25006094 # DTB hits +system.cpu.dtb.misses 37308 # DTB misses +system.cpu.dtb.accesses 25043402 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -510,8 +520,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 22903214 # ITB inst hits -system.cpu.itb.inst_misses 9061 # ITB inst misses +system.cpu.itb.inst_hits 22908933 # ITB inst hits +system.cpu.itb.inst_misses 9079 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -520,84 +530,84 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2388 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2384 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 5760 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 5702 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 22912275 # ITB inst accesses -system.cpu.itb.hits 22903214 # DTB hits -system.cpu.itb.misses 9061 # DTB misses -system.cpu.itb.accesses 22912275 # DTB accesses -system.cpu.numCycles 572663270 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 22918012 # ITB inst accesses +system.cpu.itb.hits 22908933 # DTB hits +system.cpu.itb.misses 9079 # DTB misses +system.cpu.itb.accesses 22918012 # DTB accesses +system.cpu.numCycles 572551547 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60593470 # Number of instructions committed -system.cpu.committedOps 72944147 # Number of ops (including micro ops) committed -system.cpu.discardedOps 3225433 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 60593541 # Number of instructions committed +system.cpu.committedOps 72944224 # Number of ops (including micro ops) committed +system.cpu.discardedOps 3228444 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 77492 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 4562060973 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 9.450907 # CPI: cycles per instruction -system.cpu.ipc 0.105810 # IPC: instructions per cycle +system.cpu.quiesceCycles 4562038068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 9.449052 # CPI: cycles per instruction +system.cpu.ipc 0.105831 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82978 # number of quiesce instructions executed -system.cpu.tickCycles 466702382 # Number of cycles that the object actually ticked -system.cpu.idleCycles 105960888 # Total number of cycles that the object has spent stopped -system.cpu.icache.tags.replacements 1529303 # number of replacements -system.cpu.icache.tags.tagsinuse 511.463660 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 21367406 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1529815 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 13.967314 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 9992606000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.463660 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998952 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998952 # Average percentage of cache occupancy +system.cpu.tickCycles 466653116 # Number of cycles that the object actually ticked +system.cpu.idleCycles 105898431 # Total number of cycles that the object has spent stopped +system.cpu.icache.tags.replacements 1529478 # number of replacements +system.cpu.icache.tags.tagsinuse 511.463685 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 21373010 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1529990 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 13.969379 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 9990881000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.463685 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998953 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998953 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 24427037 # Number of tag accesses -system.cpu.icache.tags.data_accesses 24427037 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 21367406 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 21367406 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 21367406 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 21367406 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 21367406 # number of overall hits -system.cpu.icache.overall_hits::total 21367406 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1529816 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1529816 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1529816 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1529816 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1529816 # number of overall misses -system.cpu.icache.overall_misses::total 1529816 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20677210137 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20677210137 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20677210137 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20677210137 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20677210137 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20677210137 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22897222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22897222 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22897222 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22897222 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22897222 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22897222 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066812 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.066812 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.066812 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.066812 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.066812 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.066812 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13516.141900 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13516.141900 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13516.141900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13516.141900 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13516.141900 # average overall miss latency +system.cpu.icache.tags.tag_accesses 24432991 # Number of tag accesses +system.cpu.icache.tags.data_accesses 24432991 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 21373010 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 21373010 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 21373010 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 21373010 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 21373010 # number of overall hits +system.cpu.icache.overall_hits::total 21373010 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1529991 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1529991 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1529991 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1529991 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1529991 # number of overall misses +system.cpu.icache.overall_misses::total 1529991 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20681368889 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20681368889 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20681368889 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20681368889 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20681368889 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20681368889 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22903001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22903001 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22903001 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22903001 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22903001 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22903001 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.066803 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.066803 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.066803 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.066803 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.066803 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13517.314082 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13517.314082 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13517.314082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13517.314082 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13517.314082 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -606,198 +616,211 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529816 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1529816 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1529816 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1529816 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1529816 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1529816 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17611902863 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17611902863 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17611902863 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17611902863 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17611902863 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17611902863 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1529991 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1529991 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1529991 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1529991 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1529991 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1529991 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17615727111 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17615727111 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17615727111 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17615727111 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17615727111 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17615727111 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 172140750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 172140750 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 172140750 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 172140750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066812 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.066812 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066812 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.066812 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11512.432125 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11512.432125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11512.432125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11512.432125 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.066803 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.066803 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.066803 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.066803 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11513.614859 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11513.614859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11513.614859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11513.614859 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.throughput 71285625 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3182019 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3182018 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3182062 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3182061 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763365 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763365 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 600964 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2972 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 247467 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 247467 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3062398 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5774016 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 28971 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 100817 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8966202 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 97936512 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84584698 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43908 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 166616 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 182731734 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 182731734 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 218488 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3381194945 # Layer occupancy (ticks) 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histogram +system.cpu.toL2Bus.snoop_fanout::total 2846983 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3381152937 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2301585887 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2301840639 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2547997212 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2547807667 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 18000487 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 18027487 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 59164999 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 59116998 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.l2cache.tags.replacements 65085 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51558.734735 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2407104 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 130473 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.449058 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2524856942500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36497.819876 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.059887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 65091 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51567.943403 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2406935 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 130479 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 18.446915 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2524835361000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36492.360835 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 17.402377 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000576 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 15046.854396 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.556913 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000215 # Average percentage of cache occupancy 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Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 15 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65373 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2560 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6585 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56117 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.997528 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 22967155 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 22967155 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 41633 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10975 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1892880 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1945488 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 600964 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 600964 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 85 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2561 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6578 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56121 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000229 # Percentage of cache occupancy per task id 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(read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10949 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2007080 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2059437 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 41408 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10949 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2007080 # number of overall hits +system.cpu.l2cache.overall_hits::total 2059437 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 26 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 23661 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23684 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.inst 2947 # number of UpgradeReq misses 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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012306 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.011993 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.991611 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991611 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.538731 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.538731 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.070802 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000628 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000183 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.072503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.070802 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59377.532638 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59383.008681 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.339328 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.339328 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57425.064310 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57425.064310 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59536.133723 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59544.772169 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10001.338409 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.338409 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57434.245756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57434.245756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65238.095238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67153.846154 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57718.643869 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57719.711088 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57750.210152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57751.828680 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -891,86 +914,86 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 635561 # number of replacements +system.cpu.dcache.tags.replacements 635446 # number of replacements system.cpu.dcache.tags.tagsinuse 511.959259 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21828853 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 636073 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 34.318157 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21828831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 635958 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 34.324328 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 227074250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.inst 511.959259 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91724261 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91724261 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 11595405 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11595405 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 9746069 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9746069 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236744 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236744 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 91723842 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91723842 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 11595412 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11595412 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 9746012 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9746012 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 236764 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236764 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.inst 247613 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247613 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 21341474 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21341474 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 21341474 # number of overall hits -system.cpu.dcache.overall_hits::total 21341474 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 458732 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 458732 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 476614 # number of WriteReq misses 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number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 29181049443 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 12054069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12054069 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 10222675 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222675 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 247614 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 247614 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.inst 247613 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 247613 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 22276820 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 22276820 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 22276820 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22276820 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038056 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.038056 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046623 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.046623 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043899 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043899 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.inst 0.041987 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.041987 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.inst 0.041987 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.041987 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15135.571388 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15135.571388 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46644.860424 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 46644.860424 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13968.261270 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13968.261270 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31191.414129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31191.414129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31191.414129 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.inst 22276744 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22276744 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.inst 22276744 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22276744 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.038050 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.038050 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.046628 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046628 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.043818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043818 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.inst 0.041986 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.041986 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.inst 0.041986 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.041986 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 15147.785129 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15147.785129 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 46643.879972 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46643.879972 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 13990.368664 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13990.368664 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31199.000816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.inst 31199.000816 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31199.000816 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -979,64 +1002,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 600964 # number of writebacks -system.cpu.dcache.writebacks::total 600964 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80923 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80923 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226176 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 226176 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 72 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 72 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.inst 307099 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 307099 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.inst 307099 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 307099 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377809 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 377809 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250438 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 250438 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10798 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 10798 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.inst 628247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 628247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.inst 628247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 628247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4823958811 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4823958811 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10813361832 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10813361832 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129211000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129211000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15637320643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 15637320643 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15637320643 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15637320643 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182632094750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182632094750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058171145 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058171145 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208690265895 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 208690265895 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031343 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031343 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 600919 # number of writebacks +system.cpu.dcache.writebacks::total 600919 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 80937 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 80937 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 226224 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 226224 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.inst 71 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 71 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.inst 307161 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 307161 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.inst 307161 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 307161 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 377720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 377720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 250439 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250439 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst 10779 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 10779 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.inst 628159 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 628159 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.inst 628159 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 628159 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 4824316311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4824316311 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 10814527330 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10814527330 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 129220000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 129220000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 15638843641 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 15638843641 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 15638843641 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15638843641 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 182633838500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182633838500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 26058035692 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26058035692 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 208691874192 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 208691874192 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.031335 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.031335 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.024498 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024498 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043608 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043608 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.028202 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028202 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028202 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12768.247477 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12768.247477 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43177.799823 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43177.799823 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11966.197444 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11966.197444 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24890.402410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24890.402410 # average overall mshr miss latency +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.043531 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.043531 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.028198 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.028198 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028198 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12772.202454 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12772.202454 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 43182.281234 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43182.281234 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 11988.125058 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11988.125058 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 24896.313897 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24896.313897 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -1060,10 +1083,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736623648250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736623648250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736623648250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1737063641000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1737063641000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1737063641000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 05396d247..ffb671fcc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542203 # Number of seconds simulated -sim_ticks 2542202956000 # Number of ticks simulated -final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542157 # Number of seconds simulated +sim_ticks 2542156879500 # Number of ticks simulated +final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40853 # Simulator instruction rate (inst/s) -host_op_rate 49218 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1721973071 # Simulator tick rate (ticks/s) -host_mem_usage 411692 # Number of bytes of host memory used -host_seconds 1476.33 # Real time elapsed on the host -sim_insts 60311945 # Number of instructions simulated -sim_ops 72661478 # Number of ops (including micro ops) simulated +host_inst_rate 45011 # Simulator instruction rate (inst/s) +host_op_rate 54228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1897222602 # Simulator tick rate (ticks/s) +host_mem_usage 464684 # Number of bytes of host memory used +host_seconds 1339.94 # Real time elapsed on the host +sim_insts 60311972 # Number of instructions simulated +sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory @@ -28,95 +28,95 @@ system.realview.nvmem.bw_total::total 19 # To system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295608 # Number of read requests accepted system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::0 955787 # Per bank write bursts system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953003 # Per bank write bursts -system.physmem.perBankRdBursts::3 951059 # Per bank write bursts -system.physmem.perBankRdBursts::4 958601 # Per bank write bursts -system.physmem.perBankRdBursts::5 955602 # Per bank write bursts -system.physmem.perBankRdBursts::6 952653 # Per bank write bursts -system.physmem.perBankRdBursts::7 950407 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::2 953511 # Per bank write bursts +system.physmem.perBankRdBursts::3 951566 # Per bank write bursts +system.physmem.perBankRdBursts::4 958612 # Per bank write bursts +system.physmem.perBankRdBursts::5 955530 # Per bank write bursts +system.physmem.perBankRdBursts::6 953056 # Per bank write bursts +system.physmem.perBankRdBursts::7 951020 # Per bank write bursts +system.physmem.perBankRdBursts::8 956158 # Per bank write bursts system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952889 # Per bank write bursts -system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::10 952686 # Per bank write bursts +system.physmem.perBankRdBursts::11 950200 # Per bank write bursts system.physmem.perBankRdBursts::12 956166 # Per bank write bursts system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953918 # Per bank write bursts -system.physmem.perBankRdBursts::15 950940 # Per bank write bursts -system.physmem.perBankWrBursts::0 6546 # Per bank write bursts -system.physmem.perBankWrBursts::1 6352 # Per bank write bursts -system.physmem.perBankWrBursts::2 6488 # Per bank write bursts -system.physmem.perBankWrBursts::3 6518 # Per bank write bursts -system.physmem.perBankWrBursts::4 6421 # Per bank write bursts -system.physmem.perBankWrBursts::5 6701 # Per bank write bursts -system.physmem.perBankWrBursts::6 6665 # Per bank write bursts -system.physmem.perBankWrBursts::7 6611 # Per bank write bursts -system.physmem.perBankWrBursts::8 6966 # Per bank write bursts -system.physmem.perBankWrBursts::9 6759 # Per bank write bursts -system.physmem.perBankWrBursts::10 6421 # Per bank write bursts -system.physmem.perBankWrBursts::11 6055 # Per bank write bursts -system.physmem.perBankWrBursts::12 7037 # Per bank write bursts -system.physmem.perBankWrBursts::13 6645 # Per bank write bursts -system.physmem.perBankWrBursts::14 6920 # Per bank write bursts -system.physmem.perBankWrBursts::15 6806 # Per bank write bursts +system.physmem.perBankRdBursts::14 953812 # Per bank write bursts +system.physmem.perBankRdBursts::15 951254 # Per bank write bursts +system.physmem.perBankWrBursts::0 6556 # Per bank write bursts +system.physmem.perBankWrBursts::1 6344 # Per bank write bursts +system.physmem.perBankWrBursts::2 6481 # Per bank write bursts +system.physmem.perBankWrBursts::3 6512 # Per bank write bursts +system.physmem.perBankWrBursts::4 6422 # Per bank write bursts +system.physmem.perBankWrBursts::5 6709 # Per bank write bursts +system.physmem.perBankWrBursts::6 6691 # Per bank write bursts +system.physmem.perBankWrBursts::7 6631 # Per bank write bursts +system.physmem.perBankWrBursts::8 6968 # Per bank write bursts +system.physmem.perBankWrBursts::9 6764 # Per bank write bursts +system.physmem.perBankWrBursts::10 6424 # Per bank write bursts +system.physmem.perBankWrBursts::11 6068 # Per bank write bursts +system.physmem.perBankWrBursts::12 7033 # Per bank write bursts +system.physmem.perBankWrBursts::13 6638 # Per bank write bursts +system.physmem.perBankWrBursts::14 6915 # Per bank write bursts +system.physmem.perBankWrBursts::15 6799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542201638000 # Total gap between requests +system.physmem.totGap 2542155562500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153412 # Read request sizes (log2) +system.physmem.readPktSize::6 153413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) @@ -124,26 +124,26 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -171,28 +171,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -220,50 +220,53 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads -system.physmem.totQLat 395449280750 # Total ticks spent queuing -system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads +system.physmem.totQLat 395458190750 # Total ticks spent queuing +system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s @@ -271,62 +274,71 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing -system.physmem.readRowHits 14269193 # Number of row buffer hits during reads -system.physmem.writeRowHits 90708 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing +system.physmem.readRowHits 14271218 # Number of row buffer hits during reads +system.physmem.writeRowHits 90719 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes -system.physmem.avgGap 157821.19 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states -system.physmem.memoryStateTime::REF 84889480000 # Time in different power states +system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes +system.physmem.avgGap 157818.32 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states +system.physmem.memoryStateTime::REF 84888180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states +system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 55125441 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16348039 # Transaction distribution -system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::ReadReq 16348037 # Transaction distribution +system.membus.trans_dist::ReadResp 16348037 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution system.membus.trans_dist::Writeback 58488 # Transaction distribution system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131651 # Transaction distribution -system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.trans_dist::ReadExReq 131654 # Transaction distribution +system.membus.trans_dist::ReadExResp 131654 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140140058 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 216513 # Request fanout histogram +system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,7 +346,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48580309 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution @@ -366,34 +377,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383056 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501006 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) @@ -440,22 +450,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13201290 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits +system.cpu.branchPred.lookups 13200672 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +489,25 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 13156743 # DTB read hits -system.cpu.checker.dtb.read_misses 7321 # DTB read misses -system.cpu.checker.dtb.write_hits 11227340 # DTB write hits +system.cpu.checker.dtb.read_hits 13156766 # DTB read hits +system.cpu.checker.dtb.read_misses 7319 # DTB read misses +system.cpu.checker.dtb.write_hits 11227349 # DTB write hits system.cpu.checker.dtb.write_misses 2193 # DTB write misses system.cpu.checker.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.dtb.prefetch_faults 180 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 13164064 # DTB read accesses -system.cpu.checker.dtb.write_accesses 11229533 # DTB write accesses +system.cpu.checker.dtb.read_accesses 13164085 # DTB read accesses +system.cpu.checker.dtb.write_accesses 11229542 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 24384083 # DTB hits -system.cpu.checker.dtb.misses 9514 # DTB misses -system.cpu.checker.dtb.accesses 24393597 # DTB accesses +system.cpu.checker.dtb.hits 24384115 # DTB hits +system.cpu.checker.dtb.misses 9512 # DTB misses +system.cpu.checker.dtb.accesses 24393627 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,7 +529,7 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.inst_hits 61486079 # ITB inst hits +system.cpu.checker.itb.inst_hits 61486106 # ITB inst hits system.cpu.checker.itb.inst_misses 4473 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -536,11 +546,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 61490552 # ITB inst accesses -system.cpu.checker.itb.hits 61486079 # DTB hits +system.cpu.checker.itb.inst_accesses 61490579 # ITB inst accesses +system.cpu.checker.itb.hits 61486106 # DTB hits system.cpu.checker.itb.misses 4473 # DTB misses -system.cpu.checker.itb.accesses 61490552 # DTB accesses -system.cpu.checker.numCycles 72947431 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 61490579 # DTB accesses +system.cpu.checker.numCycles 72947471 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits @@ -566,25 +576,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31642294 # DTB read hits -system.cpu.dtb.read_misses 39524 # DTB read misses -system.cpu.dtb.write_hits 11381361 # DTB write hits -system.cpu.dtb.write_misses 10135 # DTB write misses +system.cpu.dtb.read_hits 31644036 # DTB read hits +system.cpu.dtb.read_misses 39518 # DTB read misses +system.cpu.dtb.write_hits 11381434 # DTB write hits +system.cpu.dtb.write_misses 10146 # DTB write misses system.cpu.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31681818 # DTB read accesses -system.cpu.dtb.write_accesses 11391496 # DTB write accesses +system.cpu.dtb.read_accesses 31683554 # DTB read accesses +system.cpu.dtb.write_accesses 11391580 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43023655 # DTB hits -system.cpu.dtb.misses 49659 # DTB misses -system.cpu.dtb.accesses 43073314 # DTB accesses +system.cpu.dtb.hits 43025470 # DTB hits +system.cpu.dtb.misses 49664 # DTB misses +system.cpu.dtb.accesses 43075134 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -606,8 +616,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24159481 # ITB inst hits -system.cpu.itb.inst_misses 10516 # ITB inst misses +system.cpu.itb.inst_hits 24158829 # ITB inst hits +system.cpu.itb.inst_misses 10513 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -616,98 +626,98 @@ system.cpu.itb.flush_tlb 4 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 2878 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 126 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169997 # ITB inst accesses -system.cpu.itb.hits 24159481 # DTB hits -system.cpu.itb.misses 10516 # DTB misses -system.cpu.itb.accesses 24169997 # DTB accesses -system.cpu.numCycles 499350041 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169342 # ITB inst accesses +system.cpu.itb.hits 24158829 # DTB hits +system.cpu.itb.misses 10513 # DTB misses +system.cpu.itb.accesses 24169342 # DTB accesses +system.cpu.numCycles 499362415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -715,44 +725,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued @@ -776,101 +786,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued -system.cpu.iq.rate 0.188050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued +system.cpu.iq.rate 0.188049 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176010 # number of nop insts executed -system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791342 # Number of branches executed -system.cpu.iew.exec_stores 11888889 # Number of stores executed -system.cpu.iew.exec_rate 0.186738 # Inst execution rate -system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35465784 # num instructions producing a value -system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value +system.cpu.iew.exec_nop 176011 # number of nop insts executed +system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791373 # Number of branches executed +system.cpu.iew.exec_stores 11888962 # Number of stores executed +system.cpu.iew.exec_rate 0.186737 # Inst execution rate +system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35461894 # num instructions producing a value +system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462326 # Number of instructions committed -system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462353 # Number of instructions committed +system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244569 # Number of memory references committed -system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.refs 25244590 # Number of memory references committed +system.cpu.commit.loads 13512938 # Number of loads committed system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308073 # Number of branches committed +system.cpu.commit.branches 10308077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction @@ -898,72 +908,89 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction -system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction +system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568287463 # The number of ROB reads -system.cpu.rob.rob_writes 154414560 # The number of ROB writes -system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311945 # Number of Instructions Simulated -system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116898 # number of integer regfile reads -system.cpu.int_regfile_writes 47012348 # number of integer regfile writes +system.cpu.rob.rob_reads 568215140 # The number of ROB reads +system.cpu.rob.rob_writes 154414029 # The number of ROB writes +system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311972 # Number of Instructions Simulated +system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116744 # number of integer regfile reads +system.cpu.int_regfile_writes 47012213 # number of integer regfile writes system.cpu.fp_regfile_reads 8305 # number of floating regfile reads system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320404209 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes -system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes -system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.cc_regfile_reads 320409321 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes +system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 26770 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::9 2266210 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) 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-system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses -system.cpu.icache.overall_misses::total 1005369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits +system.cpu.icache.overall_hits::total 23148830 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses +system.cpu.icache.overall_misses::total 1005344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13667748229 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13667748229 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13667748229 # number of demand (read+write) miss cycles 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demand accesses system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 960370 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 960370 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11288731510 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11288731510 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11288731510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11288731510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11288731510 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11288731510 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223034500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223034500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223034500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 223034500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039760 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.039760 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039760 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.039760 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11754.564918 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11754.564918 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11754.564918 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11754.564918 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 63302 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51128.734687 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1829071 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 128690 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.213000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2530789670500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37302.599889 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 6.814194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.replacements 63303 # number of replacements +system.cpu.l2cache.tags.tagsinuse 51126.923594 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1828959 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 128691 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 14.212019 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2530750696500 # Cycle when the warmup percentage was hit. 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60703.651317 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10010.969062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10010.969062 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57621.434968 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57621.434968 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1323,184 +1350,184 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 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MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses 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-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1524,16 +1551,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index b3c80425c..7c26dcd5b 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,192 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.621647 # Number of seconds simulated -sim_ticks 2621647051000 # Number of ticks simulated -final_tick 2621647051000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.607932 # Number of seconds simulated +sim_ticks 2607931908500 # Number of ticks simulated +final_tick 2607931908500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 56801 # Simulator instruction rate (inst/s) -host_op_rate 68443 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2377539464 # Simulator tick rate (ticks/s) -host_mem_usage 411700 # Number of bytes of host memory used -host_seconds 1102.67 # Real time elapsed on the host -sim_insts 62632896 # Number of instructions simulated -sim_ops 75470296 # Number of ops (including micro ops) simulated +host_inst_rate 43892 # Simulator instruction rate (inst/s) +host_op_rate 52863 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1823841209 # Simulator tick rate (ticks/s) +host_mem_usage 431084 # Number of bytes of host memory used +host_seconds 1429.91 # Real time elapsed on the host +sim_insts 62761278 # Number of instructions simulated +sim_ops 75589768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 128 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 176 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 128 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 176 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 67 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 67 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 67 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 516048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6568572 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 301968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2981560 # Number of bytes read from this memory -system.physmem.bytes_read::total 131479316 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 516048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 301968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 818016 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4189696 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 3029096 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 7218832 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 457724 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 4608960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 71568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 618744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5382208 # Number of bytes read from this memory +system.physmem.bytes_read::total 132372740 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 122112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 71568 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 193680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4391552 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory +system.physmem.bytes_written::total 7420688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10590 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 102693 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4761 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 46605 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15303475 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 65464 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 757274 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 822748 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46196351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 171 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 196841 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2505513 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 115183 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1137285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50151418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 196841 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 115183 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 312024 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1598116 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 1155417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2753548 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1598116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46196351 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 171 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 196841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3660931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 115183 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1137300 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 52904966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15303475 # Number of read requests accepted -system.physmem.writeReqs 822748 # Number of write requests accepted -system.physmem.readBursts 15303475 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 822748 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 977402304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2020096 # Total number of bytes read from write queue -system.physmem.bytesWritten 7239040 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131479316 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7218832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 31564 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709609 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12033 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 956536 # Per bank write bursts -system.physmem.perBankRdBursts::1 956505 # Per bank write bursts -system.physmem.perBankRdBursts::2 953083 # Per bank write bursts -system.physmem.perBankRdBursts::3 951219 # Per bank write bursts -system.physmem.perBankRdBursts::4 959451 # Per bank write bursts -system.physmem.perBankRdBursts::5 955886 # Per bank write bursts -system.physmem.perBankRdBursts::6 953593 # Per bank write bursts -system.physmem.perBankRdBursts::7 950807 # Per bank write bursts -system.physmem.perBankRdBursts::8 956024 # Per bank write bursts -system.physmem.perBankRdBursts::9 956507 # Per bank write bursts -system.physmem.perBankRdBursts::10 953309 # Per bank write bursts -system.physmem.perBankRdBursts::11 950948 # Per bank write bursts -system.physmem.perBankRdBursts::12 956403 # Per bank write bursts -system.physmem.perBankRdBursts::13 956390 # Per bank write bursts -system.physmem.perBankRdBursts::14 954120 # Per bank write bursts -system.physmem.perBankRdBursts::15 951130 # Per bank write bursts -system.physmem.perBankWrBursts::0 7301 # Per bank write bursts -system.physmem.perBankWrBursts::1 7301 # Per bank write bursts -system.physmem.perBankWrBursts::2 6635 # Per bank write bursts -system.physmem.perBankWrBursts::3 6826 # Per bank write bursts -system.physmem.perBankWrBursts::4 7245 # Per bank write bursts -system.physmem.perBankWrBursts::5 6961 # Per bank write bursts -system.physmem.perBankWrBursts::6 7187 # Per bank write bursts -system.physmem.perBankWrBursts::7 6869 # Per bank write bursts -system.physmem.perBankWrBursts::8 6823 # Per bank write bursts -system.physmem.perBankWrBursts::9 7301 # Per bank write bursts -system.physmem.perBankWrBursts::10 6956 # Per bank write bursts -system.physmem.perBankWrBursts::11 6738 # Per bank write bursts -system.physmem.perBankWrBursts::12 7232 # Per bank write bursts -system.physmem.perBankWrBursts::13 7102 # Per bank write bursts -system.physmem.perBankWrBursts::14 7378 # Per bank write bursts -system.physmem.perBankWrBursts::15 7255 # Per bank write bursts +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 4443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 7211 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 72015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1161 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9686 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 84097 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15317443 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 68618 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory +system.physmem.num_writes::total 825902 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46439298 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 46823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 175512 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1767285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 196 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27442 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 237255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 2063784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50757744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 46823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27442 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 74266 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1683921 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6519 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1154990 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2845430 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1683921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46439298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 46823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 182031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1767285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 27442 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1392245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 2063784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53603174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15317443 # Number of read requests accepted +system.physmem.writeReqs 825902 # Number of write requests accepted +system.physmem.readBursts 15317443 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 976329024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3987328 # Total number of bytes read from write queue +system.physmem.bytesWritten 7443968 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 132372740 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7420688 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 62302 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709563 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16003 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 957415 # Per bank write bursts +system.physmem.perBankRdBursts::1 954356 # Per bank write bursts +system.physmem.perBankRdBursts::2 951532 # Per bank write bursts +system.physmem.perBankRdBursts::3 951095 # Per bank write bursts +system.physmem.perBankRdBursts::4 960453 # Per bank write bursts +system.physmem.perBankRdBursts::5 954333 # Per bank write bursts +system.physmem.perBankRdBursts::6 950562 # Per bank write bursts +system.physmem.perBankRdBursts::7 950350 # Per bank write bursts +system.physmem.perBankRdBursts::8 957423 # Per bank write bursts +system.physmem.perBankRdBursts::9 955252 # Per bank write bursts +system.physmem.perBankRdBursts::10 950399 # Per bank write bursts +system.physmem.perBankRdBursts::11 949996 # Per bank write bursts +system.physmem.perBankRdBursts::12 957025 # Per bank write bursts +system.physmem.perBankRdBursts::13 954231 # Per bank write bursts +system.physmem.perBankRdBursts::14 950565 # Per bank write bursts +system.physmem.perBankRdBursts::15 950154 # Per bank write bursts +system.physmem.perBankWrBursts::0 7537 # Per bank write bursts +system.physmem.perBankWrBursts::1 7271 # Per bank write bursts +system.physmem.perBankWrBursts::2 7519 # Per bank write bursts +system.physmem.perBankWrBursts::3 7339 # Per bank write bursts +system.physmem.perBankWrBursts::4 7525 # Per bank write bursts +system.physmem.perBankWrBursts::5 7506 # Per bank write bursts +system.physmem.perBankWrBursts::6 7304 # Per bank write bursts +system.physmem.perBankWrBursts::7 7173 # Per bank write bursts +system.physmem.perBankWrBursts::8 7520 # Per bank write bursts +system.physmem.perBankWrBursts::9 7613 # Per bank write bursts +system.physmem.perBankWrBursts::10 6934 # Per bank write bursts +system.physmem.perBankWrBursts::11 6533 # Per bank write bursts +system.physmem.perBankWrBursts::12 7225 # Per bank write bursts +system.physmem.perBankWrBursts::13 7011 # Per bank write bursts +system.physmem.perBankWrBursts::14 7249 # Per bank write bursts +system.physmem.perBankWrBursts::15 7053 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2621645657000 # Total gap between requests +system.physmem.totGap 2607930021000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 15138841 # Read request sizes (log2) -system.physmem.readPktSize::4 3426 # Read request sizes (log2) +system.physmem.readPktSize::4 3437 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 161149 # Read request sizes (log2) +system.physmem.readPktSize::6 175106 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 65464 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1118217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 965108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965171 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1074431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973448 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1034951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2682221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2590422 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3372339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 127125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 110466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101918 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 97549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20170 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 19015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 68618 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1022635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1020084 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 981701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1092290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 979402 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1043990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2669652 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2569034 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3344990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 138441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 119851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 110072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 105368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18580 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 172 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 1 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see @@ -176,46 +202,46 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6732 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6856 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7574 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7768 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see @@ -225,558 +251,604 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1014826 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 970.256324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 901.955292 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 206.811149 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24748 2.44% 2.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20792 2.05% 4.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9109 0.90% 5.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2441 0.24% 5.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2631 0.26% 5.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1759 0.17% 6.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9074 0.89% 6.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1088 0.11% 7.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943184 92.94% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1014826 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2307.281009 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 96810.313262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6612 99.89% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 1 0.02% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 1 0.02% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 2 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.31072e+06-1.57286e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6619 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.088684 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.037372 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.359683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3686 55.69% 55.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 52 0.79% 56.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1827 27.60% 84.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 927 14.01% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 37 0.56% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 27 0.41% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 28 0.42% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.32% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.17% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6619 # Writes before turning the bus around for reads -system.physmem.totQLat 395207982750 # Total ticks spent queuing -system.physmem.totMemAccLat 681556314000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76359555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25878.10 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1020956 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.580205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 884.289338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 220.002398 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 33463 3.28% 3.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19295 1.89% 5.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8776 0.86% 6.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2662 0.26% 6.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3249 0.32% 6.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2138 0.21% 6.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8494 0.83% 7.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1074 0.11% 7.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941805 92.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1020956 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6723 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2269.096237 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 97829.440322 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6717 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 1 0.01% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.01% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.3593e+06-2.62144e+06 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7.34003e+06-7.60218e+06 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6723 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6723 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.300610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.224413 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.695658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3618 53.82% 53.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 52 0.77% 54.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1623 24.14% 78.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 981 14.59% 93.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 153 2.28% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 115 1.71% 97.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 65 0.97% 98.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 63 0.94% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 23 0.34% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 16 0.24% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6723 # Writes before turning the bus around for reads +system.physmem.totQLat 400005056750 # Total ticks spent queuing +system.physmem.totMemAccLat 686038950500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76275705000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26221.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44628.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 372.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.76 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.15 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 44971.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 374.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.85 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.76 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.85 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.93 # Data bus utilization in percentage -system.physmem.busUtilRead 2.91 # Data bus utilization in percentage for reads +system.physmem.busUtil 2.95 # Data bus utilization in percentage +system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.85 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.60 # Average write queue length when enqueuing -system.physmem.readRowHits 14274861 # Number of row buffer hits during reads -system.physmem.writeRowHits 95334 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes -system.physmem.avgGap 162570.35 # Average gap between requests -system.physmem.pageHitRate 93.40 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2271344460000 # Time in different power states -system.physmem.memoryStateTime::REF 87542520000 # Time in different power states +system.physmem.avgRdQLen 6.13 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.82 # Average write queue length when enqueuing +system.physmem.readRowHits 14262971 # Number of row buffer hits during reads +system.physmem.writeRowHits 87526 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.23 # Row buffer hit rate for writes +system.physmem.avgGap 161548.30 # Average gap between requests +system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2277790546750 # Time in different power states +system.physmem.memoryStateTime::REF 87084400000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262759227500 # Time in different power states +system.physmem.memoryStateTime::ACT 243051888250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 192 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 192 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 3 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 12 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 18 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 55 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 73 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 18 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 55 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 73 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 18 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 55 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 73 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 53827614 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16353736 # Transaction distribution -system.membus.trans_dist::ReadResp 16353736 # Transaction distribution -system.membus.trans_dist::WriteReq 768463 # Transaction distribution -system.membus.trans_dist::WriteResp 768463 # Transaction distribution -system.membus.trans_dist::Writeback 65464 # Transaction distribution -system.membus.trans_dist::UpgradeReq 28363 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 16887 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12033 # Transaction distribution -system.membus.trans_dist::ReadExReq 137713 # Transaction distribution -system.membus.trans_dist::ReadExResp 137251 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 24 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 10950 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 16496763 # Transaction distribution +system.membus.trans_dist::ReadResp 16496763 # Transaction distribution +system.membus.trans_dist::WriteReq 769202 # Transaction distribution +system.membus.trans_dist::WriteResp 769202 # Transaction distribution +system.membus.trans_dist::Writeback 68618 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58416 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 23667 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16003 # Transaction distribution +system.membus.trans_dist::ReadExReq 15703 # Transaction distribution +system.membus.trans_dist::ReadExResp 8933 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13898 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2058 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1967095 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4364477 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2045296 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4445638 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34642109 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2392641 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 192 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 21900 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4116 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17587620 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20006477 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 141117005 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 141117005 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1559281500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34723270 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 176 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4100 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18682900 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21107657 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 142218185 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 72850 # Total snoops (count) +system.membus.snoop_fanout::samples 332577 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 332577 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 332577 # Request fanout histogram +system.membus.reqLayer0.occupancy 1569259492 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 14500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 13500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9763000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11956494 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1786500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1552000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17605374000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17698783999 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4830238688 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5007965719 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37428300697 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37372928091 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 71035 # number of replacements -system.l2c.tags.tagsinuse 52844.560777 # Cycle average of tags in use -system.l2c.tags.total_refs 1830685 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 136207 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.440462 # Average number of references to valid blocks. +system.l2c.tags.replacements 91666 # number of replacements +system.l2c.tags.tagsinuse 54831.199714 # Cycle average of tags in use +system.l2c.tags.total_refs 387443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156491 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.475817 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37821.803984 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.739512 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000522 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5415.027395 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6377.582658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.953654 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2390.174334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 833.278718 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.577115 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000088 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082627 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.097314 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012715 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.806344 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3098 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8323 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53527 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994385 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18484845 # Number of tag accesses -system.l2c.tags.data_accesses 18484845 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20873 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5362 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 546777 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 243323 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 15709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4324 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 434561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 119239 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1390168 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 583269 # number of Writeback hits -system.l2c.Writeback_hits::total 583269 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 378 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1712 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 271 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 117 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 388 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 65538 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 44550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 110088 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20873 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5362 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 546777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 308861 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 15709 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4324 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 434561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 163789 # number of demand (read+write) hits -system.l2c.demand_hits::total 1500256 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20873 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5362 # number of overall hits -system.l2c.overall_hits::cpu0.inst 546777 # number of overall hits -system.l2c.overall_hits::cpu0.data 308861 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 15709 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4324 # number of overall hits -system.l2c.overall_hits::cpu1.inst 434561 # number of overall hits -system.l2c.overall_hits::cpu1.data 163789 # number of overall hits -system.l2c.overall_hits::total 1500256 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7230 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9897 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 4714 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2106 # number of ReadReq misses -system.l2c.ReadReq_misses::total 23958 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 4509 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3863 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8372 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 516 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 628 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1144 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 94130 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 45638 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 139768 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 8 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 104027 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 4714 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 47744 # number of demand (read+write) misses -system.l2c.demand_misses::total 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-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 83500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 334292999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 165107999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1756326995 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 11295015 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 12799954 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 24094969 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1793923 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1118952 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2912875 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6378706625 # number of ReadExReq miss cycles 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+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 178129250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13420217500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3278250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 170978784519 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184580409519 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.179629 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.217387 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.465266 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.715918 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.732854 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.722892 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.933921 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.828911 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.880100 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.686326 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.649656 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.665170 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.472592 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.025210 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.063830 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.182992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.499345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.045455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.129714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.333837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.529565 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.472592 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 64774.930654 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65283.704393 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 90817.681910 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10089.861430 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10100.279144 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10094.209896 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10088.643082 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10081.026959 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10084.966653 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 62046.338910 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62109.200118 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62081.758770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 52916.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 48333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 70895.342427 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 63280.719878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82781.009206 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75067.028986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63619.483682 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100574.459041 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 89335.537412 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -797,69 +869,53 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 57560286 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2682607 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2682607 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 768463 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 768463 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 583269 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 27558 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 17275 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44833 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 1 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 261997 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 261997 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1115277 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2956767 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 14518 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50368 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 879187 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 2909426 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 12099 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 38611 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7976253 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 35510400 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 53724619 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21456 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83524 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 28114656 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 29015778 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 17296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 62840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146550569 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146550569 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4352184 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4888594820 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2503079453 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2482730980 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 1650974 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1650974 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 769202 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 769202 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 213987 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 63464 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 24002 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 87466 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 23286 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 23286 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 760669 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4337396 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5098065 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 18146443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 24785598 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 42932041 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 177868 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 783993 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 783993 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 783993 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2614417508 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 1150691896 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2659939258 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9171959 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 29595779 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1980581418 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 2244583247 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer8.occupancy 7797450 # Layer occupancy (ticks) -system.toL2Bus.respLayer8.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer9.occupancy 22968355 # Layer occupancy (ticks) -system.toL2Bus.respLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 47108999 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322906 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322906 # Transaction distribution -system.iobus.trans_dist::WriteReq 8083 # Transaction distribution -system.iobus.trans_dist::WriteResp 8083 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30944 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8814 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 16322916 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322916 # Transaction distribution +system.iobus.trans_dist::WriteReq 8084 # Transaction distribution +system.iobus.trans_dist::WriteResp 8084 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8832 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1034 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1032 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 740 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -876,51 +932,50 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384346 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384368 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32661978 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40713 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 17628 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2392641 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123503169 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123503169 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21713000 # Layer occupancy (ticks) +system.iobus.pkt_count::total 32662000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17664 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2064 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 394 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123503205 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4413000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4422000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 523000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 522000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 440000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 442000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -954,21 +1009,21 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376263000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2376284000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38168032303 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38188943909 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 8682194 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6490987 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 415813 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 5217710 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4131218 # Number of BTB hits +system.cpu0.branchPred.lookups 6445077 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4515785 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 302094 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3732049 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2838132 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 79.176842 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 908190 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 19748 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.047555 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 777958 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 15130 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -992,25 +1047,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 10917771 # DTB read hits -system.cpu0.dtb.read_misses 23643 # DTB read misses -system.cpu0.dtb.write_hits 7767808 # DTB write hits -system.cpu0.dtb.write_misses 8146 # DTB write misses +system.cpu0.dtb.read_hits 6738270 # DTB read hits +system.cpu0.dtb.read_misses 20792 # DTB read misses +system.cpu0.dtb.write_hits 5108254 # DTB write hits +system.cpu0.dtb.write_misses 4938 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 163 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 270 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1733 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 361 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 194 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 598 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 10941414 # DTB read accesses -system.cpu0.dtb.write_accesses 7775954 # DTB write accesses +system.cpu0.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6759062 # DTB read accesses +system.cpu0.dtb.write_accesses 5113192 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 18685579 # DTB hits -system.cpu0.dtb.misses 31789 # DTB misses -system.cpu0.dtb.accesses 18717368 # DTB accesses +system.cpu0.dtb.hits 11846524 # DTB hits +system.cpu0.dtb.misses 25730 # DTB misses +system.cpu0.dtb.accesses 11872254 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1032,8 +1087,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 16449037 # ITB inst hits -system.cpu0.itb.inst_misses 5743 # ITB inst misses +system.cpu0.itb.inst_hits 11251934 # ITB inst hits +system.cpu0.itb.inst_misses 5844 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1042,593 +1097,996 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1206 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1215 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2114 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2392 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 16454780 # ITB inst accesses -system.cpu0.itb.hits 16449037 # DTB hits -system.cpu0.itb.misses 5743 # DTB misses -system.cpu0.itb.accesses 16454780 # DTB accesses -system.cpu0.numCycles 110984158 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 11257778 # ITB inst accesses +system.cpu0.itb.hits 11251934 # DTB hits +system.cpu0.itb.misses 5844 # DTB misses +system.cpu0.itb.accesses 11257778 # DTB accesses +system.cpu0.numCycles 70547986 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 29010417 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 51007104 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 8682194 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 5039408 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 76702951 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1090474 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 80643 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 23949 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 71996 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1961272 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 16450117 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 242573 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2510 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 108396478 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.561251 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.057421 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 4766943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 34365037 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6445077 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3616090 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61724532 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 827468 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 75473 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 31308 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 103372 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 2299403 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 9118 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 11252710 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 69213 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1641 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 69423883 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.597378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.081788 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 80471532 74.24% 74.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 9354408 8.63% 82.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 4228353 3.90% 86.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 14342185 13.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 50336190 72.51% 72.51% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 6591848 9.50% 82.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2607109 3.76% 85.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 9888736 14.24% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 108396478 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.078229 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.459589 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 24273364 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 59696324 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 21865637 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 2148424 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 412729 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1100967 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 134603 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56048449 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 1161275 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 412729 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 26181144 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 23163659 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 11818847 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 22001270 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 24818829 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 54863842 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 371818 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 4330145 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2622839 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 9842391 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 13156385 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 58083982 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 254404471 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 69151408 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3820 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 54276662 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 3807314 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 540800 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 442723 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4591136 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9492850 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 8297955 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 506397 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 589876 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53569882 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 859573 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 55433156 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 105167 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 2762956 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 5503873 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 84823 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 108396478 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.511393 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.864824 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 69423883 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.091357 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.487116 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 6423281 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 48508889 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 12244404 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1928072 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 319237 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 872011 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 96101 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 34918059 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 1200237 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 319237 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 8391286 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 22294228 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 11033133 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 12128468 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 15257531 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 33562016 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 347139 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 4725852 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2951017 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 10590659 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 2752771 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 34856617 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 154488080 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 39935090 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3818 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30135138 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4721470 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 454498 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 374192 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4720858 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 6116778 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5560819 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 585791 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 708239 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 32317524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 796272 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 32794597 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 169276 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 3620256 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 7615411 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 145849 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 69423883 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.472382 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.871380 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74367725 68.61% 68.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 17769290 16.39% 85.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 11558620 10.66% 95.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 4256755 3.93% 99.59% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 444079 0.41% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 50273243 72.41% 72.41% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9200980 13.25% 85.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 6622047 9.54% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2961360 4.27% 99.47% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 365822 0.53% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 431 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 108396478 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 69423883 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3788078 33.87% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 172 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.87% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 3595287 32.14% 66.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3801407 33.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2899348 33.55% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 364 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 33.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 2954493 34.19% 67.74% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 2788370 32.26% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 14948 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 35826739 64.63% 64.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 64782 0.12% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 64.77% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 722 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 64.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 11302035 20.39% 85.16% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 8223930 14.84% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 14544 0.04% 0.04% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 20241553 61.72% 61.77% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 42703 0.13% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 684 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.90% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 7058068 21.52% 83.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5437045 16.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 55433156 # Type of FU issued -system.cpu0.iq.rate 0.499469 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11184944 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.201774 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 230540772 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 57191232 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 52885161 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12129 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4604 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 32794597 # Type of FU issued +system.cpu0.iq.rate 0.464855 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 8642575 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.263537 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 143812961 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 36735702 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 31078347 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11966 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4590 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 3838 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 66595213 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7939 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 146965 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 41415013 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7615 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 165813 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 634189 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 503 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 3442 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 242149 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 774144 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 762 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 6359 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 332945 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 1082260 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 1003693 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 1087991 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 169554 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 412729 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7302695 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 6441595 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 54523303 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 319237 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 7637691 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 6668537 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 33216242 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9492850 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 8297955 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 524870 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 12318 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6420937 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 3442 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 134210 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 165432 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 299642 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 55026621 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 11133456 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 374843 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 6116778 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5560819 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 485296 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 10796 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6648479 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 6359 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 101328 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 128415 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 229743 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 32427250 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 6903411 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 342013 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 93848 # number of nop insts executed -system.cpu0.iew.exec_refs 19301977 # number of memory reference insts executed -system.cpu0.iew.exec_branches 7332190 # Number of branches executed -system.cpu0.iew.exec_stores 8168521 # Number of stores executed -system.cpu0.iew.exec_rate 0.495806 # Inst execution rate -system.cpu0.iew.wb_sent 54039254 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 52888999 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 25110485 # num instructions producing a value -system.cpu0.iew.wb_consumers 37735585 # num instructions consuming a value +system.cpu0.iew.exec_nop 102446 # number of nop insts executed +system.cpu0.iew.exec_refs 12283212 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4700114 # Number of branches executed +system.cpu0.iew.exec_stores 5379801 # Number of stores executed +system.cpu0.iew.exec_rate 0.459648 # Inst execution rate +system.cpu0.iew.wb_sent 32232102 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 31082185 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 15739944 # num instructions producing a value +system.cpu0.iew.wb_consumers 27168343 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.476545 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.665433 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.440582 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.579349 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 2480238 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 774750 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 283305 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 107840192 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.477624 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.224539 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 3250105 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 650423 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 207597 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 68788504 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.427377 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.179796 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 82912194 76.88% 76.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 14339479 13.30% 90.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 5152045 4.78% 94.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1572745 1.46% 96.42% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1370622 1.27% 97.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 690625 0.64% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 401555 0.37% 98.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 407085 0.38% 99.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 993842 0.92% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 54880088 79.78% 79.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7965099 11.58% 91.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2563469 3.73% 95.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1116854 1.62% 96.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 779155 1.13% 97.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 426783 0.62% 98.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 259327 0.38% 98.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 232321 0.34% 99.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 565408 0.82% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 107840192 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 43173906 # Number of instructions committed -system.cpu0.commit.committedOps 51507078 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 68788504 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24068410 # Number of instructions committed +system.cpu0.commit.committedOps 29398607 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 16914467 # Number of memory references committed -system.cpu0.commit.loads 8858661 # Number of loads committed -system.cpu0.commit.membars 263890 # Number of memory barriers committed -system.cpu0.commit.branches 7043091 # Number of branches committed +system.cpu0.commit.refs 10570507 # Number of memory references committed +system.cpu0.commit.loads 5342633 # Number of loads committed +system.cpu0.commit.membars 231974 # Number of memory barriers committed +system.cpu0.commit.branches 4351471 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 45505753 # Number of committed integer instructions. -system.cpu0.commit.function_calls 666034 # Number of function calls committed. +system.cpu0.commit.int_insts 25743783 # Number of committed integer instructions. +system.cpu0.commit.function_calls 499778 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 34530023 67.04% 67.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 61866 0.12% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 722 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8858661 17.20% 84.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 8055806 15.64% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 18787662 63.91% 63.91% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 39754 0.14% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 684 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.04% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 5342633 18.17% 82.22% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5227874 17.78% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51507078 # Class of committed instruction -system.cpu0.commit.bw_lim_events 993842 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 29398607 # Class of committed instruction +system.cpu0.commit.bw_lim_events 565408 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 159811836 # The number of ROB reads -system.cpu0.rob.rob_writes 108530018 # The number of ROB writes -system.cpu0.timesIdled 338876 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2587680 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5132257518 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 43093164 # Number of Instructions Simulated -system.cpu0.committedOps 51426336 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.575447 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.575447 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.388282 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.388282 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 67127966 # number of integer regfile reads -system.cpu0.int_regfile_writes 33211893 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3352 # number of floating regfile reads +system.cpu0.rob.rob_reads 99997744 # The number of ROB reads +system.cpu0.rob.rob_writes 65895627 # The number of ROB writes +system.cpu0.timesIdled 89184 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 1124103 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5145325170 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23987668 # Number of Instructions Simulated +system.cpu0.committedOps 29317865 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.941011 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.941011 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340019 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340019 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 37156240 # number of integer regfile reads +system.cpu0.int_regfile_writes 18851805 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads system.cpu0.fp_regfile_writes 840 # number of floating regfile writes -system.cpu0.cc_regfile_reads 191848471 # number of cc regfile reads -system.cpu0.cc_regfile_writes 22040987 # number of cc regfile writes -system.cpu0.misc_regfile_reads 169210728 # number of misc regfile reads -system.cpu0.misc_regfile_writes 593502 # number of misc regfile writes -system.cpu0.icache.tags.replacements 554010 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.387606 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 15866984 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 554522 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.613804 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 18806389250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.387606 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998804 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998804 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 113767432 # number of cc regfile reads +system.cpu0.cc_regfile_writes 12814569 # number of cc regfile writes +system.cpu0.misc_regfile_reads 112163009 # number of misc regfile reads +system.cpu0.misc_regfile_writes 502202 # number of misc regfile writes +system.cpu0.toL2Bus.trans_dist::ReadReq 900797 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 693938 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 228050 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 268938 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 56335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 24640 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 62766 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 29 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 133470 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 124418 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 651974 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1223749 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 16358 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 46407 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 1938488 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20698608 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 38615195 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 26900 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 80012 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 59420715 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 640729 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 1524410 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.372076 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.483359 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 957213 62.79% 62.79% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 567197 37.21% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 1524410 # Request fanout histogram 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511.545879 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 10915164 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 322628 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.832042 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6524367000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.545879 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999113 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999113 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 17001271 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 17001271 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 15866984 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 15866984 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 15866984 # number of demand (read+write) hits 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(read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8029558142 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 8029558142 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8029558142 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 16446745 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 16446745 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 16446745 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 16446745 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 16446745 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 16446745 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.035251 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.035251 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.035251 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.035251 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.035251 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.035251 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13849.772824 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13849.772824 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13849.772824 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13849.772824 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13849.772824 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 739 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 55 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.436364 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 22821148 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 22821148 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 10915164 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 10915164 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 10915164 # number of demand (read+write) hits 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(read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 2863305358 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 2863305358 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 2863305358 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 11249255 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 11249255 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 11249255 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 11249255 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 11249255 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 11249255 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029699 # miss rate for ReadReq accesses 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overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 177531 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 22346 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 7.944643 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 61.400000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 25235 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 25235 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 25235 # number of demand (read+write) MSHR hits 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MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 6629844046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6629844046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 6629844046 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6629844046 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 226658500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 226658500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 226658500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 226658500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033716 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033716 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033716 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033716 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11955.875912 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11955.875912 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11955.875912 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 11453 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 11453 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 11453 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 11453 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 11453 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 11453 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 322638 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 322638 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 322638 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 322638 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 322638 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 322638 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 2310628588 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 2310628588 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 2310628588 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 2310628588 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 2310628588 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 2310628588 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 272886999 # number of ReadReq MSHR uncacheable cycles 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7161.675277 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7161.675277 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7161.675277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 7161.675277 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 409126 # number of replacements -system.cpu0.dcache.tags.tagsinuse 483.194796 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 12942599 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 409638 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.595211 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 271704250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.194796 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943740 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.943740 # Average percentage of cache occupancy +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 3529222 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 247992 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 2979692 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86609 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 16144 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 198785 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 261906 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time 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occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 8912.820942 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.291283 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000710 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000066 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.044864 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.092678 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.543995 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.973597 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 7338 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # 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MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 8151036272 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 354005766 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 354005766 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 158485722 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 158485722 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 490000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 490000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 601346170 # 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+system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 181100759 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 1541770762 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 8151036272 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 9881463044 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 244240750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 13865359008 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 14109599758 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 1262027985 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 1262027985 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 244240750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 15127386993 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15371627743 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.233212 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.099984 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000022 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.749058 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.749058 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.945809 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.945809 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.190227 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.190227 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.115747 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.017197 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025279 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.018464 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.217821 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.407212 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 18880.994860 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20062.557340 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41005.520060 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17988.097866 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17988.097866 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14598.905859 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14598.905859 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 490000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 490000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 26536.612241 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26536.612241 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 21921.062745 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14548.694767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15002.941176 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 30406.440396 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 21274.900468 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41005.520060 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 35580.923973 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.tags.replacements 297335 # number of replacements +system.cpu0.dcache.tags.tagsinuse 469.059398 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9029469 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 297847 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.315796 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 284699500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 469.059398 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.916132 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.916132 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 346 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63030887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63030887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 8037454 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 8037454 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4509267 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4509267 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 46089 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 46089 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 156971 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 156971 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 159079 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 159079 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12546721 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12546721 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12592810 # number of overall hits -system.cpu0.dcache.overall_hits::total 12592810 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 406720 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 406720 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2221250 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2221250 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 92142 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 92142 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10979 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10979 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7659 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7659 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2627970 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2627970 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2720112 # number of overall misses -system.cpu0.dcache.overall_misses::total 2720112 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5668958645 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5668958645 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 107130503686 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 107130503686 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 114563996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 114563996 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 44413016 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 44413016 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 112799462331 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 112799462331 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 112799462331 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 112799462331 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8444174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8444174 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6730517 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6730517 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 138231 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 138231 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 167950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 167950 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 166738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 166738 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 15174691 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15174691 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 15312922 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15312922 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.048166 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.048166 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330027 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330027 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.666580 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.666580 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065371 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065371 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.045934 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.045934 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.173181 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.173181 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177635 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.177635 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.234277 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.234277 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48229.827208 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48229.827208 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10434.829766 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10434.829766 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5798.800888 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5798.800888 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 42922.659821 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 42922.659821 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41468.683029 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41468.683029 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 14275 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1041 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.712776 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 20887113 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 20887113 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4736171 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 4736171 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3900194 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3900194 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 45240 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 45240 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135351 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 135351 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 133505 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 133505 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8636365 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8636365 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8681605 # number of overall hits +system.cpu0.dcache.overall_hits::total 8681605 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 322447 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 322447 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 906986 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 906986 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 75027 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 75027 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 10798 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 10798 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 11479 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11479 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1229433 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1229433 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1304460 # number of overall misses +system.cpu0.dcache.overall_misses::total 1304460 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3662752641 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3662752641 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 13080008270 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 13080008270 # number of WriteReq miss cycles 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of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5058618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5058618 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4807180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4807180 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 120267 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 120267 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 146149 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 146149 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144984 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144984 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 9865798 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9865798 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9986065 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9986065 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063742 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063742 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.188673 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188673 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.623837 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.623837 # miss rate for SoftPFReq accesses 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+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14421.400408 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14421.400408 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16922.624560 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16922.624560 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23823.263699 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13618.278435 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13618.278435 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12835.012887 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12835.012887 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1895359 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 100025 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 18.948853 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 375988 # number of writebacks -system.cpu0.dcache.writebacks::total 375988 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 193747 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 193747 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 2045363 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 2045363 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1054 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1054 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2239110 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2239110 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2239110 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2239110 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212973 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 212973 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175887 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 175887 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 54623 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 54623 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9925 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7659 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7659 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 388860 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 388860 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 443483 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 443483 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2487825853 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2487825853 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7369362883 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7369362883 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1035896777 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1035896777 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 82981003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 82981003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 29093984 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 29093984 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9857188736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9857188736 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10893085513 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10893085513 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13737621002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13737621002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 26275689041 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26275689041 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 40013310043 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 40013310043 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.025221 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025221 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.026133 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.026133 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.395157 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.395157 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059095 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059095 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.045934 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.045934 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025626 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.025626 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028961 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028961 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11681.414325 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11681.414325 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41898.280618 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41898.280618 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18964.479743 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18964.479743 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8360.806348 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8360.806348 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3798.666144 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3798.666144 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 25348.939814 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25348.939814 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24562.577400 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24562.577400 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 228050 # number of writebacks +system.cpu0.dcache.writebacks::total 228050 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 162419 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 162419 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 762846 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 762846 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 1187 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1187 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 925265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 925265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 925265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 925265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 160028 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 160028 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 144140 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 144140 # number of WriteReq MSHR misses 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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 249287756 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 626000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 626000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 3810348363 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 3810348363 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 4518643858 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4518643858 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 14541407491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14541407491 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1345528496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345528496 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 15886935987 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 15886935987 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.031635 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.031635 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.029984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.029984 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.366884 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.366884 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065762 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.079174 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.079174 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.030831 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.030831 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.034878 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034878 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10356.119454 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10356.119454 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14937.416949 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14937.416949 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16052.386343 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16052.386343 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15303.662470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15303.662470 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21716.853036 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12527.117787 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12527.117787 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12973.722790 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12973.722790 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1636,15 +2094,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 5001209 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3530067 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 291977 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3184313 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2141032 # Number of BTB hits +system.cpu1.branchPred.lookups 9149866 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6786400 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 422129 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5825788 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4286605 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.236858 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 582225 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 13211 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.579832 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 927303 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 19424 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1668,25 +2126,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 21293354 # DTB read hits -system.cpu1.dtb.read_misses 17527 # DTB read misses -system.cpu1.dtb.write_hits 4063342 # DTB write hits -system.cpu1.dtb.write_misses 3266 # DTB write misses +system.cpu1.dtb.read_hits 25102636 # DTB read hits +system.cpu1.dtb.read_misses 30137 # DTB read misses +system.cpu1.dtb.write_hits 6841685 # DTB write hits +system.cpu1.dtb.write_misses 6769 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1908 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 789 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 274 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1912 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1186 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 224 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 694 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 21310881 # DTB read accesses -system.cpu1.dtb.write_accesses 4066608 # DTB write accesses +system.cpu1.dtb.perms_faults 731 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25132773 # DTB read accesses +system.cpu1.dtb.write_accesses 6848454 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 25356696 # DTB hits -system.cpu1.dtb.misses 20793 # DTB misses -system.cpu1.dtb.accesses 25377489 # DTB accesses +system.cpu1.dtb.hits 31944321 # DTB hits +system.cpu1.dtb.misses 36906 # DTB misses +system.cpu1.dtb.accesses 31981227 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1708,8 +2166,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8626509 # ITB inst hits -system.cpu1.itb.inst_misses 4363 # ITB inst misses +system.cpu1.itb.inst_hits 16803682 # ITB inst hits +system.cpu1.itb.inst_misses 6173 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1718,595 +2176,986 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1319 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2055 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2309 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8630872 # ITB inst accesses -system.cpu1.itb.hits 8626509 # DTB hits -system.cpu1.itb.misses 4363 # DTB misses -system.cpu1.itb.accesses 8630872 # DTB accesses -system.cpu1.numCycles 396849081 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16809855 # ITB inst accesses +system.cpu1.itb.hits 16803682 # DTB hits +system.cpu1.itb.misses 6173 # DTB misses +system.cpu1.itb.accesses 16809855 # DTB accesses +system.cpu1.numCycles 436917069 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18444788 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 25760845 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 5001209 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2723257 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 375027882 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 802688 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 60706 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 28139 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 75697 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1303305 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.CacheLines 8624270 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 181619 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 1774 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 395341861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.079415 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 0.442124 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 7779761 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 51586006 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9149866 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5213908 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 424935366 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 1119898 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 77514 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 41827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 113975 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2395843 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 15405 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 16801187 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 110293 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1839 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 435919640 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.141195 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 0.582401 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 380851246 96.33% 96.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4867429 1.23% 97.57% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2340779 0.59% 98.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7282407 1.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 407581344 93.50% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 9416514 2.16% 95.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4632400 1.06% 96.72% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 14289382 3.28% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 395341861 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.012602 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.064913 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 15111141 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 368322319 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9619404 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1988623 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 300374 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 680085 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102949 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 27336312 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 828595 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 300374 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16508550 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 196017158 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 17889321 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 9851688 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 154774770 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 26427025 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 243114 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 56891125 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 39780893 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 150628157 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2138867 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 27113530 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 124075273 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 31437770 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6241 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 24483458 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2630072 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 642693 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 559165 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 4862604 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 5657845 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 4330093 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 343073 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 498131 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 25260320 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 861912 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 41442639 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 78274 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1902061 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 3789747 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 92749 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 395341861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.104827 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.383209 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 435919640 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.020942 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.118068 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 9900868 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 404219752 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 17609153 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3776585 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 413282 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1053225 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 148821 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 53082842 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1693858 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 413282 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13042184 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 210392870 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 23473030 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 17900158 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 170698116 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51361658 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 445811 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 60462789 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 44486963 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 161544271 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5689953 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54453588 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 239756743 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 64654520 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6270 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 48767925 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 5685663 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 754764 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 650155 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9515727 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9671211 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7398216 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 539915 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 877439 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 49754499 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1063600 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 65146152 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 226823 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 4308815 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 9268536 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 164257 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 435919640 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.149445 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.502702 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 362283147 91.64% 91.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26570133 6.72% 98.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4792582 1.21% 99.57% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1496663 0.38% 99.95% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 199327 0.05% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 391740283 89.87% 89.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 28930464 6.64% 96.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 10221316 2.34% 98.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 4337467 1.00% 99.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 689895 0.16% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 215 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 395341861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 435919640 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1195141 5.96% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 685 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.96% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 16909984 84.32% 90.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1947822 9.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 4426779 17.51% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 691 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 17.51% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 17782110 70.33% 87.84% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3074512 12.16% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13868 0.03% 0.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 15563362 37.55% 37.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 33954 0.08% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1648 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 37.67% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 21553207 52.01% 89.68% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 4276600 10.32% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 14260 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 32351105 49.66% 49.68% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 60186 0.09% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.77% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1702 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.78% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 25491005 39.13% 88.91% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7227894 11.09% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 41442639 # Type of FU issued -system.cpu1.iq.rate 0.104429 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 20053632 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.483889 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 498337881 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 28019357 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 25018416 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 21164 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 7936 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6759 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 61468547 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 13856 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 72058 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 65146152 # Type of FU issued +system.cpu1.iq.rate 0.149104 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 25284092 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.388113 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 591701467 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 55128847 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 48339304 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 21392 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7974 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6777 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 90402329 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 13655 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 164874 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 455146 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 306 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3014 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 163146 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 922858 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 700 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9957 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 405915 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 15996057 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1487 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16016509 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 155340 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 300374 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 87167513 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 92299631 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 26204459 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 413282 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 90103879 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 101302025 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 50907640 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 5657845 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 4330093 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 630570 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9334 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 92232105 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3014 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 83298 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 118271 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 201569 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 41178523 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 21441390 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 243431 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 9671211 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7398216 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 775761 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 15322 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 101224655 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9957 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 133208 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 167801 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 301009 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 64655254 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25297716 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 454169 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 82227 # number of nop insts executed -system.cpu1.iew.exec_refs 25682989 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3899404 # Number of branches executed -system.cpu1.iew.exec_stores 4241599 # Number of stores executed -system.cpu1.iew.exec_rate 0.103764 # Inst execution rate -system.cpu1.iew.wb_sent 41086324 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 25025175 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 11348419 # num instructions producing a value -system.cpu1.iew.wb_consumers 16538487 # num instructions consuming a value +system.cpu1.iew.exec_nop 89541 # number of nop insts executed +system.cpu1.iew.exec_refs 32443779 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6846575 # Number of branches executed +system.cpu1.iew.exec_stores 7146063 # Number of stores executed +system.cpu1.iew.exec_rate 0.147981 # Inst execution rate +system.cpu1.iew.wb_sent 64439493 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 48346081 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25811466 # num instructions producing a value +system.cpu1.iew.wb_consumers 39458467 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.063060 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.686182 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.110653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.654143 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1702265 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 769163 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 191007 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 394940200 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.061056 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.422241 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 3859068 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899343 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 275462 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 435139005 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.106498 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.626723 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 381244473 96.53% 96.53% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 9114140 2.31% 98.84% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2236589 0.57% 99.41% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 955406 0.24% 99.65% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 446570 0.11% 99.76% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 403381 0.10% 99.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 181575 0.05% 99.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 97100 0.02% 99.93% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 260966 0.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 413392451 95.00% 95.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12955608 2.98% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 3521257 0.81% 98.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1360882 0.31% 99.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1313314 0.30% 99.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 777449 0.18% 99.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 559175 0.13% 99.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 305729 0.07% 99.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 953140 0.22% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 394940200 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 19609371 # Number of instructions committed -system.cpu1.commit.committedOps 24113599 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 435139005 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38843249 # Number of instructions committed +system.cpu1.commit.committedOps 46341542 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 9369646 # Number of memory references committed -system.cpu1.commit.loads 5202699 # Number of loads committed -system.cpu1.commit.membars 162322 # Number of memory barriers committed -system.cpu1.commit.branches 3698878 # Number of branches committed +system.cpu1.commit.refs 15740654 # Number of memory references committed +system.cpu1.commit.loads 8748353 # Number of loads committed +system.cpu1.commit.membars 195273 # Number of memory barriers committed +system.cpu1.commit.branches 6419002 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 21204966 # Number of committed integer instructions. -system.cpu1.commit.function_calls 385194 # Number of function calls committed. +system.cpu1.commit.int_insts 41058956 # Number of committed integer instructions. +system.cpu1.commit.function_calls 553431 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 14709151 61.00% 61.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 33154 0.14% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1648 0.01% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.14% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 5202699 21.58% 82.72% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 4166947 17.28% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 30541068 65.90% 65.90% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 58118 0.13% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1702 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.03% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 8748353 18.88% 84.91% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6992301 15.09% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 24113599 # Class of committed instruction -system.cpu1.commit.bw_lim_events 260966 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 46341542 # Class of committed instruction +system.cpu1.commit.bw_lim_events 953140 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 419589246 # The number of ROB reads -system.cpu1.rob.rob_writes 52032512 # The number of ROB writes -system.cpu1.timesIdled 248745 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1507220 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4845699469 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 19539732 # Number of Instructions Simulated -system.cpu1.committedOps 24043960 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 20.309853 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 20.309853 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.049237 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.049237 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 45343306 # number of integer regfile reads -system.cpu1.int_regfile_writes 15599183 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5046 # number of floating regfile reads +system.cpu1.rob.rob_reads 483317632 # The number of ROB reads +system.cpu1.rob.rob_writes 101136219 # The number of ROB writes +system.cpu1.timesIdled 117466 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 997429 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4778390126 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38773610 # Number of Instructions Simulated +system.cpu1.committedOps 46271903 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 11.268413 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 11.268413 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.088744 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.088744 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 76047297 # number of integer regfile reads +system.cpu1.int_regfile_writes 30995697 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4960 # number of floating regfile reads system.cpu1.fp_regfile_writes 2260 # number of floating regfile writes -system.cpu1.cc_regfile_reads 139131439 # number of cc regfile reads -system.cpu1.cc_regfile_writes 9348976 # number of cc regfile writes -system.cpu1.misc_regfile_reads 454367618 # number of misc regfile reads -system.cpu1.misc_regfile_writes 623445 # number of misc regfile writes -system.cpu1.icache.tags.replacements 439266 # number of replacements -system.cpu1.icache.tags.tagsinuse 497.815366 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 8166304 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 439778 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 18.569151 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 119618152250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 497.815366 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972296 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.972296 # Average percentage of cache occupancy +system.cpu1.cc_regfile_reads 220730482 # number of cc regfile reads +system.cpu1.cc_regfile_writes 19377985 # number of cc regfile writes +system.cpu1.misc_regfile_reads 520419201 # number of misc regfile reads +system.cpu1.misc_regfile_writes 723683 # number of misc regfile writes +system.cpu1.toL2Bus.trans_dist::ReadReq 2172606 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1978157 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 758384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 758384 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 291033 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 272197 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 56199 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 25233 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 54439 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 45 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 157045 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 149477 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1093505 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4944143 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17380 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 65233 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6120261 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 34983760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 51460526 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28972 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 118552 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86591810 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 595717 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1871452 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.290652 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.454063 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1327511 70.93% 70.93% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 543941 29.07% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1871452 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2995139487 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46865000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 820984463 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 2122961296 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 10148477 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 36069550 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.icache.tags.replacements 546235 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.934216 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16238797 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 546747 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 29.700752 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73709463000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.934216 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974481 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974481 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 509 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 9063984 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 9063984 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 8166304 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8166304 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8166304 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8166304 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8166304 # number of overall hits -system.cpu1.icache.overall_hits::total 8166304 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 457900 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 457900 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 457900 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 457900 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 457900 # number of overall misses -system.cpu1.icache.overall_misses::total 457900 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6264180115 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6264180115 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6264180115 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6264180115 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6264180115 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6264180115 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8624204 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8624204 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8624204 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8624204 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8624204 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8624204 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.053095 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.053095 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.053095 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.053095 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.053095 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.053095 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13680.236111 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13680.236111 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13680.236111 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13680.236111 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13680.236111 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 882 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 53 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.641509 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 34148852 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34148852 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16238797 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16238797 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16238797 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16238797 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16238797 # number of overall hits +system.cpu1.icache.overall_hits::total 16238797 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 562244 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 562244 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 562244 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 562244 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 562244 # number of overall misses +system.cpu1.icache.overall_misses::total 562244 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4743193454 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4743193454 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4743193454 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4743193454 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4743193454 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4743193454 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16801041 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16801041 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16801041 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16801041 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16801041 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16801041 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.033465 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.033465 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.033465 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.033465 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.033465 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.033465 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8436.183319 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8436.183319 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8436.183319 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8436.183319 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8436.183319 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 307905 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40708 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 7.563747 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18120 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 18120 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 18120 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 18120 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 18120 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 18120 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 439780 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 439780 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 439780 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 439780 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 439780 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 439780 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5188034078 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5188034078 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5188034078 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5188034078 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5188034078 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5188034078 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4304000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4304000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4304000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 4304000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.050994 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.050994 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.050994 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.050994 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11796.884983 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11796.884983 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11796.884983 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 15474 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 15474 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 15474 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 15474 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 15474 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 15474 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 546770 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 546770 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 546770 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 546770 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 546770 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 546770 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3839673113 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3839673113 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3839673113 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3839673113 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3839673113 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3839673113 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5117249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5117249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5117249 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 5117249 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032544 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.032544 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032544 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.032544 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7022.464863 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7022.464863 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7022.464863 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 227040 # number of replacements -system.cpu1.dcache.tags.tagsinuse 492.830733 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7082160 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 227406 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 31.143242 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 99092137500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 492.830733 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.962560 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.962560 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 366 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 32684037 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 32684037 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3792757 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3792757 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3094601 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3094601 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 14161 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 14161 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 75622 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 75622 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 75613 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 75613 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6887358 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6887358 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6901519 # number of overall hits -system.cpu1.dcache.overall_hits::total 6901519 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 187422 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 187422 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 806941 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 806941 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 41483 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 41483 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10414 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10414 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 9617 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 9617 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 994363 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 994363 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1035846 # number of overall misses -system.cpu1.dcache.overall_misses::total 1035846 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2444126213 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2444126213 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 27779707617 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 27779707617 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 86490246 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 86490246 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53209125 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53209125 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 14000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 14000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 30223833830 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 30223833830 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 30223833830 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 30223833830 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3980179 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3980179 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3901542 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3901542 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 55644 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 55644 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 86036 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 86036 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85230 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85230 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7881721 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7881721 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7937365 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7937365 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.047089 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.047089 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.206826 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.206826 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.745507 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.745507 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121042 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121042 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.112836 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.112836 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.126161 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.126161 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.130503 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.130503 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13040.764761 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13040.764761 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 34425.946404 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 34425.946404 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8305.189745 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8305.189745 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5532.819486 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5532.819486 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percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 8428 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 6994 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2154 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 2511 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3763 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2597 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1568 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2829 # Occupied blocks per task id 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7243 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 546605 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 257672 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 841158 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 291033 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 291033 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 22797 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 22797 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 14393 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 14393 # number of SCUpgradeReq accesses(hits+misses) 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accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7243 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 546605 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 405775 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 989261 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.012282 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.021814 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020785 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.235881 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.086384 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses 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21297.468354 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30318.631723 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 26532.579056 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27096.694741 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 17367.506752 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 17367.506752 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20309.226494 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20309.226494 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 596000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 596000 # average SCUpgradeFailReq miss latency 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HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 10843374528 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 344645957 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 344645957 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 188520557 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 188520557 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 996000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 996000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 690789082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 690789082 # number of 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1874848035 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 10843374528 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 12960562319 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4572000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 174823243259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 174827815259 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 29484635658 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 29484635658 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 4572000 # number of overall MSHR uncacheable cycles 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miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.296557 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16264.462810 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14359.872611 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27380.013562 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 19527.004189 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20461.895123 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 54258.108803 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16740.137799 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16740.137799 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14294.855702 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14294.855702 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 498000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 498000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29007.687999 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29007.687999 # average ReadExReq mshr miss latency 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miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 54258.108803 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 44177.911726 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 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percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940978 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 331 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.646484 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 27770563 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 27770563 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 7205629 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7205629 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4858222 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4858222 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 24502 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 24502 # number of SoftPFReq hits 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4296873688 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 15627489636 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 15627489636 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 254785499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 254785499 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 332075324 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 332075324 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1276000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1276000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 19924363324 # number of demand (read+write) miss cycles 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+system.cpu1.dcache.WriteReq_miss_rate::total 0.166045 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.659874 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.659874 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137111 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137111 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.133477 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.133477 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.099271 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.099271 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.102270 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.102270 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 11860.806536 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 11860.806536 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16155.817169 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16155.817169 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17036.810364 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17036.810364 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23068.796388 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23068.796388 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30395.171411 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 30395.171411 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29177.922037 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 29177.922037 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 4476 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 723 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 6.190871 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14985.535449 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14985.535449 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14468.254382 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14468.254382 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 4991 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 2160220 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 228 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 94010 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 21.890351 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 22.978619 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 207281 # number of writebacks -system.cpu1.dcache.writebacks::total 207281 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 70540 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 70540 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 693700 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 693700 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 500 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 500 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 764240 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 764240 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 764240 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 764240 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116882 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116882 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 113241 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 113241 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23891 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23891 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 9914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 9914 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9617 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 9617 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230123 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230123 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 254014 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 254014 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1203808322 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1203808322 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3988299754 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3988299754 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 341716536 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 341716536 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 60834504 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 60834504 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 33974875 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 33974875 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 12000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 12000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5192108076 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 5192108076 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5533824612 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5533824612 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168973544758 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168973544758 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 522517625 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 522517625 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 169496062383 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 169496062383 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.029366 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029366 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029025 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029025 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.429354 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.429354 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.115231 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.115231 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.112836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.112836 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029197 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.029197 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032002 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032002 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10299.347393 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10299.347393 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35219.573776 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35219.573776 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14303.149136 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14303.149136 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6136.221908 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6136.221908 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3532.793491 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3532.793491 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 291033 # number of writebacks +system.cpu1.dcache.writebacks::total 291033 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 148293 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 148293 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 797245 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 797245 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1426 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1426 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 945538 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 945538 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 945538 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 945538 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 213982 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 213982 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 170053 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 170053 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 30328 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 30328 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13529 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13529 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 14395 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 14395 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 384035 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 384035 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 414363 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 414363 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2231950081 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2231950081 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2569103752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2569103752 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 638180745 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 638180745 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 208910751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 208910751 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 302166676 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 302166676 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1220000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1220000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4801053833 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4801053833 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5439234578 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5439234578 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 183653885735 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183653885735 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 50893842775 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 50893842775 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 234547728510 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 234547728510 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028275 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.028275 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.029191 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.029191 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.421000 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.421000 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.124037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124037 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.133477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.133477 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028673 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028673 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030772 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030772 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10430.550612 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10430.550612 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15107.664975 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15107.664975 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21042.625462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21042.625462 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15441.699387 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15441.699387 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20991.085516 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20991.085516 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22562.317004 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22562.317004 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21785.510295 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21785.510295 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12501.604888 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12501.604888 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13126.738097 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13126.738097 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2330,18 +3179,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736665659303 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736665659303 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736665659303 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736182068909 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736182068909 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736182068909 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 52427 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 42962 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 40685 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 50554 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index e77a65365..8ecc8ed09 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,110 +1,110 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.542203 # Number of seconds simulated -sim_ticks 2542202956000 # Number of ticks simulated -final_tick 2542202956000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.542157 # Number of seconds simulated +sim_ticks 2542156879500 # Number of ticks simulated +final_tick 2542156879500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 47189 # Simulator instruction rate (inst/s) -host_op_rate 56852 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1989066585 # Simulator tick rate (ticks/s) -host_mem_usage 412724 # Number of bytes of host memory used -host_seconds 1278.09 # Real time elapsed on the host -sim_insts 60311945 # Number of instructions simulated -sim_ops 72661478 # Number of ops (including micro ops) simulated +host_inst_rate 53622 # Simulator instruction rate (inst/s) +host_op_rate 64601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2260157205 # Simulator tick rate (ticks/s) +host_mem_usage 463148 # Number of bytes of host memory used +host_seconds 1124.77 # Real time elapsed on the host +sim_insts 60311972 # Number of instructions simulated +sim_ops 72661518 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9072728 # Number of bytes read from this memory -system.physmem.bytes_read::total 130982664 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798576 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 798448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9072920 # Number of bytes read from this memory +system.physmem.bytes_read::total 130982728 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 798448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 798448 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 3743232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory system.physmem.bytes_written::total 6759304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 14991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141787 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15295607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 14989 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141790 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15295608 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 58488 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory system.physmem.num_writes::total 812506 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47639992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.clcd 47640855 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 314128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3568845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51523292 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314128 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1472436 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1186401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2658837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1472436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47639992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 314083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3568985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51524251 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314083 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1472463 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1186422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2658885 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1472463 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47640855 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 314128 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4755246 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54182129 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15295607 # Number of read requests accepted +system.physmem.bw_total::cpu.inst 314083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4755408 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54183136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15295608 # Number of read requests accepted system.physmem.writeReqs 812506 # Number of write requests accepted -system.physmem.readBursts 15295607 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 15295608 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 812506 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 976934144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1984704 # Total number of bytes read from write queue -system.physmem.bytesWritten 6778304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130982664 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 977064192 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1854720 # Total number of bytes read from write queue +system.physmem.bytesWritten 6781120 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130982728 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 6759304 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 31011 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706576 # Number of DRAM write bursts merged with an existing one +system.physmem.servicedByWrQ 28980 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706520 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 4612 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 955786 # Per bank write bursts +system.physmem.perBankRdBursts::0 955787 # Per bank write bursts system.physmem.perBankRdBursts::1 955478 # Per bank write bursts -system.physmem.perBankRdBursts::2 953003 # Per bank write bursts -system.physmem.perBankRdBursts::3 951059 # Per bank write bursts -system.physmem.perBankRdBursts::4 958601 # Per bank write bursts -system.physmem.perBankRdBursts::5 955602 # Per bank write bursts -system.physmem.perBankRdBursts::6 952653 # Per bank write bursts -system.physmem.perBankRdBursts::7 950407 # Per bank write bursts -system.physmem.perBankRdBursts::8 956154 # Per bank write bursts +system.physmem.perBankRdBursts::2 953511 # Per bank write bursts +system.physmem.perBankRdBursts::3 951566 # Per bank write bursts +system.physmem.perBankRdBursts::4 958612 # Per bank write bursts +system.physmem.perBankRdBursts::5 955530 # Per bank write bursts +system.physmem.perBankRdBursts::6 953056 # Per bank write bursts +system.physmem.perBankRdBursts::7 951020 # Per bank write bursts +system.physmem.perBankRdBursts::8 956158 # Per bank write bursts system.physmem.perBankRdBursts::9 955874 # Per bank write bursts -system.physmem.perBankRdBursts::10 952889 # Per bank write bursts -system.physmem.perBankRdBursts::11 950148 # Per bank write bursts +system.physmem.perBankRdBursts::10 952686 # Per bank write bursts +system.physmem.perBankRdBursts::11 950200 # Per bank write bursts system.physmem.perBankRdBursts::12 956166 # Per bank write bursts system.physmem.perBankRdBursts::13 955918 # Per bank write bursts -system.physmem.perBankRdBursts::14 953918 # Per bank write bursts -system.physmem.perBankRdBursts::15 950940 # Per bank write bursts -system.physmem.perBankWrBursts::0 6546 # Per bank write bursts -system.physmem.perBankWrBursts::1 6352 # Per bank write bursts -system.physmem.perBankWrBursts::2 6488 # Per bank write bursts -system.physmem.perBankWrBursts::3 6518 # Per bank write bursts -system.physmem.perBankWrBursts::4 6421 # Per bank write bursts -system.physmem.perBankWrBursts::5 6701 # Per bank write bursts -system.physmem.perBankWrBursts::6 6665 # Per bank write bursts -system.physmem.perBankWrBursts::7 6611 # Per bank write bursts -system.physmem.perBankWrBursts::8 6966 # Per bank write bursts -system.physmem.perBankWrBursts::9 6759 # Per bank write bursts -system.physmem.perBankWrBursts::10 6421 # Per bank write bursts -system.physmem.perBankWrBursts::11 6055 # Per bank write bursts -system.physmem.perBankWrBursts::12 7037 # Per bank write bursts -system.physmem.perBankWrBursts::13 6645 # Per bank write bursts -system.physmem.perBankWrBursts::14 6920 # Per bank write bursts -system.physmem.perBankWrBursts::15 6806 # Per bank write bursts +system.physmem.perBankRdBursts::14 953812 # Per bank write bursts +system.physmem.perBankRdBursts::15 951254 # Per bank write bursts +system.physmem.perBankWrBursts::0 6556 # Per bank write bursts +system.physmem.perBankWrBursts::1 6344 # Per bank write bursts +system.physmem.perBankWrBursts::2 6481 # Per bank write bursts +system.physmem.perBankWrBursts::3 6512 # Per bank write bursts +system.physmem.perBankWrBursts::4 6422 # Per bank write bursts +system.physmem.perBankWrBursts::5 6709 # Per bank write bursts +system.physmem.perBankWrBursts::6 6691 # Per bank write bursts +system.physmem.perBankWrBursts::7 6631 # Per bank write bursts +system.physmem.perBankWrBursts::8 6968 # Per bank write bursts +system.physmem.perBankWrBursts::9 6764 # Per bank write bursts +system.physmem.perBankWrBursts::10 6424 # Per bank write bursts +system.physmem.perBankWrBursts::11 6068 # Per bank write bursts +system.physmem.perBankWrBursts::12 7033 # Per bank write bursts +system.physmem.perBankWrBursts::13 6638 # Per bank write bursts +system.physmem.perBankWrBursts::14 6915 # Per bank write bursts +system.physmem.perBankWrBursts::15 6799 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2542201638000 # Total gap between requests +system.physmem.totGap 2542155562500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 3351 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 153412 # Read request sizes (log2) +system.physmem.readPktSize::6 153413 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) @@ -112,26 +112,26 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 58488 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1110293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 964892 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 965548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1076032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 973735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1036027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2680967 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2587988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3368391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 111642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 103064 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98734 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20085 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 19255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1110331 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 965784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1077100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 974799 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1038209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2680927 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2586042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3366057 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 129275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 112161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 103418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 99187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19249 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 90 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -159,28 +159,28 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 6263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5332 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 6253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6254 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -208,50 +208,53 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1010606 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.388688 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.020446 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.819397 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22711 2.25% 2.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19828 1.96% 4.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8563 0.85% 5.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2249 0.22% 5.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2594 0.26% 5.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1688 0.17% 5.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8931 0.88% 6.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 959 0.09% 6.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 943083 93.32% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1010606 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6196 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2463.620239 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 113702.310017 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 6191 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1010646 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.481627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.246732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.676766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22575 2.23% 2.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19975 1.98% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8601 0.85% 5.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2200 0.22% 5.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2445 0.24% 5.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1700 0.17% 5.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8928 0.88% 6.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 928 0.09% 6.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 943294 93.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1010646 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6195 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2464.343987 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 113708.986245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 6190 99.92% 99.92% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::524288-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.04858e+06-1.57286e+06 2 0.03% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8.38861e+06-8.9129e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6196 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6196 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.093447 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.042337 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.354685 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3441 55.54% 55.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 45 0.73% 56.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1714 27.66% 83.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 868 14.01% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 47 0.76% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 22 0.36% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.44% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.34% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.16% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6196 # Writes before turning the bus around for reads -system.physmem.totQLat 395449280750 # Total ticks spent queuing -system.physmem.totMemAccLat 681660455750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76322980000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25906.31 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6195 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6195 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.103309 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.049475 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.400786 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3455 55.77% 55.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 44 0.71% 56.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1683 27.17% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 856 13.82% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 62 1.00% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 32 0.52% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 30 0.48% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.23% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.21% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6195 # Writes before turning the bus around for reads +system.physmem.totQLat 395458190750 # Total ticks spent queuing +system.physmem.totMemAccLat 681707465750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76333140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25903.44 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44656.31 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44653.44 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 384.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.67 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.52 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.66 # Average system write bandwidth in MiByte/s @@ -259,18 +262,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.20 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.61 # Average write queue length when enqueuing -system.physmem.readRowHits 14269193 # Number of row buffer hits during reads -system.physmem.writeRowHits 90708 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.09 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.73 # Average write queue length when enqueuing +system.physmem.readRowHits 14271218 # Number of row buffer hits during reads +system.physmem.writeRowHits 90719 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.63 # Row buffer hit rate for writes -system.physmem.avgGap 157821.19 # Average gap between requests -system.physmem.pageHitRate 93.42 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2194513894000 # Time in different power states -system.physmem.memoryStateTime::REF 84889480000 # Time in different power states +system.physmem.writeRowHitRate 85.60 # Row buffer hit rate for writes +system.physmem.avgGap 157818.32 # Average gap between requests +system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2194559119750 # Time in different power states +system.physmem.memoryStateTime::REF 84888180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 262799464750 # Time in different power states +system.physmem.memoryStateTime::ACT 262709081500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 48 # Number of bytes read from this memory @@ -284,49 +287,58 @@ system.realview.nvmem.bw_inst_read::cpu.inst 19 system.realview.nvmem.bw_inst_read::total 19 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 19 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 19 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55125441 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16348039 # Transaction distribution -system.membus.trans_dist::ReadResp 16348039 # Transaction distribution +system.membus.trans_dist::ReadReq 16348037 # Transaction distribution +system.membus.trans_dist::ReadResp 16348037 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution system.membus.trans_dist::Writeback 58488 # Transaction distribution system.membus.trans_dist::UpgradeReq 4612 # Transaction distribution system.membus.trans_dist::UpgradeResp 4612 # Transaction distribution -system.membus.trans_dist::ReadExReq 131651 # Transaction distribution -system.membus.trans_dist::ReadExResp 131651 # Transaction distribution +system.membus.trans_dist::ReadExReq 131654 # Transaction distribution +system.membus.trans_dist::ReadExResp 131654 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 6 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889330 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276174 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1889332 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4276176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34553806 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19029530 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140140058 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140140058 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1558440500 # Layer occupancy (ticks) +system.membus.pkt_count::total 34553808 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 48 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16631504 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 19029594 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140140122 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 216513 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 216513 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 216513 # Request fanout histogram +system.membus.reqLayer0.occupancy 1556318500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 3500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3512000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3760500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17513415500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17512345000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4726913870 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4726136292 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37423565460 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37419189712 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -334,7 +346,6 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48580309 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution @@ -366,34 +377,33 @@ system.iobus.pkt_count_system.bridge.master::total 2383056 system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501006 # Total data (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) @@ -440,22 +450,22 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38173420540 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38173439288 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 13201290 # Number of BP lookups -system.cpu.branchPred.condPredicted 9675974 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 704139 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8377301 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6024680 # Number of BTB hits +system.cpu.branchPred.lookups 13200672 # Number of BP lookups +system.cpu.branchPred.condPredicted 9675464 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 8378152 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6024616 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.916719 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1435837 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 30801 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.908650 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1435808 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 30777 # Number of incorrect RAS predictions. system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -479,25 +489,25 @@ system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DT system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31642294 # DTB read hits -system.cpu.dtb.read_misses 39524 # DTB read misses -system.cpu.dtb.write_hits 11381361 # DTB write hits -system.cpu.dtb.write_misses 10135 # DTB write misses +system.cpu.dtb.read_hits 31644036 # DTB read hits +system.cpu.dtb.read_misses 39518 # DTB read misses +system.cpu.dtb.write_hits 11381434 # DTB write hits +system.cpu.dtb.write_misses 10146 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3437 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 314 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 314 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 1342 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31681818 # DTB read accesses -system.cpu.dtb.write_accesses 11391496 # DTB write accesses +system.cpu.dtb.read_accesses 31683554 # DTB read accesses +system.cpu.dtb.write_accesses 11391580 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 43023655 # DTB hits -system.cpu.dtb.misses 49659 # DTB misses -system.cpu.dtb.accesses 43073314 # DTB accesses +system.cpu.dtb.hits 43025470 # DTB hits +system.cpu.dtb.misses 49664 # DTB misses +system.cpu.dtb.accesses 43075134 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -519,8 +529,8 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 24159481 # ITB inst hits -system.cpu.itb.inst_misses 10516 # ITB inst misses +system.cpu.itb.inst_hits 24158829 # ITB inst hits +system.cpu.itb.inst_misses 10513 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -529,98 +539,98 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2464 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2463 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 4176 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 4177 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 24169997 # ITB inst accesses -system.cpu.itb.hits 24159481 # DTB hits -system.cpu.itb.misses 10516 # DTB misses -system.cpu.itb.accesses 24169997 # DTB accesses -system.cpu.numCycles 499350041 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 24169342 # ITB inst accesses +system.cpu.itb.hits 24158829 # DTB hits +system.cpu.itb.misses 10513 # DTB misses +system.cpu.itb.accesses 24169342 # DTB accesses +system.cpu.numCycles 499362415 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 43030629 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 74131140 # Number of instructions fetch has processed -system.cpu.fetch.Branches 13201290 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 7460517 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448266810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1858598 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 133224 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 12550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 145871 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 3032125 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 24158180 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 404816 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4527 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.179793 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 0.652924 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 43030394 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 74128653 # Number of instructions fetch has processed +system.cpu.fetch.Branches 13200672 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 7460424 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 448275105 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1858360 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 133126 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 12568 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 145919 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 3031035 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 43 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 24157528 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 404783 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 4525 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.179785 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 0.652906 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 454644690 91.75% 91.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13614673 2.75% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 6391682 1.29% 95.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 20899505 4.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 454652495 91.75% 91.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13614115 2.75% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 6392828 1.29% 95.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 20897932 4.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 495550550 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.026437 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.148455 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 35577628 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 424964763 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 30286365 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4037656 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 684138 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1691487 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 250438 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 80256354 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2078563 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 684138 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38799814 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 217885603 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 28702319 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 30653900 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 178824776 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 78213523 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 597412 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 61147213 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 42400387 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 160465829 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 14695892 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 82092463 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 364185184 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 97017359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 495557370 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.026435 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.148447 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 35569711 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 424983346 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 30281377 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4038894 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 684042 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1691471 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 250415 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 80255110 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2078434 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 684042 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38792488 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 217877928 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 28703436 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 30648610 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 178850866 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 78212678 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 597297 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 61152111 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 42400388 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 160465834 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14716938 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 82091302 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 364181024 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 97016550 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 9816 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 75931181 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6161276 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1134052 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 964724 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8995770 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 14558741 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 12101093 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 791110 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1256144 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 75819284 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1655722 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 93902738 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 178739 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4397586 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8688962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 172255 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 495550550 # Number of insts issued each cycle +system.cpu.rename.CommittedMaps 75931219 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 6160077 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1133996 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 964709 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9001428 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 14558433 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 12101238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 791096 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1255692 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 75818942 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1655707 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 93904368 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 178701 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4397117 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8687724 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 172240 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 495557370 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.189492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.548412 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.548385 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 430558497 86.88% 86.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 42998311 8.68% 95.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 15714626 3.17% 98.73% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5641325 1.14% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 637755 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 430560734 86.88% 86.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 43002673 8.68% 95.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 15716973 3.17% 98.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5640247 1.14% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 636707 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -628,44 +638,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 495550550 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 495557370 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4849757 15.79% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 148 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 20356138 66.26% 82.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5517293 17.96% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4845097 15.77% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 148 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 15.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 20357888 66.27% 82.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5517607 17.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 28518 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49538159 52.75% 52.79% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 91859 0.10% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49538039 52.75% 52.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 91860 0.10% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.88% # Type of FU issued @@ -689,101 +699,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.88% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32267131 34.36% 87.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 11974960 12.75% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2111 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.88% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32268758 34.36% 87.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 11975082 12.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 93902738 # Type of FU issued -system.cpu.iq.rate 0.188050 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30723336 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.327183 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 714225557 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 81867089 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 74968821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 93904368 # Type of FU issued +system.cpu.iq.rate 0.188049 # Inst issue rate +system.cpu.iq.fu_busy_cnt 30720740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.327149 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 714233003 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 81866264 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 74968812 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 32544 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 12124 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10212 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 124576093 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124575127 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 21463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 210027 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 210020 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1045815 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 542 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6661 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 369450 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1045495 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 540 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 6662 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 369586 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 17074256 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1003626 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 17074158 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1006174 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 684138 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 94162664 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 98281305 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 77651016 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 684042 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 94158200 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 98278744 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 77650660 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 14558741 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 12101093 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1114432 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 20278 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 98196726 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6661 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 210280 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275497 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 485777 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93247730 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 32000327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 605564 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 14558433 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 12101238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1114427 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 20284 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 98194153 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 6662 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 210239 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 275440 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 485679 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93249449 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 32002025 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 605470 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 176010 # number of nop insts executed -system.cpu.iew.exec_refs 43889216 # number of memory reference insts executed -system.cpu.iew.exec_branches 10791342 # Number of branches executed -system.cpu.iew.exec_stores 11888889 # Number of stores executed -system.cpu.iew.exec_rate 0.186738 # Inst execution rate -system.cpu.iew.wb_sent 92183788 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 74979033 # cumulative count of insts written-back -system.cpu.iew.wb_producers 35465784 # num instructions producing a value -system.cpu.iew.wb_consumers 52709939 # num instructions consuming a value +system.cpu.iew.exec_nop 176011 # number of nop insts executed +system.cpu.iew.exec_refs 43890987 # number of memory reference insts executed +system.cpu.iew.exec_branches 10791373 # Number of branches executed +system.cpu.iew.exec_stores 11888962 # Number of stores executed +system.cpu.iew.exec_rate 0.186737 # Inst execution rate +system.cpu.iew.wb_sent 92183769 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 74979024 # cumulative count of insts written-back +system.cpu.iew.wb_producers 35461894 # num instructions producing a value +system.cpu.iew.wb_consumers 52697256 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.150153 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.672848 # average fanout of values written-back +system.cpu.iew.wb_rate 0.150150 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.672936 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 3942514 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3942249 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1483467 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 458978 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 494644570 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.147200 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 0.699335 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 458881 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 494573774 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.147222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 0.699394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 457921524 92.58% 92.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 22157230 4.48% 97.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 6973464 1.41% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2402706 0.49% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1803578 0.36% 99.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1042786 0.21% 99.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 592301 0.12% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 490313 0.10% 99.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1260668 0.25% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 457850390 92.57% 92.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 22155471 4.48% 97.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 6977487 1.41% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2402189 0.49% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1803487 0.36% 99.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1041949 0.21% 99.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 590384 0.12% 99.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490446 0.10% 99.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1261971 0.26% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 494644570 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60462326 # Number of instructions committed -system.cpu.commit.committedOps 72811859 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 494573774 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60462353 # Number of instructions committed +system.cpu.commit.committedOps 72811899 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 25244569 # Number of memory references committed -system.cpu.commit.loads 13512926 # Number of loads committed +system.cpu.commit.refs 25244590 # Number of memory references committed +system.cpu.commit.loads 13512938 # Number of loads committed system.cpu.commit.membars 403660 # Number of memory barriers committed -system.cpu.commit.branches 10308073 # Number of branches committed +system.cpu.commit.branches 10308077 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 64250122 # Number of committed integer instructions. +system.cpu.commit.int_insts 64250158 # Number of committed integer instructions. system.cpu.commit.function_calls 991634 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 47477289 65.21% 65.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 87890 0.12% 65.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 47477309 65.21% 65.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 87889 0.12% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.33% # Class of committed instruction @@ -811,72 +821,85 @@ system.cpu.commit.op_class_0::SimdFloatMisc 2111 0.00% 65.33% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.33% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.33% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13512926 18.56% 83.89% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 11731643 16.11% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13512938 18.56% 83.89% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 11731652 16.11% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 72811859 # Class of committed instruction -system.cpu.commit.bw_lim_events 1260668 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 72811899 # Class of committed instruction +system.cpu.commit.bw_lim_events 1261971 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 568287463 # The number of ROB reads -system.cpu.rob.rob_writes 154414560 # The number of ROB writes -system.cpu.timesIdled 544007 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3799491 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4584972685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60311945 # Number of Instructions Simulated -system.cpu.committedOps 72661478 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.279455 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.279455 # CPI: Total CPI of All Threads -system.cpu.ipc 0.120781 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.120781 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 109116898 # number of integer regfile reads -system.cpu.int_regfile_writes 47012340 # number of integer regfile writes +system.cpu.rob.rob_reads 568215140 # The number of ROB reads +system.cpu.rob.rob_writes 154414029 # The number of ROB writes +system.cpu.timesIdled 543953 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 3805045 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4584951345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60311972 # Number of Instructions Simulated +system.cpu.committedOps 72661518 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 8.279657 # CPI: Cycles Per Instruction +system.cpu.cpi_total 8.279657 # CPI: Total CPI of All Threads +system.cpu.ipc 0.120778 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.120778 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 109116744 # number of integer regfile reads +system.cpu.int_regfile_writes 47012206 # number of integer regfile writes system.cpu.fp_regfile_reads 8305 # number of floating regfile reads system.cpu.fp_regfile_writes 2780 # number of floating regfile writes -system.cpu.cc_regfile_reads 320404185 # number of cc regfile reads -system.cpu.cc_regfile_writes 30332896 # number of cc regfile writes -system.cpu.misc_regfile_reads 605539146 # number of misc regfile reads -system.cpu.misc_regfile_writes 1173999 # number of misc regfile writes -system.cpu.toL2Bus.throughput 57498963 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2604292 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2604292 # Transaction distribution +system.cpu.cc_regfile_reads 320409300 # number of cc regfile reads +system.cpu.cc_regfile_writes 30332935 # number of cc regfile writes +system.cpu.misc_regfile_reads 605119297 # number of misc regfile reads +system.cpu.misc_regfile_writes 1173998 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 2604204 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2604204 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 599976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 599947 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2950 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2952 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246570 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246570 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926546 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768452 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27160 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85384 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7807542 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61456864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84377274 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37916 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135596 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 146007650 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 146007650 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 166384 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3090458553 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::ReadExReq 246567 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246567 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1926460 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5768361 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 27152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 85364 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7807337 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61454112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 84373434 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 37904 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 135564 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 146001014 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 26770 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 2266210 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 2266210 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2266210 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3090363565 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1447056987 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1446991237 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2544187527 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2544137605 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 17686240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 17681240 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 51535649 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 51517661 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 959881 # number of replacements -system.cpu.icache.tags.tagsinuse 511.383361 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23149457 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 960393 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 24.104150 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 11344582250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.383361 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 959838 # number of replacements +system.cpu.icache.tags.tagsinuse 511.383389 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23148830 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 960350 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 24.104576 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 11339333250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.383389 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998796 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -885,242 +908,242 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 171 system.cpu.icache.tags.age_task_id_blocks_1024::2 221 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 25115239 # Number of tag accesses -system.cpu.icache.tags.data_accesses 25115239 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23149457 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23149457 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23149457 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23149457 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23149457 # number of overall hits -system.cpu.icache.overall_hits::total 23149457 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1005369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1005369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1005369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1005369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1005369 # number of overall misses -system.cpu.icache.overall_misses::total 1005369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13656038478 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13656038478 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13656038478 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13656038478 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13656038478 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 24154826 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 24154826 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 24154826 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 24154826 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 24154826 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 25114544 # Number of tag accesses +system.cpu.icache.tags.data_accesses 25114544 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23148830 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23148830 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23148830 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23148830 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23148830 # number of overall hits +system.cpu.icache.overall_hits::total 23148830 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1005344 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1005344 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1005344 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1005344 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1005344 # number of overall misses +system.cpu.icache.overall_misses::total 1005344 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13667748229 # number of ReadReq miss cycles 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24154174 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.041622 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.041622 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.041622 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.041622 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.041622 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.041622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13583.110756 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13583.110756 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13583.110756 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13583.110756 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1617 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13595.096036 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13595.096036 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13595.096036 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13595.096036 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1628 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 119 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 118 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 13.588235 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 13.796610 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44956 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 44956 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 44956 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 44956 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 44956 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960413 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 960413 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 960413 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 960413 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 960413 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11283890760 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11283890760 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11283890760 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 223026500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 223026500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.039761 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.039761 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.039761 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11748.998358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11748.998358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11748.998358 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 44974 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 44974 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 44974 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 44974 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 44974 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 960370 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 960370 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 960370 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 960370 # number of demand (read+write) MSHR misses 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uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167186700750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 17146783596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 17146783596 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 174356000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184159128346 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184333484346 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026102 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015655 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015654 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986102 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986102 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.540836 # mshr miss rate for ReadExReq accesses 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accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.094783 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000295 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012132 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226345 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.094777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000317 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012131 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.226360 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.094783 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58717.826375 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62553.695093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60501.160287 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10005.812650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10005.812650 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57564.727740 # average ReadExReq mshr miss latency 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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58717.826375 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57916.238816 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57976.678284 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59183.257347 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57961.873649 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58053.794915 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67083.333333 # average overall mshr miss latency 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number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 633790 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.086571 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 267154250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.949942 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.949941 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999902 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 170 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 91797001 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 91797001 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11311240 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11311240 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7209458 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7209458 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 60823 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 60823 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236444 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236444 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 91796938 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 91796938 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 11311263 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 11311263 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7209463 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7209463 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 60828 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 60828 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236419 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236419 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 247594 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 247594 # number of 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miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 26000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 133232870230 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 133232870230 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 133232870230 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 133232870230 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 11884501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11884501 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10221942 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10221942 # number of WriteReq accesses(hits+misses) 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-system.cpu.dcache.overall_accesses::cpu.data 22293767 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 22293767 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048236 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.048236 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 22106458 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 22106458 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 22293785 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 22293785 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.048234 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.048234 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.294708 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.294708 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675306 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.675306 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052070 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052070 # miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.675284 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.675284 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052072 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052072 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000008 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.162204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.162204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166515 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166515 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12588.259390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 12588.259390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41831.429499 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41831.429499 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13719.240838 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13719.240838 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.162203 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162203 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.166514 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.166514 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 12600.762532 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 12600.762532 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41873.463543 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41873.463543 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13647.994148 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13647.994148 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 13000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37156.259084 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37156.259084 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35890.097324 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35890.097324 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 18826 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1227 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.343113 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37193.701936 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37193.701936 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35926.279165 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35926.279165 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 17394 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 459 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1226 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.187602 # average number of cycles each access was blocked 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ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2763128 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2763128 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1233 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1233 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3034874 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3034874 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3034874 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3034874 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 301506 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 301506 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249365 # number of WriteReq MSHR misses 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550842 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 550842 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 624986 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 624986 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3569589078 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3569589078 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10791306319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10791306319 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1230913250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1230913250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 139261250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 139261250 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14353660897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 14353660897 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15584943897 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 15584943897 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182408022250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182408022250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26599942575 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26599942575 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 209007964825 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025370 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025370 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14360895397 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 15591808647 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182406065750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26598901323 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209004967073 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025368 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.025368 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024395 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024395 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395812 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047127 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047127 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.395800 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.395800 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047128 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047128 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024919 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11839.835950 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43245.360492 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16606.419853 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11925.861336 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11925.861336 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024918 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028034 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11840.179242 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43275.838319 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16601.656911 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11847.987919 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11847.987919 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26056.301561 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26056.301561 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24935.271892 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24935.271892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26070.806868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26070.806868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24947.452658 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24947.452658 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1437,16 +1460,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1736929447540 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736929447540 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1736929447540 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1736978742288 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1736978742288 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1736978742288 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83187 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83186 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 3b38aee5d..91e62d8ff 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,180 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.400983 # Number of seconds simulated -sim_ticks 2400982506000 # Number of ticks simulated -final_tick 2400982506000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.400978 # Number of seconds simulated +sim_ticks 2400977890000 # Number of ticks simulated +final_tick 2400977890000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112943 # Simulator instruction rate (inst/s) -host_op_rate 135898 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4496473277 # Simulator tick rate (ticks/s) -host_mem_usage 411684 # Number of bytes of host memory used -host_seconds 533.97 # Real time elapsed on the host -sim_insts 60307964 # Number of instructions simulated -sim_ops 72565708 # Number of ops (including micro ops) simulated +host_inst_rate 184738 # Simulator instruction rate (inst/s) +host_op_rate 222291 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7354994241 # Simulator tick rate (ticks/s) +host_mem_usage 464680 # Number of bytes of host memory used +host_seconds 326.44 # Real time elapsed on the host +sim_insts 60306316 # Number of instructions simulated +sim_ops 72565030 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 493064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6826968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 489736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6827544 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 75520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 799936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1451264 # Number of bytes read from this memory -system.physmem.bytes_read::total 124655200 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 493064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 75520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 757000 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3741312 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1144164 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 79168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 799488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 187904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1451008 # Number of bytes read from this memory +system.physmem.bytes_read::total 124654688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 489736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 79168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 187904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 756808 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3741376 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1144160 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159264 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1712388 # Number of bytes written to this memory -system.physmem.bytes_written::total 6757128 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1712392 # Number of bytes written to this memory +system.physmem.bytes_written::total 6757192 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 13916 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 106697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13864 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 106706 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1180 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 12499 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22676 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512311 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58458 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 286041 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1237 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 12492 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 22672 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512303 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58459 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 286040 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39816 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 428097 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812412 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47821703 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 428098 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812413 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47821795 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 205359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2843406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 203974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2843651 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 31454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 333170 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 78475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 604446 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51918412 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 31454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 78475 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1558242 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 476540 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 332984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 604340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51918299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 203974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32973 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78261 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315208 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 476539 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66333 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 713203 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2814318 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1558242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47821703 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 713206 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2814350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558272 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47821795 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3319946 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 203974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3320191 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 31454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 399503 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 78475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1317649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54732730 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13448319 # Number of read requests accepted -system.physmem.writeReqs 485647 # Number of write requests accepted -system.physmem.readBursts 13448319 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 485647 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860692416 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 32973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 399317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1317546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54732649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446786 # Number of read requests accepted +system.physmem.writeReqs 485691 # Number of write requests accepted +system.physmem.readBursts 13446786 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 485691 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860594304 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 3019520 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109787968 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3006628 # Total written bytes from the system interface side +system.physmem.bytesWritten 3023744 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109777664 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 3009384 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 438446 # Number of DRAM write bursts merged with an existing one +system.physmem.mergedWrBursts 438423 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2870 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835559 # Per bank write bursts -system.physmem.perBankRdBursts::1 835684 # Per bank write bursts -system.physmem.perBankRdBursts::2 835582 # Per bank write bursts -system.physmem.perBankRdBursts::3 835955 # Per bank write bursts -system.physmem.perBankRdBursts::4 836860 # Per bank write bursts -system.physmem.perBankRdBursts::5 838029 # Per bank write bursts -system.physmem.perBankRdBursts::6 838426 # Per bank write bursts -system.physmem.perBankRdBursts::7 839444 # Per bank write bursts -system.physmem.perBankRdBursts::8 841128 # Per bank write bursts -system.physmem.perBankRdBursts::9 843519 # Per bank write bursts -system.physmem.perBankRdBursts::10 843777 # Per bank write bursts -system.physmem.perBankRdBursts::11 843721 # Per bank write bursts -system.physmem.perBankRdBursts::12 845312 # Per bank write bursts -system.physmem.perBankRdBursts::13 845603 # Per bank write bursts -system.physmem.perBankRdBursts::14 845260 # Per bank write bursts -system.physmem.perBankRdBursts::15 844460 # Per bank write bursts -system.physmem.perBankWrBursts::0 2621 # Per bank write bursts -system.physmem.perBankWrBursts::1 2605 # Per bank write bursts -system.physmem.perBankWrBursts::2 2850 # Per bank write bursts -system.physmem.perBankWrBursts::3 3117 # Per bank write bursts -system.physmem.perBankWrBursts::4 3557 # Per bank write bursts -system.physmem.perBankWrBursts::5 3522 # Per bank write bursts -system.physmem.perBankWrBursts::6 2837 # Per bank write bursts -system.physmem.perBankWrBursts::7 2549 # Per bank write bursts -system.physmem.perBankWrBursts::8 2654 # Per bank write bursts -system.physmem.perBankWrBursts::9 2632 # Per bank write bursts -system.physmem.perBankWrBursts::10 2402 # Per bank write bursts -system.physmem.perBankWrBursts::11 2522 # Per bank write bursts -system.physmem.perBankWrBursts::12 3817 # Per bank write bursts -system.physmem.perBankWrBursts::13 3843 # Per bank write bursts -system.physmem.perBankWrBursts::14 3141 # Per bank write bursts -system.physmem.perBankWrBursts::15 2511 # Per bank write bursts +system.physmem.perBankRdBursts::0 835534 # Per bank write bursts +system.physmem.perBankRdBursts::1 835708 # Per bank write bursts +system.physmem.perBankRdBursts::2 835573 # Per bank write bursts +system.physmem.perBankRdBursts::3 835895 # Per bank write bursts +system.physmem.perBankRdBursts::4 836820 # Per bank write bursts +system.physmem.perBankRdBursts::5 838059 # Per bank write bursts +system.physmem.perBankRdBursts::6 838590 # Per bank write bursts +system.physmem.perBankRdBursts::7 839423 # Per bank write bursts +system.physmem.perBankRdBursts::8 841113 # Per bank write bursts +system.physmem.perBankRdBursts::9 843484 # Per bank write bursts +system.physmem.perBankRdBursts::10 843775 # Per bank write bursts +system.physmem.perBankRdBursts::11 843709 # Per bank write bursts +system.physmem.perBankRdBursts::12 845212 # Per bank write bursts +system.physmem.perBankRdBursts::13 845578 # Per bank write bursts +system.physmem.perBankRdBursts::14 844651 # Per bank write bursts +system.physmem.perBankRdBursts::15 843662 # Per bank write bursts +system.physmem.perBankWrBursts::0 2614 # Per bank write bursts +system.physmem.perBankWrBursts::1 2619 # Per bank write bursts +system.physmem.perBankWrBursts::2 2845 # Per bank write bursts +system.physmem.perBankWrBursts::3 3084 # Per bank write bursts +system.physmem.perBankWrBursts::4 3522 # Per bank write bursts +system.physmem.perBankWrBursts::5 3545 # Per bank write bursts +system.physmem.perBankWrBursts::6 2950 # Per bank write bursts +system.physmem.perBankWrBursts::7 2539 # Per bank write bursts +system.physmem.perBankWrBursts::8 2638 # Per bank write bursts +system.physmem.perBankWrBursts::9 2619 # Per bank write bursts +system.physmem.perBankWrBursts::10 2391 # Per bank write bursts +system.physmem.perBankWrBursts::11 2507 # Per bank write bursts +system.physmem.perBankWrBursts::12 3740 # Per bank write bursts +system.physmem.perBankWrBursts::13 3837 # Per bank write bursts +system.physmem.perBankWrBursts::14 3267 # Per bank write bursts +system.physmem.perBankWrBursts::15 2529 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2398981428000 # Total gap between requests +system.physmem.totGap 2398976781000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13409008 # Read request sizes (log2) +system.physmem.readPktSize::3 13407440 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 39311 # Read request sizes (log2) +system.physmem.readPktSize::6 39346 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 467913 # Write request sizes (log2) +system.physmem.writePktSize::2 467914 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17734 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 878886 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 855155 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 852902 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 940592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861312 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 914649 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2399113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2323436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3041002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 84284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 79661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 76726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16593 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16236 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16118 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 39 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17777 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 878947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 855123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852879 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 944479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861163 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 917283 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2393694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2315582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3029092 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 97091 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 88809 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 83328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 80474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,42 +190,42 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2527 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2514 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2513 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2614 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2606 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2704 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2487 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,414 +254,411 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866402 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.895132 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.187701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.697526 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8320 0.96% 0.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8911 1.03% 1.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6111 0.71% 2.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 785 0.09% 2.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 956 0.11% 2.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 773 0.09% 2.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7768 0.90% 3.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 290 0.03% 3.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832488 96.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866402 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2583 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5206.469222 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 249565.705681 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2582 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 866162 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 997.062961 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.716097 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.162362 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8098 0.93% 0.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8963 1.03% 1.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6105 0.70% 2.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 860 0.10% 2.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 965 0.11% 2.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 764 0.09% 2.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7665 0.88% 3.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 291 0.03% 3.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 832451 96.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 866162 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5195.817620 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 249325.060826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2587 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2583 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.265583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.091885 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.157240 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 3 0.12% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 2 0.08% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.04% 0.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 2 0.08% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 3 0.12% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 4 0.15% 0.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 537 20.79% 21.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 7 0.27% 21.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 754 29.19% 51.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1050 40.65% 91.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 100 3.87% 95.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 31 1.20% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 20 0.77% 97.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 15 0.58% 98.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 9 0.35% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 3 0.12% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 7 0.27% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.19% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 5 0.19% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 5 0.19% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 6 0.23% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.15% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 5 0.19% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2583 # Writes before turning the bus around for reads -system.physmem.totQLat 346447958000 # Total ticks spent queuing -system.physmem.totMemAccLat 598603939250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67241595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25761.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2588 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2588 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.255796 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.093626 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.104963 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 2 0.08% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.04% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 3 0.12% 0.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.08% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.12% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.08% 0.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 2 0.08% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 3 0.12% 0.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 555 21.45% 22.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 6 0.23% 22.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 738 28.52% 50.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1040 40.19% 91.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 103 3.98% 95.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 50 1.93% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 14 0.54% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 11 0.43% 97.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 13 0.50% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 5 0.19% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.27% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 6 0.23% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.19% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.23% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.15% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 5 0.19% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2588 # Writes before turning the bus around for reads +system.physmem.totQLat 347055171000 # Total ticks spent queuing +system.physmem.totMemAccLat 599182408500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67233930000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25809.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44511.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44559.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.43 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.26 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.25 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.91 # Average read queue length when enqueuing -system.physmem.avgWrQLen 2.57 # Average write queue length when enqueuing -system.physmem.readRowHits 12588353 # Number of row buffer hits during reads -system.physmem.writeRowHits 40744 # Number of row buffer hits during writes +system.physmem.avgRdQLen 7.23 # Average read queue length when enqueuing +system.physmem.avgWrQLen 2.52 # Average write queue length when enqueuing +system.physmem.readRowHits 12587076 # Number of row buffer hits during reads +system.physmem.writeRowHits 40794 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.32 # Row buffer hit rate for writes -system.physmem.avgGap 172167.88 # Average gap between requests +system.physmem.writeRowHitRate 86.30 # Row buffer hit rate for writes +system.physmem.avgGap 172185.95 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2165142880250 # Time in different power states +system.physmem.memoryStateTime::IDLE 2165163855000 # Time in different power states system.physmem.memoryStateTime::REF 80173860000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 155659356000 # Time in different power states +system.physmem.memoryStateTime::ACT 155638381250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55731244 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13775425 # Transaction distribution -system.membus.trans_dist::ReadResp 13775425 # Transaction distribution -system.membus.trans_dist::WriteReq 471057 # Transaction distribution -system.membus.trans_dist::WriteResp 471057 # Transaction distribution -system.membus.trans_dist::Writeback 17734 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2870 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2870 # Transaction distribution -system.membus.trans_dist::ReadExReq 31339 # Transaction distribution -system.membus.trans_dist::ReadExResp 31339 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 722736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 440 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 15564561 # Transaction distribution +system.membus.trans_dist::ReadResp 15564561 # Transaction distribution +system.membus.trans_dist::WriteReq 763190 # Transaction distribution +system.membus.trans_dist::WriteResp 763190 # Transaction distribution +system.membus.trans_dist::Writeback 58459 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4572 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4572 # Transaction distribution +system.membus.trans_dist::ReadExReq 131741 # Transaction distribution +system.membus.trans_dist::ReadExResp 131741 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382948 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3510 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1037922 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1761100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26818016 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28579116 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 726717 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 880 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5522532 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 6250133 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107272064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113522197 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133809743 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 411651000 # Layer occupancy (ticks) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1895349 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4281819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 28704768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 28704768 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32986587 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390317 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7020 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16592808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18990169 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 114819072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 114819072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 133809241 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 216296 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 216296 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 216296 # Request fanout histogram +system.membus.reqLayer0.occupancy 410119000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 449000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 415500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14677819500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14677410500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1677943291 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1676192784 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33210614750 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33189927250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63162 # number of replacements -system.l2c.tags.tagsinuse 50410.338960 # Cycle average of tags in use -system.l2c.tags.total_refs 1759139 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128553 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.684154 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2389834567500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36865.555388 # Average occupied blocks per requestor +system.l2c.tags.replacements 63154 # number of replacements +system.l2c.tags.tagsinuse 50400.562310 # Cycle average of tags in use +system.l2c.tags.total_refs 1759923 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128542 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.691424 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2389821916000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36854.968320 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4868.284859 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3674.892610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4866.476746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3677.784289 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993335 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 794.582710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 806.547655 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832999 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1730.563101 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1659.086161 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562524 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 799.149653 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 805.381857 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.908524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1731.923626 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1656.975819 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562362 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.074284 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.056074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074257 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.056119 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.012124 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012307 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.026406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.025316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769201 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65380 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3043 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6074 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000168 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997620 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17759906 # Number of tag accesses -system.l2c.tags.data_accesses 17759906 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8189 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2843 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 435869 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 178927 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2011 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 887 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 119100 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 59229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 19905 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6074 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 331991 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 135602 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1300627 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597941 # number of Writeback hits -system.l2c.Writeback_hits::total 597941 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.012194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012289 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.026427 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.025283 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.769052 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3042 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6071 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55876 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17767412 # Number of tag accesses +system.l2c.tags.data_accesses 17767412 # Number of data accesses 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miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58039.611964 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63245.251858 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65302.659517 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62229.853073 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10011.104042 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10008.429279 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 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overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 86843.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60776.651907 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62025.745314 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60774.388564 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -802,57 +811,69 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write 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-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55378 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3509407 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29133952 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 38939733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 68189241 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141801951 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 115908 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2288858155 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 2539315 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2539315 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 763190 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 763190 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 598065 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2933 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2933 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246953 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246953 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1813392 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5760169 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 30385 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 80672 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7684618 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 57608092 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 84067517 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 138604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 141862677 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 18229 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2196613 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2196613 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2196613 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2287106157 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2052757055 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2054352798 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1915102818 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1912625851 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 13212439 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 13149443 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 33686507 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33486737 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48817267 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13767391 # Transaction distribution -system.iobus.trans_dist::ReadResp 13767391 # Transaction distribution -system.iobus.trans_dist::WriteReq 2985 # Transaction distribution -system.iobus.trans_dist::WriteResp 2985 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 12256 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3140 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 706746 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 15535704 # Transaction distribution +system.iobus.trans_dist::ReadResp 15535704 # Transaction distribution +system.iobus.trans_dist::WriteReq 8154 # Transaction distribution +system.iobus.trans_dist::WriteResp 8154 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30010 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 492 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1000 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 732 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -862,45 +883,44 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 722736 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818016 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26818016 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27540752 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 16027 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6280 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 703222 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 726717 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 107998781 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209403 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8657000 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::total 2382948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 28704768 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 28704768 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 31087716 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39305 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15868 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 984 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2000 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 390 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390317 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 114819072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 114819072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 117209389 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 8534000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1570000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1569000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 143000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -908,7 +928,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 353820000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 352708000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -940,11 +960,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13409008000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 719751000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 13407440000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 717460000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33775984250 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33785464750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -969,25 +989,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6543805 # DTB read hits -system.cpu0.dtb.read_misses 5435 # DTB read misses -system.cpu0.dtb.write_hits 6063639 # DTB write hits -system.cpu0.dtb.write_misses 1808 # DTB write misses +system.cpu0.dtb.read_hits 6552093 # DTB read hits +system.cpu0.dtb.read_misses 5443 # DTB read misses +system.cpu0.dtb.write_hits 6067983 # DTB write hits +system.cpu0.dtb.write_misses 1816 # DTB write misses system.cpu0.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5223 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5219 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 107 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 108 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 162 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6549240 # DTB read accesses -system.cpu0.dtb.write_accesses 6065447 # DTB write accesses +system.cpu0.dtb.read_accesses 6557536 # DTB read accesses +system.cpu0.dtb.write_accesses 6069799 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12607444 # DTB hits -system.cpu0.dtb.misses 7243 # DTB misses -system.cpu0.dtb.accesses 12614687 # DTB accesses +system.cpu0.dtb.hits 12620076 # DTB hits +system.cpu0.dtb.misses 7259 # DTB misses +system.cpu0.dtb.accesses 12627335 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1009,55 +1029,55 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30119411 # ITB inst hits -system.cpu0.itb.inst_misses 2986 # ITB inst misses +system.cpu0.itb.inst_hits 30154576 # ITB inst hits +system.cpu0.itb.inst_misses 2994 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 493 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 23 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2362 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 496 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2367 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30122397 # ITB inst accesses -system.cpu0.itb.hits 30119411 # DTB hits -system.cpu0.itb.misses 2986 # DTB misses -system.cpu0.itb.accesses 30122397 # DTB accesses -system.cpu0.numCycles 109377986 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30157570 # ITB inst accesses +system.cpu0.itb.hits 30154576 # DTB hits +system.cpu0.itb.misses 2994 # DTB misses +system.cpu0.itb.accesses 30157570 # DTB accesses +system.cpu0.numCycles 109411317 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29708958 # Number of instructions committed -system.cpu0.committedOps 36436691 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32091710 # Number of integer alu accesses +system.cpu0.committedInsts 29741333 # Number of instructions committed +system.cpu0.committedOps 36475405 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 32123717 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4289 # Number of float alu accesses -system.cpu0.num_func_calls 1119227 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3806697 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32091710 # number of integer instructions +system.cpu0.num_func_calls 1120042 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3813280 # number of instructions that are conditional controls +system.cpu0.num_int_insts 32123717 # number of integer instructions system.cpu0.num_fp_insts 4289 # number of float instructions -system.cpu0.num_int_register_reads 59433720 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21150393 # number of times the integer registers were written +system.cpu0.num_int_register_reads 59486063 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21170898 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3327 # number of times the floating registers were read system.cpu0.num_fp_register_writes 964 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 109113758 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14198144 # number of times the CC registers were written -system.cpu0.num_mem_refs 13068134 # number of memory refs -system.cpu0.num_load_insts 6718957 # Number of load instructions -system.cpu0.num_store_insts 6349177 # Number of store instructions -system.cpu0.num_idle_cycles 107075141.411044 # Number of idle cycles -system.cpu0.num_busy_cycles 2302844.588956 # Number of busy cycles -system.cpu0.not_idle_fraction 0.021054 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.978946 # Percentage of idle cycles -system.cpu0.Branches 5297571 # Number of branches fetched -system.cpu0.op_class::No_OpClass 11842 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23375924 64.04% 64.07% # Class of executed instruction -system.cpu0.op_class::IntMult 45526 0.12% 64.20% # Class of executed instruction +system.cpu0.num_cc_register_reads 109224829 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14221647 # number of times the CC registers were written +system.cpu0.num_mem_refs 13081203 # number of memory refs +system.cpu0.num_load_insts 6727170 # Number of load instructions +system.cpu0.num_store_insts 6354033 # Number of store instructions +system.cpu0.num_idle_cycles 107121976.742744 # Number of idle cycles +system.cpu0.num_busy_cycles 2289340.257256 # Number of busy cycles +system.cpu0.not_idle_fraction 0.020924 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.979076 # Percentage of idle cycles +system.cpu0.Branches 5305474 # Number of branches fetched +system.cpu0.op_class::No_OpClass 11839 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23401650 64.04% 64.07% # Class of executed instruction +system.cpu0.op_class::IntMult 45463 0.12% 64.20% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 64.20% # Class of executed instruction @@ -1081,414 +1101,414 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 64.20% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1430 0.00% 64.20% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1432 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 64.20% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 64.20% # Class of executed instruction -system.cpu0.op_class::MemRead 6718957 18.41% 82.61% # Class of executed instruction -system.cpu0.op_class::MemWrite 6349177 17.39% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 6727170 18.41% 82.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 6354033 17.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36502856 # Class of executed instruction +system.cpu0.op_class::total 36541587 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82922 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 899179 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.616650 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 41225487 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 899691 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 45.821829 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7765042250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.273634 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.912581 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.430435 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967331 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.011548 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020372 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999251 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 82908 # number of quiesce instructions executed +system.cpu0.icache.tags.replacements 899905 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.617888 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41210869 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 900417 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 45.768648 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7755633000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.394938 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.639138 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.583812 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967568 # Average 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miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015096 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089835 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.022030 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014728 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015096 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089835 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.022030 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13655.476234 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13395.193669 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7019.832775 # average ReadReq miss latency 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-system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.423963 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.896552 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27790 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 27790 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 27790 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 27790 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 27790 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 27790 # number of overall MSHR hits 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3957248170 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5359119420 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1401871250 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3957248170 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5359119420 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1401871250 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3957248170 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5359119420 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015103 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.082809 # mshr miss rate for ReadReq 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ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11630.215204 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11799.191283 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11754.517064 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 27890 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 27890 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 27890 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 27890 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 27890 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 27890 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 119626 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 336645 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 456271 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 119626 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 336645 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 456271 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 119626 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 336645 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 456271 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1393831000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3968205684 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5362036684 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1393831000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3968205684 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5362036684 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1393831000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3968205684 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5362036684 # number of overall MSHR miss cycles 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of replacements +system.cpu0.dcache.tags.replacements 630395 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997117 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 21342473 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630803 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.833817 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 21342587 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630907 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.828420 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21757000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.608321 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 7.871908 # Average occupied blocks per requestor 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system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 207 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 92219903 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 92219903 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 5361652 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1457794 # number of ReadReq hits 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LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 85200741 # number of LoadLockedReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1746538982 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 30345323018 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32091862000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1746538982 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 30345323018 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32091862000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5503813 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1503603 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4986969 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 11994385 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5648344 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1304724 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 3264091 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10217159 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 90371 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 32099 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 65414 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 187884 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 128815 # number of LoadLockedReq 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for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.044020 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050320 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047828 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026596 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026945 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.130560 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065260 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029671 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.032831 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.134551 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069012 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13503.307189 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14031.217273 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9490.532076 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37773.885101 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32590.783574 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 27735.952122 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13457.468880 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14736.884331 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 7113.102438 # average LoadLockedReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23080.996194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 28169.091672 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22139.479597 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18728.837176 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27118.396540 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 20760.359523 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 38637 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 6212 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 5775 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 192 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 6.690390 # average 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average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22286.934122 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 18737.476995 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 27311.583864 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 20899.734562 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 35984 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 7309 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 5054 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 190 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.119905 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.468421 # average number of cycles each access was blocked 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cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3901843974 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5668968991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27358748000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27904372000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55263120000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1501669410 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14569249955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16070919365 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 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mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.012886 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11508.649157 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12206.197430 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12002.014851 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35482.277979 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31928.461923 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33016.418024 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.992921 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18514.587842 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17406.560489 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11456.085754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12973.775413 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12570.360110 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20851.475663 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19594.232368 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19968.643508 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20034.295301 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19466.199569 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19639.798754 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 598065 # number of writebacks +system.cpu0.dcache.writebacks::total 598065 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 80 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146918 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146998 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 655 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 754285 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 754940 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 469 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 469 # number of LoadLockedReq MSHR hits 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cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3921572201 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5678363468 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27292544500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 27798821000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55091365500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1484661903 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14572262972 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 16056924875 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28777206403 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42371083972 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71148290375 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030296 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.022172 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.012996 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.022530 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.020265 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009340 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.416320 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.363746 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.197040 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044020 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045056 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.021787 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026683 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.021418 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011314 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.031065 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024109 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.012872 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11510.148296 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12196.929764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11997.889488 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35333.812891 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32200.637628 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33160.299574 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15449.163132 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 18464.335308 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17388.587965 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11503.633218 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12807.176632 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12462.128045 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20868.450282 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19682.264058 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20033.460061 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20051.719117 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19537.817928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19693.973808 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1522,25 +1542,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 1746639 # DTB read hits -system.cpu1.dtb.read_misses 1917 # DTB read misses -system.cpu1.dtb.write_hits 1378449 # DTB write hits +system.cpu1.dtb.read_hits 1733555 # DTB read hits +system.cpu1.dtb.read_misses 1889 # DTB read misses +system.cpu1.dtb.write_hits 1370998 # DTB write hits system.cpu1.dtb.write_misses 367 # DTB write misses system.cpu1.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1626 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1592 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 33 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 28 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 77 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 1748556 # DTB read accesses -system.cpu1.dtb.write_accesses 1378816 # DTB write accesses +system.cpu1.dtb.read_accesses 1735444 # DTB read accesses +system.cpu1.dtb.write_accesses 1371365 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3125088 # DTB hits -system.cpu1.dtb.misses 2284 # DTB misses -system.cpu1.dtb.accesses 3127372 # DTB accesses +system.cpu1.dtb.hits 3104553 # DTB hits +system.cpu1.dtb.misses 2256 # DTB misses +system.cpu1.dtb.accesses 3106809 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1562,55 +1582,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7981130 # ITB inst hits -system.cpu1.itb.inst_misses 1058 # ITB inst misses +system.cpu1.itb.inst_hits 7924396 # ITB inst hits +system.cpu1.itb.inst_misses 1030 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 251 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 10 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 834 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 248 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 806 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7982188 # ITB inst accesses -system.cpu1.itb.hits 7981130 # DTB hits -system.cpu1.itb.misses 1058 # DTB misses -system.cpu1.itb.accesses 7982188 # DTB accesses -system.cpu1.numCycles 582833153 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7925426 # ITB inst accesses +system.cpu1.itb.hits 7924396 # DTB hits +system.cpu1.itb.misses 1030 # DTB misses +system.cpu1.itb.accesses 7925426 # DTB accesses +system.cpu1.numCycles 582686408 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7797141 # Number of instructions committed -system.cpu1.committedOps 9191219 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 8219243 # Number of integer alu accesses +system.cpu1.committedInsts 7745878 # Number of instructions committed +system.cpu1.committedOps 9129746 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 8166989 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1689 # Number of float alu accesses -system.cpu1.num_func_calls 289029 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 993030 # number of instructions that are conditional controls -system.cpu1.num_int_insts 8219243 # number of integer instructions +system.cpu1.num_func_calls 287006 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 983778 # number of instructions that are conditional controls +system.cpu1.num_int_insts 8166989 # number of integer instructions system.cpu1.num_fp_insts 1689 # number of float instructions -system.cpu1.num_int_register_reads 14554839 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5500250 # number of times the integer registers were written +system.cpu1.num_int_register_reads 14466592 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5466665 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1177 # number of times the floating registers were read system.cpu1.num_fp_register_writes 512 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 33218155 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 3793046 # number of times the CC registers were written -system.cpu1.num_mem_refs 3251661 # number of memory refs -system.cpu1.num_load_insts 1804549 # Number of load instructions -system.cpu1.num_store_insts 1447112 # Number of store instructions -system.cpu1.num_idle_cycles 548698663.963538 # Number of idle cycles -system.cpu1.num_busy_cycles 34134489.036462 # Number of busy cycles -system.cpu1.not_idle_fraction 0.058566 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.941434 # Percentage of idle cycles -system.cpu1.Branches 1360376 # Number of branches fetched -system.cpu1.op_class::No_OpClass 4595 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6078995 65.05% 65.10% # Class of executed instruction -system.cpu1.op_class::IntMult 10163 0.11% 65.20% # Class of executed instruction +system.cpu1.num_cc_register_reads 32997995 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 3759402 # number of times the CC registers were written +system.cpu1.num_mem_refs 3229777 # number of memory refs +system.cpu1.num_load_insts 1791377 # Number of load instructions +system.cpu1.num_store_insts 1438400 # Number of store instructions +system.cpu1.num_idle_cycles 548052403.807954 # Number of idle cycles +system.cpu1.num_busy_cycles 34634004.192046 # Number of busy cycles +system.cpu1.not_idle_fraction 0.059438 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.940562 # Percentage of idle cycles +system.cpu1.Branches 1348409 # Number of branches fetched +system.cpu1.op_class::No_OpClass 4600 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6037827 65.04% 65.09% # Class of executed instruction +system.cpu1.op_class::IntMult 10088 0.11% 65.20% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 65.20% # Class of executed instruction @@ -1634,26 +1654,26 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.20% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.20% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.20% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 281 0.00% 65.21% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 273 0.00% 65.21% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 65.21% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.21% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.21% # Class of executed instruction -system.cpu1.op_class::MemRead 1804549 19.31% 84.52% # Class of executed instruction -system.cpu1.op_class::MemWrite 1447112 15.48% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 1791377 19.30% 84.50% # Class of executed instruction +system.cpu1.op_class::MemWrite 1438400 15.50% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 9345695 # Class of executed instruction +system.cpu1.op_class::total 9282565 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5844133 # Number of BP lookups -system.cpu2.branchPred.condPredicted 4389690 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 248799 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3701982 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2861782 # Number of BTB hits +system.cpu2.branchPred.lookups 5846326 # Number of BP lookups +system.cpu2.branchPred.condPredicted 4388844 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 249586 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3633950 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2855743 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 77.304050 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 588875 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 15609 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 78.585093 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 589622 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 15464 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1677,25 +1697,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 13926534 # DTB read hits -system.cpu2.dtb.read_misses 28241 # DTB read misses -system.cpu2.dtb.write_hits 3979346 # DTB write hits -system.cpu2.dtb.write_misses 9743 # DTB write misses +system.cpu2.dtb.read_hits 13911313 # DTB read hits +system.cpu2.dtb.read_misses 27890 # DTB read misses +system.cpu2.dtb.write_hits 3983127 # DTB write hits +system.cpu2.dtb.write_misses 9793 # DTB write misses system.cpu2.dtb.flush_tlb 550 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2739 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 445 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 255 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2737 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 484 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 262 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 656 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 13954775 # DTB read accesses -system.cpu2.dtb.write_accesses 3989089 # DTB write accesses +system.cpu2.dtb.perms_faults 640 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 13939203 # DTB read accesses +system.cpu2.dtb.write_accesses 3992920 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 17905880 # DTB hits -system.cpu2.dtb.misses 37984 # DTB misses -system.cpu2.dtb.accesses 17943864 # DTB accesses +system.cpu2.dtb.hits 17894440 # DTB hits +system.cpu2.dtb.misses 37683 # DTB misses +system.cpu2.dtb.accesses 17932123 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1717,8 +1737,8 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4053038 # ITB inst hits -system.cpu2.itb.inst_misses 6578 # ITB inst misses +system.cpu2.itb.inst_hits 4060759 # ITB inst hits +system.cpu2.itb.inst_misses 6577 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1727,266 +1747,266 @@ system.cpu2.itb.flush_tlb 550 # Nu system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 2058 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 2055 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 2441 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 2376 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4059616 # ITB inst accesses -system.cpu2.itb.hits 4053038 # DTB hits -system.cpu2.itb.misses 6578 # DTB misses -system.cpu2.itb.accesses 4059616 # DTB accesses -system.cpu2.numCycles 88208146 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4067336 # ITB inst accesses +system.cpu2.itb.hits 4060759 # DTB hits +system.cpu2.itb.misses 6577 # DTB misses +system.cpu2.itb.accesses 4067336 # DTB accesses +system.cpu2.numCycles 88050542 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10487397 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32911643 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 5844133 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 3450657 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 74966701 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 679472 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 80302 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 630 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 972 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 72243 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 1263867 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 410 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4050067 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 153217 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2804 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 87212188 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 0.443226 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 1.629212 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10519234 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32939379 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 5846326 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 3445365 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 74770225 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 681136 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 80231 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 505 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 954 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 72091 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 1265694 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 337 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4057838 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 153485 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2814 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 87049769 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 0.444404 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 1.631683 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 79899565 91.62% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 625094 0.72% 92.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 698013 0.80% 93.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 764181 0.88% 94.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 868461 1.00% 95.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 574503 0.66% 95.66% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 981504 1.13% 96.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 301305 0.35% 97.13% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2499562 2.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 79735168 91.60% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 627849 0.72% 92.32% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 697488 0.80% 93.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 764418 0.88% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 855506 0.98% 94.98% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 578096 0.66% 95.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 986877 1.13% 96.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 299514 0.34% 97.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2504853 2.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 87212188 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.066254 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.373113 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 8569138 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 72587758 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 4831209 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 941079 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 281926 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 736866 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 58789 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34844703 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 196626 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 281926 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 9031224 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 19204705 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13140033 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5253439 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 40299841 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33794581 # Number of instructions processed by rename +system.cpu2.fetch.rateDist::total 87049769 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.066397 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.374096 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 8593092 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 72401111 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 4830102 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 941679 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 282689 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 738219 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 58888 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 34839136 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 197306 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 282689 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 9053752 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 19270728 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13147343 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5254066 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 40040151 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 33787886 # Number of instructions processed by rename system.cpu2.rename.ROBFullEvents 74120 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 29618551 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 37683898 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 1100267 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 36626919 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 154339316 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41664821 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4127 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 28795876 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 7831027 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 344066 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 286541 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 5082070 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6089915 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 4400227 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 719431 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1142118 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32029170 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 669683 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 38616590 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 44993 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 5567256 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12099893 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 238978 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 87212188 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.442789 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.239118 # Number of insts issued each cycle +system.cpu2.rename.IQFullEvents 29496747 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 37523489 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1004110 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 36611560 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 154353600 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 41662755 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4122 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 28819307 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 7792237 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 344984 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 287406 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 5085187 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6095255 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 4404078 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 715172 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1132058 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32032092 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 661150 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 38610720 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 45237 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5536917 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12037471 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 230168 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 87049769 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.443548 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.240485 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 73763195 84.58% 84.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 4095516 4.70% 89.28% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2328743 2.67% 91.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2051674 2.35% 94.30% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2976748 3.41% 97.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 798764 0.92% 98.63% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 739781 0.85% 99.48% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 293068 0.34% 99.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 164699 0.19% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73601742 84.55% 84.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 4103417 4.71% 89.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2329810 2.68% 91.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2044829 2.35% 94.29% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2965004 3.41% 97.70% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 800473 0.92% 98.62% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 744836 0.86% 99.47% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 295465 0.34% 99.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 164193 0.19% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 87212188 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 87049769 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 122993 5.40% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.40% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1970586 86.46% 91.85% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 185678 8.15% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 123164 5.43% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 2 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1963174 86.51% 91.94% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 182867 8.06% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 12081 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 20207276 52.33% 52.36% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 34218 0.09% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 404 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.45% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 14176555 36.71% 89.16% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 4186056 10.84% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 12079 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 20212271 52.35% 52.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 34343 0.09% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 410 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.47% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 14161220 36.68% 89.15% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 4190397 10.85% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 38616590 # Type of FU issued -system.cpu2.iq.rate 0.437789 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2279258 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.059023 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 166760031 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 38278238 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29588244 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9588 # Number of floating instruction queue reads +system.cpu2.iq.FU_type_0::total 38610720 # Type of FU issued +system.cpu2.iq.rate 0.438506 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2269207 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.058771 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 166576049 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 38242231 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 29605417 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9604 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 5150 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 4304 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 40878658 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5109 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 176007 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 40862730 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5118 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 177793 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1107424 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2018 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 18033 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 469449 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1108149 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 17977 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 469749 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5207867 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 3518142 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5186465 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 3515984 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 281926 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 17856855 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 716566 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32817404 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 57776 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6089915 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 4400227 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 491578 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 63121 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 616282 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 18033 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 121106 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 106258 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 227364 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 38297957 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 14051286 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 280797 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 282689 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 17818885 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 827114 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32812972 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 58820 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6095255 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 4404078 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 482366 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 63304 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 726253 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 17977 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 122015 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 106758 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 228773 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 38292590 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 14036165 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 280577 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 118551 # number of nop insts executed -system.cpu2.iew.exec_refs 18186993 # number of memory reference insts executed -system.cpu2.iew.exec_branches 4220297 # Number of branches executed -system.cpu2.iew.exec_stores 4135707 # Number of stores executed -system.cpu2.iew.exec_rate 0.434177 # Inst execution rate -system.cpu2.iew.wb_sent 34852514 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29592548 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17266310 # num instructions producing a value -system.cpu2.iew.wb_consumers 30698955 # num instructions consuming a value +system.cpu2.iew.exec_nop 119730 # number of nop insts executed +system.cpu2.iew.exec_refs 18176329 # number of memory reference insts executed +system.cpu2.iew.exec_branches 4221740 # Number of branches executed +system.cpu2.iew.exec_stores 4140164 # Number of stores executed +system.cpu2.iew.exec_rate 0.434893 # Inst execution rate +system.cpu2.iew.wb_sent 34848706 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 29609721 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 17270580 # num instructions producing a value +system.cpu2.iew.wb_consumers 30711387 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.335485 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.562440 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.336281 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.562351 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 5479640 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 430705 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 190919 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 86342246 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.312843 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.237203 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 5477647 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 430982 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 191637 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 86152512 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.313795 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.238508 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 77364915 89.60% 89.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4177735 4.84% 94.44% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1290086 1.49% 95.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 753837 0.87% 96.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 490440 0.57% 97.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 381562 0.44% 97.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 374801 0.43% 98.25% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 197147 0.23% 98.48% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1311723 1.52% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 77159399 89.56% 89.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4186602 4.86% 94.42% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1295333 1.50% 95.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 754876 0.88% 96.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 491618 0.57% 97.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 381305 0.44% 97.81% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 375733 0.44% 98.25% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 196216 0.23% 98.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1311430 1.52% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 86342246 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 22875674 # Number of instructions committed -system.cpu2.commit.committedOps 27011607 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 86152512 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 22893469 # Number of instructions committed +system.cpu2.commit.committedOps 27034243 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8913269 # Number of memory references committed -system.cpu2.commit.loads 4982491 # Number of loads committed -system.cpu2.commit.membars 117220 # Number of memory barriers committed -system.cpu2.commit.branches 3644555 # Number of branches committed +system.cpu2.commit.refs 8921435 # Number of memory references committed +system.cpu2.commit.loads 4987106 # Number of loads committed +system.cpu2.commit.membars 117312 # Number of memory barriers committed +system.cpu2.commit.branches 3648396 # Number of branches committed system.cpu2.commit.fp_insts 4270 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 23908542 # Number of committed integer instructions. -system.cpu2.commit.function_calls 341319 # Number of function calls committed. +system.cpu2.commit.int_insts 23927319 # Number of committed integer instructions. +system.cpu2.commit.function_calls 341825 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 18065773 66.88% 66.88% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 32161 0.12% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 18080099 66.88% 66.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 32299 0.12% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::IntDiv 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 67.00% # Class of committed instruction @@ -2010,36 +2030,36 @@ system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 67.00% # system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 404 0.00% 67.00% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 410 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.00% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 4982491 18.45% 85.45% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3930778 14.55% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 4987106 18.45% 85.45% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3934329 14.55% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 27011607 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1311723 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 27034243 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1311430 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 116854146 # The number of ROB reads -system.cpu2.rob.rob_writes 65855440 # The number of ROB writes -system.cpu2.timesIdled 179134 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 995958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3544369510 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 22801865 # Number of Instructions Simulated -system.cpu2.committedOps 26937798 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 3.868462 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 3.868462 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.258501 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.258501 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 45014030 # number of integer regfile reads -system.cpu2.int_regfile_writes 19144459 # number of integer regfile writes -system.cpu2.fp_regfile_reads 47113 # number of floating regfile reads +system.cpu2.rob.rob_reads 116684345 # The number of ROB reads +system.cpu2.rob.rob_writes 65897015 # The number of ROB writes +system.cpu2.timesIdled 179321 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1000773 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3544672545 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 22819105 # Number of Instructions Simulated +system.cpu2.committedOps 26959879 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 3.858633 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 3.858633 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.259159 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.259159 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 45005013 # number of integer regfile reads +system.cpu2.int_regfile_writes 19153075 # number of integer regfile writes +system.cpu2.fp_regfile_reads 47120 # number of floating regfile reads system.cpu2.fp_regfile_writes 45464 # number of floating regfile writes -system.cpu2.cc_regfile_reads 130800569 # number of cc regfile reads -system.cpu2.cc_regfile_writes 12559359 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124603397 # number of misc regfile reads -system.cpu2.misc_regfile_writes 350092 # number of misc regfile writes +system.cpu2.cc_regfile_reads 130804455 # number of cc regfile reads +system.cpu2.cc_regfile_writes 12559622 # number of cc regfile writes +system.cpu2.misc_regfile_reads 122469878 # number of misc regfile reads +system.cpu2.misc_regfile_writes 350259 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2056,10 +2076,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1536004079250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536004079250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1536004079250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536462300750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536462300750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536462300750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 055919fe9..9300fd8b1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,154 +1,154 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.539697 # Number of seconds simulated -sim_ticks 2539696838000 # Number of ticks simulated -final_tick 2539696838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.539695 # Number of seconds simulated +sim_ticks 2539695141000 # Number of ticks simulated +final_tick 2539695141000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33216 # Simulator instruction rate (inst/s) -host_op_rate 40018 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1398403355 # Simulator tick rate (ticks/s) -host_mem_usage 411672 # Number of bytes of host memory used -host_seconds 1816.14 # Real time elapsed on the host -sim_insts 60325607 # Number of instructions simulated -sim_ops 72677421 # Number of ops (including micro ops) simulated +host_inst_rate 55026 # Simulator instruction rate (inst/s) +host_op_rate 66292 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2316696588 # Simulator tick rate (ticks/s) +host_mem_usage 466732 # Number of bytes of host memory used +host_seconds 1096.26 # Real time elapsed on the host +sim_insts 60322278 # Number of instructions simulated +sim_ops 72673006 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 469568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3933400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 314240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5155776 # Number of bytes read from this memory -system.physmem.bytes_read::total 130985112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 469568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 314240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 783808 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3774400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1328880 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1687192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6790472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 471296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3922776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 314048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5167104 # Number of bytes read from this memory +system.physmem.bytes_read::total 130987352 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 471296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 314048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 785344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3775232 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1328636 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1687436 # Number of bytes written to this memory +system.physmem.bytes_written::total 6791304 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7337 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 61485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 80559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293132 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58975 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 332220 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 421798 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812993 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47687002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 353 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu0.inst 7364 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 61319 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 9 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 80736 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293167 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58988 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 332159 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 421859 # Number of write requests responded to by this memory +system.physmem.num_writes::total 813006 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47687034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 378 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 184891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1548768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 123731 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2030075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51575097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 184891 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 123731 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 308623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1486162 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 523244 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 664328 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2673733 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1486162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47687002 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 353 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 185572 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1544585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 123656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2034537 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51576014 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 185572 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 123656 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 309228 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1486490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 523148 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 664425 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2674063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1486490 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47687034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 378 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 184891 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2072011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 123731 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2694403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54248831 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293132 # Number of read requests accepted -system.physmem.writeReqs 812993 # Number of write requests accepted -system.physmem.readBursts 15293132 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 812993 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 975241856 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 3518592 # Total number of bytes read from write queue -system.physmem.bytesWritten 6826496 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 130985112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6790472 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 54978 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706304 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4635 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 954958 # Per bank write bursts -system.physmem.perBankRdBursts::1 950647 # Per bank write bursts -system.physmem.perBankRdBursts::2 950811 # Per bank write bursts -system.physmem.perBankRdBursts::3 950999 # Per bank write bursts -system.physmem.perBankRdBursts::4 954856 # Per bank write bursts -system.physmem.perBankRdBursts::5 951881 # Per bank write bursts -system.physmem.perBankRdBursts::6 951736 # Per bank write bursts -system.physmem.perBankRdBursts::7 951699 # Per bank write bursts -system.physmem.perBankRdBursts::8 955454 # Per bank write bursts -system.physmem.perBankRdBursts::9 951840 # Per bank write bursts -system.physmem.perBankRdBursts::10 951452 # Per bank write bursts -system.physmem.perBankRdBursts::11 951010 # Per bank write bursts -system.physmem.perBankRdBursts::12 955349 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 185572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2067733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 123656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2698962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54250077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293167 # Number of read requests accepted +system.physmem.writeReqs 813006 # Number of write requests accepted +system.physmem.readBursts 15293167 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 813006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 975220032 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3542656 # Total number of bytes read from write queue +system.physmem.bytesWritten 6827904 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 130987352 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6791304 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 55354 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706297 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4647 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 954783 # Per bank write bursts +system.physmem.perBankRdBursts::1 950591 # Per bank write bursts +system.physmem.perBankRdBursts::2 950729 # Per bank write bursts +system.physmem.perBankRdBursts::3 950904 # Per bank write bursts +system.physmem.perBankRdBursts::4 954888 # Per bank write bursts +system.physmem.perBankRdBursts::5 951868 # Per bank write bursts +system.physmem.perBankRdBursts::6 951800 # Per bank write bursts +system.physmem.perBankRdBursts::7 951730 # Per bank write bursts +system.physmem.perBankRdBursts::8 955391 # Per bank write bursts +system.physmem.perBankRdBursts::9 951917 # Per bank write bursts +system.physmem.perBankRdBursts::10 951458 # Per bank write bursts +system.physmem.perBankRdBursts::11 951066 # Per bank write bursts +system.physmem.perBankRdBursts::12 955340 # Per bank write bursts system.physmem.perBankRdBursts::13 951888 # Per bank write bursts -system.physmem.perBankRdBursts::14 952124 # Per bank write bursts -system.physmem.perBankRdBursts::15 951450 # Per bank write bursts -system.physmem.perBankWrBursts::0 6588 # Per bank write bursts -system.physmem.perBankWrBursts::1 6390 # Per bank write bursts -system.physmem.perBankWrBursts::2 6534 # Per bank write bursts -system.physmem.perBankWrBursts::3 6563 # Per bank write bursts -system.physmem.perBankWrBursts::4 6471 # Per bank write bursts +system.physmem.perBankRdBursts::14 951979 # Per bank write bursts +system.physmem.perBankRdBursts::15 951481 # Per bank write bursts +system.physmem.perBankWrBursts::0 6606 # Per bank write bursts +system.physmem.perBankWrBursts::1 6389 # Per bank write bursts +system.physmem.perBankWrBursts::2 6527 # Per bank write bursts +system.physmem.perBankWrBursts::3 6560 # Per bank write bursts +system.physmem.perBankWrBursts::4 6487 # Per bank write bursts system.physmem.perBankWrBursts::5 6764 # Per bank write bursts -system.physmem.perBankWrBursts::6 6747 # Per bank write bursts -system.physmem.perBankWrBursts::7 6681 # Per bank write bursts -system.physmem.perBankWrBursts::8 6996 # Per bank write bursts -system.physmem.perBankWrBursts::9 6810 # Per bank write bursts -system.physmem.perBankWrBursts::10 6454 # Per bank write bursts -system.physmem.perBankWrBursts::11 6114 # Per bank write bursts -system.physmem.perBankWrBursts::12 7081 # Per bank write bursts -system.physmem.perBankWrBursts::13 6669 # Per bank write bursts -system.physmem.perBankWrBursts::14 6965 # Per bank write bursts -system.physmem.perBankWrBursts::15 6837 # Per bank write bursts +system.physmem.perBankWrBursts::6 6744 # Per bank write bursts +system.physmem.perBankWrBursts::7 6672 # Per bank write bursts +system.physmem.perBankWrBursts::8 7003 # Per bank write bursts +system.physmem.perBankWrBursts::9 6796 # Per bank write bursts +system.physmem.perBankWrBursts::10 6466 # Per bank write bursts +system.physmem.perBankWrBursts::11 6118 # Per bank write bursts +system.physmem.perBankWrBursts::12 7066 # Per bank write bursts +system.physmem.perBankWrBursts::13 6690 # Per bank write bursts +system.physmem.perBankWrBursts::14 6968 # Per bank write bursts +system.physmem.perBankWrBursts::15 6830 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2539695718000 # Total gap between requests +system.physmem.totGap 2539694027000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 18 # Read request sizes (log2) system.physmem.readPktSize::3 15138826 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154288 # Read request sizes (log2) +system.physmem.readPktSize::6 154323 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 58975 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1062531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1005454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1062790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 969024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1031345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2691523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2602840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3403260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 108695 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 99295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 93778 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 90278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 18929 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18290 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see +system.physmem.writePktSize::6 58988 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1062880 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1005296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1064387 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 969141 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1032129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2687855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2599195 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3397795 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 112262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 102458 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 95445 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 91862 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 18918 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18221 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -161,43 +161,43 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 294 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 285 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 278 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 275 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 273 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 272 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 265 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6096 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 6085 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5897 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 6338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5876 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6252 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see @@ -225,24 +225,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1008721 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 973.577780 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 909.477346 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 200.561203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22290 2.21% 2.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20048 1.99% 4.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8821 0.87% 5.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2154 0.21% 5.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2027 0.20% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1663 0.16% 5.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9185 0.91% 6.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 821 0.08% 6.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 941712 93.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1008721 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6071 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2509.988470 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 47472.970867 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 6043 99.54% 99.54% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1008813 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 973.468756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 909.284641 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 200.732372 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22320 2.21% 2.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20114 1.99% 4.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8797 0.87% 5.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2199 0.22% 5.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2055 0.20% 5.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1694 0.17% 5.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9190 0.91% 6.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 817 0.08% 6.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 941627 93.34% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1008813 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6078 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2507.042448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 47447.723031 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 6050 99.54% 99.54% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::65536-131071 3 0.05% 99.59% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::131072-196607 8 0.13% 99.72% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-262143 5 0.08% 99.80% # Reads before turning the bus around for writes @@ -252,50 +252,51 @@ system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% system.physmem.rdPerTurnAround::983040-1.04858e+06 2 0.03% 99.88% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 6 0.10% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6071 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6071 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.569428 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.390583 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.344347 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 2 0.03% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 6 0.10% 0.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 3 0.05% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 4 0.07% 0.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 3 0.05% 0.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 1 0.02% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8 3 0.05% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 4 0.07% 0.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 3 0.05% 0.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 1 0.02% 0.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 3 0.05% 0.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 10 0.16% 0.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2784 45.86% 46.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 49 0.81% 47.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 1358 22.37% 69.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1417 23.34% 93.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 155 2.55% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 60 0.99% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.59% 97.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 21 0.35% 97.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 24 0.40% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 17 0.28% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 23 0.38% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 14 0.23% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 10 0.16% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 12 0.20% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 16 0.26% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 11 0.18% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 14 0.23% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6071 # Writes before turning the bus around for reads -system.physmem.totQLat 392019251500 # Total ticks spent queuing -system.physmem.totMemAccLat 677734639000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 76190770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25726.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6078 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6078 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.552813 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.369881 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.322612 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 5 0.08% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 4 0.07% 0.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 4 0.07% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 4 0.07% 0.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 2 0.03% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 2 0.03% 0.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 3 0.05% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 1 0.02% 0.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.03% 0.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 3 0.05% 0.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 3 0.05% 0.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 2 0.03% 0.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 13 0.21% 0.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2782 45.77% 46.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 46 0.76% 47.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 1401 23.05% 70.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1370 22.54% 93.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 152 2.50% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 75 1.23% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 36 0.59% 97.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 22 0.36% 97.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 24 0.39% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 25 0.41% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 13 0.21% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 15 0.25% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 16 0.26% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 12 0.20% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 9 0.15% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 11 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6078 # Writes before turning the bus around for reads +system.physmem.totQLat 392436805250 # Total ticks spent queuing +system.physmem.totMemAccLat 678145799000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 76189065000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25754.14 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44476.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 384.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44504.14 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 383.99 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.69 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s @@ -303,18 +304,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 3.02 # Data bus utilization in percentage system.physmem.busUtilRead 3.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 5.74 # Average read queue length when enqueuing -system.physmem.avgWrQLen 14.90 # Average write queue length when enqueuing -system.physmem.readRowHits 14244888 # Number of row buffer hits during reads -system.physmem.writeRowHits 91209 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.40 # Average read queue length when enqueuing +system.physmem.avgWrQLen 14.87 # Average write queue length when enqueuing +system.physmem.readRowHits 14244486 # Number of row buffer hits during reads +system.physmem.writeRowHits 91200 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.49 # Row buffer hit rate for writes -system.physmem.avgGap 157685.09 # Average gap between requests +system.physmem.writeRowHitRate 85.47 # Row buffer hit rate for writes +system.physmem.avgGap 157684.51 # Average gap between requests system.physmem.pageHitRate 93.43 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2193828681000 # Time in different power states -system.physmem.memoryStateTime::REF 84806020000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2193361967750 # Time in different power states +system.physmem.memoryStateTime::REF 84805760000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 261061225250 # Time in different power states +system.physmem.memoryStateTime::ACT 261520412250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory @@ -328,280 +329,291 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55193080 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16345666 # Transaction distribution -system.membus.trans_dist::ReadResp 16345666 # Transaction distribution +system.membus.trans_dist::ReadReq 16345693 # Transaction distribution +system.membus.trans_dist::ReadResp 16345693 # Transaction distribution system.membus.trans_dist::WriteReq 763357 # Transaction distribution system.membus.trans_dist::WriteResp 763357 # Transaction distribution -system.membus.trans_dist::Writeback 58975 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4635 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution -system.membus.trans_dist::ReadExReq 131547 # Transaction distribution -system.membus.trans_dist::ReadExResp 131547 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383056 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 58988 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4647 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4647 # Transaction distribution +system.membus.trans_dist::ReadExReq 131549 # Transaction distribution +system.membus.trans_dist::ReadExResp 131549 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383044 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3780 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1884913 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4271753 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1885020 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4271848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30277632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30277632 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34549385 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390478 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16665056 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 19063162 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 140173690 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 140173690 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487406000 # Layer occupancy (ticks) +system.membus.pkt_count::total 34549480 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390454 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16668128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19066210 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 140176738 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 217843 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 217843 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 217843 # Request fanout histogram +system.membus.reqLayer0.occupancy 1488348000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3427500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3508000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17563315500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17564779000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4754319520 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4755343440 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37450374673 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37440252152 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 64063 # number of replacements -system.l2c.tags.tagsinuse 51393.584080 # Cycle average of tags in use -system.l2c.tags.total_refs 1901876 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 129454 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 14.691520 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2528371598500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37072.406553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.476763 # Average occupied blocks per requestor +system.l2c.tags.replacements 64097 # number of replacements +system.l2c.tags.tagsinuse 51403.492359 # Cycle average of tags in use +system.l2c.tags.total_refs 1900046 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 129489 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 14.673416 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2528369126500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37092.927950 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 9.579992 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000251 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5409.710973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3302.260075 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.209843 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2641.050651 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2952.468970 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.565680 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000145 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5418.531577 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3300.356905 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.423602 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2630.879076 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2944.793006 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000146 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.082546 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.050388 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000095 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.040299 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.784204 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.082680 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.050359 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000098 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.044934 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.784355 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65378 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 438 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3140 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5952 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55810 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 434 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3142 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5950 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55813 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997589 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 18903981 # Number of tag accesses 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -776,46 +788,58 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58696725 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2675214 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2675214 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2673184 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2673184 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763357 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763357 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 606690 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2935 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2937 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 246039 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 246039 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1976942 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5792286 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42218 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136665 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7948111 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63231360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85355770 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 148879474 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 148879474 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 192412 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4956067661 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 606482 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2937 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2940 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 246011 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 246011 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1973853 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5791552 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42247 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 136455 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7944107 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 63133312 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 85325794 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 62264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 230296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 148751666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 33359 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2344441 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2344441 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2344441 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4954098182 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4453658755 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4446552172 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4478828129 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4477877910 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26774357 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 26748853 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 79740148 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 79493732 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48628247 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16322168 # Transaction distribution -system.iobus.trans_dist::ReadResp 16322168 # Transaction distribution +system.iobus.trans_dist::ReadReq 16322162 # Transaction distribution +system.iobus.trans_dist::ReadResp 16322162 # Transaction distribution system.iobus.trans_dist::WriteReq 8176 # Transaction distribution system.iobus.trans_dist::WriteResp 8176 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7940 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 520 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -837,41 +861,40 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383056 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30277632 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30277632 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 32660688 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15880 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 123501006 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 123501006 # Total data (bytes) +system.iobus.pkt_count::total 32660676 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390454 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 121110528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 123500982 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3975000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3969000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 520000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -915,21 +938,21 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15138816000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374880000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15138816000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374868000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38124261327 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38127481848 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7765284 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5771603 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 325703 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4845901 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3829041 # Number of BTB hits +system.cpu0.branchPred.lookups 7736387 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5741528 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 324689 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4736478 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3796485 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 79.016080 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 808445 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 22619 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 80.154178 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 808967 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 22406 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -953,25 +976,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 27181562 # DTB read hits -system.cpu0.dtb.read_misses 37782 # DTB read misses -system.cpu0.dtb.write_hits 5596065 # DTB write hits -system.cpu0.dtb.write_misses 10098 # DTB write misses +system.cpu0.dtb.read_hits 27184101 # DTB read hits +system.cpu0.dtb.read_misses 37692 # DTB read misses +system.cpu0.dtb.write_hits 5601213 # DTB write hits +system.cpu0.dtb.write_misses 10069 # DTB write misses system.cpu0.dtb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5491 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 645 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 284 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5493 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 558 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 288 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 704 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 27219344 # DTB read accesses -system.cpu0.dtb.write_accesses 5606163 # DTB write accesses +system.cpu0.dtb.perms_faults 698 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 27221793 # DTB read accesses +system.cpu0.dtb.write_accesses 5611282 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32777627 # DTB hits -system.cpu0.dtb.misses 47880 # DTB misses -system.cpu0.dtb.accesses 32825507 # DTB accesses +system.cpu0.dtb.hits 32785314 # DTB hits +system.cpu0.dtb.misses 47761 # DTB misses +system.cpu0.dtb.accesses 32833075 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -993,712 +1016,720 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 5349242 # ITB inst hits -system.cpu0.itb.inst_misses 7594 # ITB inst misses +system.cpu0.itb.inst_hits 5349776 # ITB inst hits +system.cpu0.itb.inst_misses 7612 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 510 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 731 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 726 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 31 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2632 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2439 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2424 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 5356836 # ITB inst accesses -system.cpu0.itb.hits 5349242 # DTB hits -system.cpu0.itb.misses 7594 # DTB misses -system.cpu0.itb.accesses 5356836 # DTB accesses -system.cpu0.numCycles 234138431 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 5357388 # ITB inst accesses +system.cpu0.itb.hits 5349776 # DTB hits +system.cpu0.itb.misses 7612 # DTB misses +system.cpu0.itb.accesses 5357388 # DTB accesses +system.cpu0.numCycles 234157878 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 14733348 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 42294638 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7765284 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4637486 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 215157682 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 899672 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 103093 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 978 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1882 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 100153 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1830103 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 127 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 5346345 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 204670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3021 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 232377075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.216391 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.156919 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 14748705 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 42201957 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7736387 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4605452 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 215146781 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 898208 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 106243 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 1405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 1864 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 95051 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1850622 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 5346983 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 204760 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2833 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 232399808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.216000 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.156571 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 222728537 95.85% 95.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 885926 0.38% 96.23% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 959241 0.41% 96.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1030592 0.44% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1233052 0.53% 97.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 718062 0.31% 97.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1129349 0.49% 98.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 448984 0.19% 98.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3243332 1.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 222777653 95.86% 95.86% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 886693 0.38% 96.24% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 957710 0.41% 96.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1031526 0.44% 97.10% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1201262 0.52% 97.61% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 716459 0.31% 97.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1131800 0.49% 98.41% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 450199 0.19% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3246506 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 232377075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.033165 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.180639 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12160999 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 212353937 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6177683 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1309281 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 372986 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 974074 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 78107 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 45045632 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 258698 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 372986 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12774661 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53419035 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 30524585 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6795741 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 128487965 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 43632543 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1343 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 95385189 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 124519108 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 1934134 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 46283925 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 200651385 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 53129662 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 5272 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 36330469 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 9953456 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 576590 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 492282 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 7436987 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7977179 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6240861 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1088795 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1688387 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 41277277 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1012498 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 59014531 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 58753 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 7256631 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 15830718 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 292140 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 232377075 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.253960 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.959343 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 232399808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.033039 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.180229 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12178110 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 212389955 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6147086 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1310186 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 372224 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 973042 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 78155 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 44916036 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 260169 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 372224 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12790792 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 53545394 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 30504571 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6768689 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 128415973 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 43504199 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1378 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 95402427 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 124537502 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1839930 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 46109442 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 200228601 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 53009049 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 5261 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 36340147 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 9769295 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 578634 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 493652 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 7443860 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7970278 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6245265 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1090249 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1688574 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 41187030 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 989826 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 58971927 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 58739 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 7127220 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 15644672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 268943 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 232399808 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.253752 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.958915 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 212079469 91.27% 91.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6238226 2.68% 93.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 2924438 1.26% 95.21% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2416467 1.04% 96.25% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6166815 2.65% 98.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1071194 0.46% 99.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 901941 0.39% 99.75% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 385048 0.17% 99.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 193477 0.08% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 212110796 91.27% 91.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6244814 2.69% 93.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 2921782 1.26% 95.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2401444 1.03% 96.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6174292 2.66% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1067597 0.46% 99.36% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 901998 0.39% 99.75% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 384604 0.17% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 192481 0.08% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 232377075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 232399808 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 114630 2.27% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.27% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4666706 92.48% 94.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 264598 5.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 115073 2.28% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 2 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.28% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4670641 92.37% 94.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 270791 5.36% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 15012 0.03% 0.03% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 25515552 43.24% 43.26% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47770 0.08% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 902 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.34% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 27508063 46.61% 89.96% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5927232 10.04% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 15020 0.03% 0.03% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 25465355 43.18% 43.21% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47791 0.08% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 896 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 27510585 46.65% 89.94% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5932280 10.06% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 59014531 # Type of FU issued -system.cpu0.iq.rate 0.252050 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 5045937 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.085503 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 355498871 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 49563440 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 38260615 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 11956 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6482 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 64039026 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6430 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 226085 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 58971927 # Type of FU issued +system.cpu0.iq.rate 0.251847 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 5056507 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.085744 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 355447115 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 49321417 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 38218166 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 11793 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6394 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5095 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 64007055 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6359 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 225424 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1459518 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2588 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 24632 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 672041 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1448099 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2516 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 24796 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 671952 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17098280 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 3147229 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17102895 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 3149110 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 372986 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 50915247 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1803662 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 42401043 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 79571 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7977179 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6240861 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 734817 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 139591 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1596321 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 24632 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 160350 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 132588 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 292938 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 58604130 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 27345857 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 362682 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 372224 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 50935329 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 1903194 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 42289333 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 78950 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7970278 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6245265 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 710795 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 138182 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 1696089 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 24796 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 159500 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 133057 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 292557 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 58565137 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 27348453 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 359214 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 111268 # number of nop insts executed -system.cpu0.iew.exec_refs 33208867 # number of memory reference insts executed -system.cpu0.iew.exec_branches 5668977 # Number of branches executed -system.cpu0.iew.exec_stores 5863010 # Number of stores executed -system.cpu0.iew.exec_rate 0.250297 # Inst execution rate -system.cpu0.iew.wb_sent 55434698 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 38265806 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 21645924 # num instructions producing a value -system.cpu0.iew.wb_consumers 38521221 # num instructions consuming a value +system.cpu0.iew.exec_nop 112477 # number of nop insts executed +system.cpu0.iew.exec_refs 33216509 # number of memory reference insts executed +system.cpu0.iew.exec_branches 5651382 # Number of branches executed +system.cpu0.iew.exec_stores 5868056 # Number of stores executed +system.cpu0.iew.exec_rate 0.250110 # Inst execution rate +system.cpu0.iew.wb_sent 55395790 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 38223261 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 21614386 # num instructions producing a value +system.cpu0.iew.wb_consumers 38462259 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.163432 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.561922 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.163237 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.561964 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7110536 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 720358 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 248726 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 231246727 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.150700 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 0.849611 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 7051288 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 720883 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 247682 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 231240606 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.150761 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 0.850016 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 218753445 94.60% 94.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6297983 2.72% 97.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1708084 0.74% 98.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1059115 0.46% 98.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 644957 0.28% 98.80% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 581299 0.25% 99.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 449364 0.19% 99.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 245033 0.11% 99.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1507447 0.65% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 218744105 94.60% 94.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6302358 2.73% 97.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1708730 0.74% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1054896 0.46% 98.52% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 648771 0.28% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 578680 0.25% 99.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 445136 0.19% 99.24% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 245162 0.11% 99.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1512768 0.65% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 231246727 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 29059194 # Number of instructions committed -system.cpu0.commit.committedOps 34848810 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 231240606 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 29065490 # Number of instructions committed +system.cpu0.commit.committedOps 34862084 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 12086481 # Number of memory references committed -system.cpu0.commit.loads 6517661 # Number of loads committed -system.cpu0.commit.membars 192728 # Number of memory barriers committed -system.cpu0.commit.branches 4958536 # Number of branches committed -system.cpu0.commit.fp_insts 5174 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 30757342 # Number of committed integer instructions. -system.cpu0.commit.function_calls 472350 # Number of function calls committed. +system.cpu0.commit.refs 12095492 # Number of memory references committed +system.cpu0.commit.loads 6522179 # Number of loads committed +system.cpu0.commit.membars 193065 # Number of memory barriers committed +system.cpu0.commit.branches 4958543 # Number of branches committed +system.cpu0.commit.fp_insts 5094 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 30770331 # Number of committed integer instructions. +system.cpu0.commit.function_calls 472637 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 22717072 65.19% 65.19% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 44355 0.13% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.31% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 902 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.32% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 6517661 18.70% 84.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5568820 15.98% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 22721291 65.17% 65.17% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 44405 0.13% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 65.30% # 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# Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 896 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.30% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 6522179 18.71% 84.01% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5573313 15.99% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 34848810 # Class of committed instruction -system.cpu0.commit.bw_lim_events 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due to idling +system.cpu0.quiesceCycles 2270312982 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 28998871 # Number of Instructions Simulated +system.cpu0.committedOps 34795465 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 8.074724 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 8.074724 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.123843 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.123843 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 66418764 # number of integer regfile reads +system.cpu0.int_regfile_writes 24158486 # number of integer regfile writes +system.cpu0.fp_regfile_reads 44743 # number of floating regfile reads +system.cpu0.fp_regfile_writes 41780 # number of floating regfile writes +system.cpu0.cc_regfile_reads 196661933 # number of cc regfile reads +system.cpu0.cc_regfile_writes 15655112 # number of cc regfile writes +system.cpu0.misc_regfile_reads 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cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 644366504 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1452134760 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73471759 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72597010 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146068769 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 245146 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 312940 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 558086 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 288390 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 344749 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 633139 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1730710058 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2210787235 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3941497293 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4783325934 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6576818347 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11360144281 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 814553760 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 636336252 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1450890012 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72971510 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 72018008 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 144989518 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6512520709 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8761115820 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15273636529 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7320288965 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9405482324 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 16725771289 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91407551750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90929310002 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336861752 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11972132389 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14721058995 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693191384 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103379684139 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105650368997 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030053136 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021369 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026985 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024274 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023230 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025353 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 11000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6514035992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8787605582 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15301641574 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7328589752 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9423941834 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16752531586 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91416176750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90920349500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182336526250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 11961680895 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 14731919998 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26693600893 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 103377857645 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 105652269498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 209030127143 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021478 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026880 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024273 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023225 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025359 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024343 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394263 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.379732 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.387919 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049205 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044389 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046575 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.394041 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.380095 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.388007 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.049209 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.044211 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046483 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000018 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022191 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026253 # mshr miss rate for demand accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000007 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.022250 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026198 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.024304 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025837 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028734 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027343 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13121.213506 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12489.933351 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12758.200586 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42365.006248 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48117.976864 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45506.053870 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18787.929851 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20081.855705 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19340.908619 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12813.351761 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11667.793314 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12217.193794 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028660 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027342 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13104.391259 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.451818 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12746.950442 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42302.241291 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 48430.179286 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45645.984052 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 18836.226066 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20004.912195 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19331.539206 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12703.953691 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11634.573183 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12149.280878 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26637.928645 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27918.447154 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27357.694206 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25463.911774 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27191.490914 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26407.375234 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26572.067225 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 28080.800096 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27418.071003 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25412.080003 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 27335.661116 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26459.484546 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1709,15 +1740,15 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8288231 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6165176 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 342380 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5156418 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4057157 # Number of BTB hits +system.cpu1.branchPred.lookups 8293404 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6173471 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 340831 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5168505 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4065400 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 78.681693 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 881950 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 23449 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 78.657175 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 881063 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 23561 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1741,25 +1772,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 28293531 # DTB read hits -system.cpu1.dtb.read_misses 40544 # DTB read misses -system.cpu1.dtb.write_hits 6190636 # DTB write hits -system.cpu1.dtb.write_misses 14491 # DTB write misses +system.cpu1.dtb.read_hits 28281448 # DTB read hits +system.cpu1.dtb.read_misses 40913 # DTB read misses +system.cpu1.dtb.write_hits 6183126 # DTB write hits +system.cpu1.dtb.write_misses 14267 # DTB write misses system.cpu1.dtb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5400 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 865 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 285 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5407 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 858 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 723 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 28334075 # DTB read accesses -system.cpu1.dtb.write_accesses 6205127 # DTB write accesses +system.cpu1.dtb.perms_faults 709 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 28322361 # DTB read accesses +system.cpu1.dtb.write_accesses 6197393 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 34484167 # DTB hits -system.cpu1.dtb.misses 55035 # DTB misses -system.cpu1.dtb.accesses 34539202 # DTB accesses +system.cpu1.dtb.hits 34464574 # DTB hits +system.cpu1.dtb.misses 55180 # DTB misses +system.cpu1.dtb.accesses 34519754 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1781,124 +1812,124 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 5693555 # ITB inst hits -system.cpu1.itb.inst_misses 8207 # ITB inst misses +system.cpu1.itb.inst_hits 5686404 # ITB inst hits +system.cpu1.itb.inst_misses 8235 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 506 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 708 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 713 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 32 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2675 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2681 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 2702 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 2705 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5701762 # ITB inst accesses -system.cpu1.itb.hits 5693555 # DTB hits -system.cpu1.itb.misses 8207 # DTB misses -system.cpu1.itb.accesses 5701762 # DTB accesses -system.cpu1.numCycles 237058963 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5694639 # ITB inst accesses +system.cpu1.itb.hits 5686404 # DTB hits +system.cpu1.itb.misses 8235 # DTB misses +system.cpu1.itb.accesses 5694639 # DTB accesses +system.cpu1.numCycles 237046957 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15389347 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 44896719 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8288231 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4939107 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 217242159 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 949095 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 106364 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 1987 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 1943 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 92979 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 2091650 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5690360 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 215494 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3361 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 235400962 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.228809 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.188674 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15347817 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 44890949 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8293404 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4946463 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 217272167 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 945647 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 107708 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 1915 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 1869 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 102411 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 2087291 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 117 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5683206 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 214159 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3400 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 235393992 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.228723 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.188286 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 225085908 95.62% 95.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 947634 0.40% 96.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1047135 0.44% 96.47% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1048515 0.45% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1240998 0.53% 97.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 829745 0.35% 97.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1296822 0.55% 98.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 452969 0.19% 98.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3451236 1.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 225080067 95.62% 95.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 947919 0.40% 96.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1046635 0.44% 96.47% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1047767 0.45% 96.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1244626 0.53% 97.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 829831 0.35% 97.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1297650 0.55% 98.34% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 454057 0.19% 98.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3445440 1.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 235400962 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.034963 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.189391 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 12590716 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 214453384 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 6500032 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1465156 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 389454 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1047596 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 86470 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 48240012 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 288766 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 389454 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 13272686 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 54002992 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 31282477 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7201814 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 129249426 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 46761611 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 1258 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 95572539 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 124561907 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 2450017 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 49620172 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 215588900 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 57377506 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 4944 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 39615169 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 10004995 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 609511 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 515718 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8221045 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 8459299 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6818667 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033426 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1557443 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 44314605 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1045489 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 62743783 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 61525 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 7205140 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 16025571 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 281591 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 235400962 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.266540 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.981476 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 235393992 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.034986 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.189376 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 12555511 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 214484659 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 6498538 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1464859 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 388308 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1045918 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85921 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 48232824 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 288029 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 388308 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 13237235 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 54097542 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 31323893 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7199069 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 129145928 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 46754074 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1435 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 95558668 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 124530529 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 2374363 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 49626992 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 215510826 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 57366811 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 4976 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 39600958 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 10026026 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 608668 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 515191 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8234978 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 8452340 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6808261 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1032874 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1526046 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 44303656 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1049317 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 62721282 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 61124 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 7218810 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16029580 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 286052 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 235393992 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.266452 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.981415 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 213793871 90.82% 90.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6637383 2.82% 93.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3199231 1.36% 95.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2579548 1.10% 96.10% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6422119 2.73% 98.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1152982 0.49% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1001630 0.43% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 407456 0.17% 99.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 206742 0.09% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 213794873 90.82% 90.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6639662 2.82% 93.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3193505 1.36% 95.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2580445 1.10% 96.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6412648 2.72% 98.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1155018 0.49% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1003845 0.43% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 407445 0.17% 99.91% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 206551 0.09% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 235400962 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 235393992 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 146491 2.81% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 1 0.00% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 146677 2.81% 2.81% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 3 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 2.81% # attempts to use FU when none available @@ -1926,184 +1957,184 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 2.81% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.81% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 2.81% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4788852 91.80% 94.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 281237 5.39% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4785763 91.77% 94.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 282272 5.41% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 13506 0.02% 0.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 27516436 43.86% 43.88% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46370 0.07% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1209 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 28654021 45.67% 89.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6512241 10.38% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 13498 0.02% 0.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 27514443 43.87% 43.89% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46382 0.07% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.96% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1213 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.97% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 28642016 45.67% 89.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6503730 10.37% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 62743783 # Type of FU issued -system.cpu1.iq.rate 0.264676 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 5216581 # FU busy when requested +system.cpu1.iq.FU_type_0::total 62721282 # Type of FU issued +system.cpu1.iq.rate 0.264594 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 5214715 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.083141 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 366155152 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 52582376 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41291326 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 11482 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6074 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5054 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67940659 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6199 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 226253 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_inst_queue_reads 366100496 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 52588764 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41277568 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11899 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6202 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5156 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 67916046 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 226153 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 1460814 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2639 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 24306 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 652998 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 1459547 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2673 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 24270 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 647934 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 17101900 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3881798 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 17097171 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3878321 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 389454 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 50160792 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 3093797 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 45494090 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 85835 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 8459299 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6818667 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 741438 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 149727 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2862513 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 24306 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 166054 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 139765 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 305819 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 62318890 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 28486625 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 369994 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 388308 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 50150951 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 3201381 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 45487056 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 83691 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 8452340 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6808261 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 746320 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 150012 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 2969807 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 24270 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165680 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 138748 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 304428 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 62296746 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 28474223 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 369499 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 133996 # number of nop insts executed -system.cpu1.iew.exec_refs 34929125 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6064585 # Number of branches executed -system.cpu1.iew.exec_stores 6442500 # Number of stores executed -system.cpu1.iew.exec_rate 0.262884 # Inst execution rate -system.cpu1.iew.wb_sent 58464614 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41296380 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 23329556 # num instructions producing a value -system.cpu1.iew.wb_consumers 41830645 # num instructions consuming a value +system.cpu1.iew.exec_nop 134083 # number of nop insts executed +system.cpu1.iew.exec_refs 34908741 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6065757 # Number of branches executed +system.cpu1.iew.exec_stores 6434518 # Number of stores executed +system.cpu1.iew.exec_rate 0.262803 # Inst execution rate +system.cpu1.iew.wb_sent 58446379 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41282724 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 23334628 # num instructions producing a value +system.cpu1.iew.wb_consumers 41837805 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.174203 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.557714 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.174154 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.557740 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 7169441 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 763898 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 257160 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 234250313 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.162130 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 0.884909 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 7166738 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 763265 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 256189 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 234203986 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.162086 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 0.884581 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 220821840 94.27% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6746509 2.88% 97.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1771690 0.76% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1085849 0.46% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 731494 0.31% 98.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 648369 0.28% 98.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 505518 0.22% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 281725 0.12% 99.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1657319 0.71% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 220778060 94.27% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6743716 2.88% 97.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1772623 0.76% 97.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1087484 0.46% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 731864 0.31% 98.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 647370 0.28% 98.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 507514 0.22% 99.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 282341 0.12% 99.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1653014 0.71% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 234250313 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 31416794 # Number of instructions committed -system.cpu1.commit.committedOps 37978992 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 234203986 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 31407169 # Number of instructions committed +system.cpu1.commit.committedOps 37961303 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13164154 # Number of memory references committed -system.cpu1.commit.loads 6998485 # Number of loads committed -system.cpu1.commit.membars 211048 # Number of memory barriers committed -system.cpu1.commit.branches 5351716 # Number of branches committed -system.cpu1.commit.fp_insts 5038 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33506635 # Number of committed integer instructions. -system.cpu1.commit.function_calls 519749 # Number of function calls committed. +system.cpu1.commit.refs 13153120 # Number of memory references committed +system.cpu1.commit.loads 6992793 # Number of loads committed +system.cpu1.commit.membars 210663 # Number of memory barriers committed +system.cpu1.commit.branches 5351172 # Number of branches committed +system.cpu1.commit.fp_insts 5118 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33489601 # Number of committed integer instructions. +system.cpu1.commit.function_calls 519360 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 24770094 65.22% 65.22% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 43535 0.11% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 1209 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.34% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 6998485 18.43% 83.77% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6165669 16.23% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 24763487 65.23% 65.23% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 43483 0.11% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 1213 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 6992793 18.42% 83.77% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6160327 16.23% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 37978992 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1657319 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 37961303 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1653014 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 276790751 # The number of ROB reads -system.cpu1.rob.rob_writes 91451122 # The number of ROB writes -system.cpu1.timesIdled 270857 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1658001 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2279071980 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 31333111 # Number of Instructions Simulated -system.cpu1.committedOps 37895309 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 7.565765 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 7.565765 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.132174 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.132174 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 71132794 # number of integer regfile reads -system.cpu1.int_regfile_writes 26016814 # number of integer regfile writes -system.cpu1.fp_regfile_reads 44316 # number of floating regfile reads -system.cpu1.fp_regfile_writes 42056 # number of floating regfile writes -system.cpu1.cc_regfile_reads 209312794 # number of cc regfile reads -system.cpu1.cc_regfile_writes 17049814 # number of cc regfile writes -system.cpu1.misc_regfile_reads 299103919 # number of misc regfile reads -system.cpu1.misc_regfile_writes 609097 # number of misc regfile writes +system.cpu1.rob.rob_reads 276729293 # The number of ROB reads +system.cpu1.rob.rob_writes 91408516 # The number of ROB writes +system.cpu1.timesIdled 270232 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 1652965 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2279190242 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 31323407 # Number of Instructions Simulated +system.cpu1.committedOps 37877541 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 7.567726 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 7.567726 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.132140 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.132140 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 71111518 # number of integer regfile reads +system.cpu1.int_regfile_writes 26004877 # number of integer regfile writes +system.cpu1.fp_regfile_reads 44415 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42120 # number of floating regfile writes +system.cpu1.cc_regfile_reads 209232786 # number of cc regfile reads +system.cpu1.cc_regfile_writes 17062784 # number of cc regfile writes +system.cpu1.misc_regfile_reads 298304880 # number of misc regfile reads +system.cpu1.misc_regfile_writes 608841 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2120,17 +2151,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1732377463327 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732377463327 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1732377463327 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1732753268848 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1732753268848 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1732753268848 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83365 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83356 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 936db738a..231f5f650 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,159 +1,147 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.626162 # Number of seconds simulated -sim_ticks 2626161554000 # Number of ticks simulated -final_tick 2626161554000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.627904 # Number of seconds simulated +sim_ticks 2627903712000 # Number of ticks simulated +final_tick 2627903712000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 476066 # Simulator instruction rate (inst/s) -host_op_rate 568569 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 20761634862 # Simulator tick rate (ticks/s) -host_mem_usage 472496 # Number of bytes of host memory used -host_seconds 126.49 # Real time elapsed on the host -sim_insts 60218144 # Number of instructions simulated -sim_ops 71918894 # Number of ops (including micro ops) simulated +host_inst_rate 497056 # Simulator instruction rate (inst/s) +host_op_rate 593637 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21691918305 # Simulator tick rate (ticks/s) +host_mem_usage 460332 # Number of bytes of host memory used +host_seconds 121.15 # Real time elapsed on the host +sim_insts 60216663 # Number of instructions simulated +sim_ops 71917112 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 124256256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 306888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4490328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 306056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4559448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 399040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4560448 # Number of bytes read from this memory -system.physmem.bytes_read::total 134013152 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 306888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 399040 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.inst 399872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4486720 # Number of bytes read from this memory +system.physmem.bytes_read::total 134008544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 306056 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 399872 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 705928 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677952 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1536620 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 1479452 # Number of bytes written to this memory -system.physmem.bytes_written::total 6694024 # Number of bytes written to this memory +system.physmem.bytes_written::writebacks 3673856 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1536536 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 1479536 # Number of bytes written to this memory +system.physmem.bytes_written::total 6689928 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15532032 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11007 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 70187 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 71267 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 71257 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15690721 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57468 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 384155 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 369863 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811486 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47314780 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 6248 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 70105 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15690649 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57404 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 384134 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 369884 # Number of write requests responded to by this memory +system.physmem.num_writes::total 811422 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47283413 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 116858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1709845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 116464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1735013 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 151948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1736545 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51030049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 116858 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 151948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 268806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1400505 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 585120 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 563351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2548976 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1400505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47314780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 152164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1707338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50994465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 116464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 152164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 268628 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1398018 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 584700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 563010 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2545728 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1398018 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47283413 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 116858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2294965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 116464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2319714 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 151948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2299897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53579025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15690721 # Number of read requests accepted -system.physmem.writeReqs 811486 # Number of write requests accepted -system.physmem.readBursts 15690721 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 811486 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1004205504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue -system.physmem.bytesWritten 6711360 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134013152 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6694024 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 706602 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4522 # Number of requests that are neither read nor write +system.physmem.bw_total::cpu1.inst 152164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2270348 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53540193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15690649 # Number of read requests accepted +system.physmem.writeReqs 811422 # Number of write requests accepted +system.physmem.readBursts 15690649 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 811422 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1004200960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 6711168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134008544 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6689928 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 706554 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4516 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 980414 # Per bank write bursts -system.physmem.perBankRdBursts::1 980046 # Per bank write bursts -system.physmem.perBankRdBursts::2 979991 # Per bank write bursts +system.physmem.perBankRdBursts::1 980044 # Per bank write bursts +system.physmem.perBankRdBursts::2 979984 # Per bank write bursts system.physmem.perBankRdBursts::3 980262 # Per bank write bursts system.physmem.perBankRdBursts::4 986671 # Per bank write bursts system.physmem.perBankRdBursts::5 980424 # Per bank write bursts -system.physmem.perBankRdBursts::6 980568 # Per bank write bursts +system.physmem.perBankRdBursts::6 980555 # Per bank write bursts system.physmem.perBankRdBursts::7 980428 # Per bank write bursts -system.physmem.perBankRdBursts::8 980784 # Per bank write bursts +system.physmem.perBankRdBursts::8 980781 # Per bank write bursts system.physmem.perBankRdBursts::9 980432 # Per bank write bursts system.physmem.perBankRdBursts::10 979731 # Per bank write bursts -system.physmem.perBankRdBursts::11 979594 # Per bank write bursts -system.physmem.perBankRdBursts::12 980346 # Per bank write bursts -system.physmem.perBankRdBursts::13 980257 # Per bank write bursts +system.physmem.perBankRdBursts::11 979566 # Per bank write bursts +system.physmem.perBankRdBursts::12 980337 # Per bank write bursts +system.physmem.perBankRdBursts::13 980248 # Per bank write bursts system.physmem.perBankRdBursts::14 980396 # Per bank write bursts system.physmem.perBankRdBursts::15 980367 # Per bank write bursts -system.physmem.perBankWrBursts::0 6649 # Per bank write bursts -system.physmem.perBankWrBursts::1 6328 # Per bank write bursts -system.physmem.perBankWrBursts::2 6318 # Per bank write bursts +system.physmem.perBankWrBursts::0 6669 # Per bank write bursts +system.physmem.perBankWrBursts::1 6337 # Per bank write bursts +system.physmem.perBankWrBursts::2 6309 # Per bank write bursts system.physmem.perBankWrBursts::3 6427 # Per bank write bursts -system.physmem.perBankWrBursts::4 6389 # Per bank write bursts -system.physmem.perBankWrBursts::5 6673 # Per bank write bursts -system.physmem.perBankWrBursts::6 6856 # Per bank write bursts -system.physmem.perBankWrBursts::7 6766 # Per bank write bursts -system.physmem.perBankWrBursts::8 7040 # Per bank write bursts -system.physmem.perBankWrBursts::9 6684 # Per bank write bursts -system.physmem.perBankWrBursts::10 6144 # Per bank write bursts -system.physmem.perBankWrBursts::11 6041 # Per bank write bursts -system.physmem.perBankWrBursts::12 6664 # Per bank write bursts -system.physmem.perBankWrBursts::13 6480 # Per bank write bursts -system.physmem.perBankWrBursts::14 6708 # Per bank write bursts -system.physmem.perBankWrBursts::15 6698 # Per bank write bursts +system.physmem.perBankWrBursts::4 6393 # Per bank write bursts +system.physmem.perBankWrBursts::5 6675 # Per bank write bursts +system.physmem.perBankWrBursts::6 6845 # Per bank write bursts +system.physmem.perBankWrBursts::7 6769 # Per bank write bursts +system.physmem.perBankWrBursts::8 7058 # Per bank write bursts +system.physmem.perBankWrBursts::9 6682 # Per bank write bursts +system.physmem.perBankWrBursts::10 6146 # Per bank write bursts +system.physmem.perBankWrBursts::11 6016 # Per bank write bursts +system.physmem.perBankWrBursts::12 6658 # Per bank write bursts +system.physmem.perBankWrBursts::13 6472 # Per bank write bursts +system.physmem.perBankWrBursts::14 6707 # Per bank write bursts +system.physmem.perBankWrBursts::15 6699 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2626157242500 # Total gap between requests +system.physmem.totGap 2627899414000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 6644 # Read request sizes (log2) system.physmem.readPktSize::3 15532042 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 152035 # Read request sizes (log2) +system.physmem.readPktSize::6 151963 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 754018 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 57468 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1139192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 982322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 987642 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1099516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 997956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1065450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2766854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2672571 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3490866 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 121692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 109210 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98650 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 38 # What read queue length does an incoming req see +system.physmem.writePktSize::6 57404 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1139478 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 982369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 987635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1091943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 997696 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1062131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2775683 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2686264 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3513182 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 110777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 100216 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 94857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 91541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18831 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18688 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -169,40 +157,40 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 343 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 345 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 338 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 333 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 329 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 328 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 323 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 318 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 3909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5873 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5857 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5801 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5719 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 3902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5824 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5782 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -233,349 +221,371 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1040256 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 971.796235 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 905.926694 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 203.945376 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22813 2.19% 2.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22914 2.20% 4.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8969 0.86% 5.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2415 0.23% 5.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2270 0.22% 5.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1819 0.17% 5.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9086 0.87% 6.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 877 0.08% 6.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 969093 93.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1040256 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5997 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2616.425880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 48628.845120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-65535 5973 99.60% 99.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::131072-196607 7 0.12% 99.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::196608-262143 4 0.07% 99.78% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1040215 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 971.829985 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 906.043406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 203.863923 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22728 2.18% 2.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22848 2.20% 4.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9187 0.88% 5.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2378 0.23% 5.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2112 0.20% 5.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1712 0.16% 5.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9383 0.90% 6.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 867 0.08% 6.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 969000 93.15% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1040215 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6002 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2614.234255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 48623.103038 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-65535 5977 99.58% 99.58% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::131072-196607 9 0.15% 99.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-262143 3 0.05% 99.78% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::393216-458751 2 0.03% 99.82% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::589824-655359 1 0.02% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::786432-851967 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::983040-1.04858e+06 1 0.02% 99.87% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.17965e+06-1.24518e+06 7 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.37626e+06-1.44179e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5997 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5997 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.486243 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.330739 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.155795 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1 3 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 3 0.05% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 4 0.07% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 5 0.08% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 8 0.13% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::6 1 0.02% 0.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 4 0.07% 0.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 6 0.10% 0.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::10 3 0.05% 0.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::11 2 0.03% 0.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 3 0.05% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::13 2 0.03% 0.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 11 0.18% 0.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2055 34.27% 35.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.50% 35.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3613 60.25% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 37 0.62% 96.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 21 0.35% 96.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 16 0.27% 97.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.23% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.30% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.22% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 29 0.48% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 18 0.30% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 15 0.25% 98.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 9 0.15% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 11 0.18% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 15 0.25% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 16 0.27% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 11 0.18% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5997 # Writes before turning the bus around for reads -system.physmem.totQLat 404022182250 # Total ticks spent queuing -system.physmem.totMemAccLat 698223013500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78453555000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25749.13 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6002 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6002 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.471176 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.313667 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.128575 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 4 0.07% 0.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 1 0.02% 0.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 5 0.08% 0.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 9 0.15% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 6 0.10% 0.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::6 1 0.02% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 2 0.03% 0.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8 2 0.03% 0.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 6 0.10% 0.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::10 3 0.05% 0.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.03% 0.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.03% 0.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::13 2 0.03% 0.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::14 2 0.03% 0.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 12 0.20% 0.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2065 34.41% 35.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 28 0.47% 35.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3575 59.56% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 74 1.23% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 26 0.43% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 13 0.22% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 8 0.13% 97.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.28% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 20 0.33% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 23 0.38% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 19 0.32% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 14 0.23% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 21 0.35% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.10% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 12 0.20% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 10 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 12 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6002 # Writes before turning the bus around for reads +system.physmem.totQLat 402684411250 # Total ticks spent queuing +system.physmem.totMemAccLat 696883911250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78453200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25663.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44499.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 382.39 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 51.03 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44413.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 382.13 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.55 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 50.99 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.01 # Data bus utilization in percentage system.physmem.busUtilRead 2.99 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.57 # Average read queue length when enqueuing -system.physmem.avgWrQLen 16.75 # Average write queue length when enqueuing -system.physmem.readRowHits 14667428 # Number of row buffer hits during reads -system.physmem.writeRowHits 87892 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.63 # Average write queue length when enqueuing +system.physmem.readRowHits 14667378 # Number of row buffer hits during reads +system.physmem.writeRowHits 87909 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.80 # Row buffer hit rate for writes -system.physmem.avgGap 159139.76 # Average gap between requests +system.physmem.writeRowHitRate 83.83 # Row buffer hit rate for writes +system.physmem.avgGap 159246.64 # Average gap between requests system.physmem.pageHitRate 93.41 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2253794386750 # Time in different power states -system.physmem.memoryStateTime::REF 87693060000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2254944154750 # Time in different power states +system.physmem.memoryStateTime::REF 87751300000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 284666999500 # Time in different power states +system.physmem.memoryStateTime::ACT 285203111500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 54492260 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16743274 # Transaction distribution -system.membus.trans_dist::ReadResp 16743274 # Transaction distribution +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 16743265 # Transaction distribution +system.membus.trans_dist::ReadResp 16743265 # Transaction distribution system.membus.trans_dist::WriteReq 763389 # Transaction distribution system.membus.trans_dist::WriteResp 763389 # Transaction distribution -system.membus.trans_dist::Writeback 57468 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4522 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4522 # Transaction distribution -system.membus.trans_dist::ReadExReq 131560 # Transaction distribution -system.membus.trans_dist::ReadExResp 131560 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383096 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::Writeback 57404 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution +system.membus.trans_dist::ReadExReq 131496 # Transaction distribution +system.membus.trans_dist::ReadExResp 131496 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2383094 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 3860 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4278894 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1891706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4278672 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 31064064 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 31064064 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35342958 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2390558 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 16450920 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 18849222 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 143105478 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 143105478 # Total data (bytes) -system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1225841000 # Layer occupancy (ticks) +system.membus.pkt_count::total 35342736 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2390554 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 7720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16442216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18840514 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143096770 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 213883 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 213883 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 213883 # Request fanout histogram +system.membus.reqLayer0.occupancy 1223591000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3816000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3677500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 18171677500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 18171099000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4988493167 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4987168321 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 38432312250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 38457119250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.5 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 61927 # number of replacements -system.l2c.tags.tagsinuse 50918.981702 # Cycle average of tags in use -system.l2c.tags.total_refs 1698761 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 127310 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.343500 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2574018004500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37920.667518 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000701 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2858.981429 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3190.441154 # Average occupied blocks per requestor +system.l2c.tags.replacements 61855 # number of replacements +system.l2c.tags.tagsinuse 50930.330896 # Cycle average of tags in use +system.l2c.tags.total_refs 1699074 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 127234 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.353931 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2574032162000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 37932.108407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000700 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2848.249708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3170.076160 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.000187 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4136.744409 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2812.146305 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.578623 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 4147.610246 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2832.285487 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.578798 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.043625 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.048682 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.043461 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.048372 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.063122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.042910 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.776962 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65383 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2167 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6500 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56664 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.997665 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17277278 # Number of tag accesses -system.l2c.tags.data_accesses 17277278 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 9702 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 462087 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 188003 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 9966 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3602 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 382555 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 182697 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1242114 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 596521 # number of Writeback hits -system.l2c.Writeback_hits::total 596521 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 15 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits +system.l2c.tags.occ_percent::cpu1.inst 0.063288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.043217 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.777135 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65379 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6516 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56686 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.997604 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17278829 # Number of tag accesses +system.l2c.tags.data_accesses 17278829 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 9065 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3142 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 447117 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 182266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 10696 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4002 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 397485 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 188475 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1242248 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596597 # number of Writeback hits +system.l2c.Writeback_hits::total 596597 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 60509 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53980 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114489 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 9702 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 462087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 248512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 9966 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3602 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 382555 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 236677 # number of demand (read+write) hits -system.l2c.demand_hits::total 1356603 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 9702 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 462087 # number of overall hits -system.l2c.overall_hits::cpu0.data 248512 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 9966 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3602 # number of overall hits -system.l2c.overall_hits::cpu1.inst 382555 # number of overall hits -system.l2c.overall_hits::cpu1.data 236677 # number of overall hits -system.l2c.overall_hits::total 1356603 # number of overall hits +system.l2c.ReadExReq_hits::cpu0.data 57734 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 56826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114560 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 9065 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 447117 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 240000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 10696 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4002 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 397485 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 245301 # number of demand (read+write) hits +system.l2c.demand_hits::total 1356808 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 9065 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3142 # number of overall hits +system.l2c.overall_hits::cpu0.inst 447117 # number of overall hits +system.l2c.overall_hits::cpu0.data 240000 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 10696 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4002 # number of overall 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of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 4381 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 70989 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 4368 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 71960 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6235 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 72072 # number of demand (read+write) misses -system.l2c.demand_misses::total 153680 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6248 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 71025 # number of demand (read+write) misses +system.l2c.demand_misses::total 153604 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses 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miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.173792 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56443.107173 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57007.857048 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56730.347172 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.647989 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.869565 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56809.298126 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56830.198795 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 56819.769418 # average ReadExReq mshr miss latency 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mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57136.396376 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 57026.568502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57174.669764 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57162.672463 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -723,45 +733,57 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 52868072 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2471434 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2471434 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2471648 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2471648 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 763389 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 763389 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 596521 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2903 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2903 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 247694 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 247694 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725408 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5753877 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20010 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 49988 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 7549283 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54763036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83799850 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 78676 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 138669986 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 138669986 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 170112 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4808749000 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::Writeback 596597 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2901 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2901 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 247697 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 247697 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1725344 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 5754019 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20105 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50232 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 7549700 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 54760476 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 83807014 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 28584 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 79048 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 138675122 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 18167 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2128077 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 2128077 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2128077 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 4809198500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3866196743 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3866085496 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4420580083 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4420737429 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12904000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 12959000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30319250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30470250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48225066 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 16715396 # Transaction distribution -system.iobus.trans_dist::ReadResp 16715396 # Transaction distribution +system.iobus.trans_dist::ReadReq 16715395 # Transaction distribution +system.iobus.trans_dist::ReadResp 16715395 # Transaction distribution system.iobus.trans_dist::WriteReq 8184 # Transaction distribution system.iobus.trans_dist::WriteResp 8184 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30038 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7948 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 536 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1044 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -783,41 +805,40 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2383096 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2383094 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 31064064 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 31064064 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33447160 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2390558 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 126646814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 126646814 # Total data (bytes) +system.iobus.pkt_count::total 33447158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 39333 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 15892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 1072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2088 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2390554 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.clcd.dma::total 124256256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 126646810 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21111000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 3979000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 3978000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 536000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -861,11 +882,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15532032000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374912000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 15532032000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374910000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 39164946750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 39130786750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -890,25 +911,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6652404 # DTB read hits -system.cpu0.dtb.read_misses 6867 # DTB read misses -system.cpu0.dtb.write_hits 5702862 # DTB write hits -system.cpu0.dtb.write_misses 1758 # DTB write misses -system.cpu0.dtb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 6554416 # DTB read hits +system.cpu0.dtb.read_misses 6570 # DTB read misses +system.cpu0.dtb.write_hits 5649486 # DTB write hits +system.cpu0.dtb.write_misses 1771 # DTB write misses +system.cpu0.dtb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 6327 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 6094 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 129 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 127 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 214 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6659271 # DTB read accesses -system.cpu0.dtb.write_accesses 5704620 # DTB write accesses +system.cpu0.dtb.perms_faults 206 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6560986 # DTB read accesses +system.cpu0.dtb.write_accesses 5651257 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12355266 # DTB hits -system.cpu0.dtb.misses 8625 # DTB misses -system.cpu0.dtb.accesses 12363891 # DTB accesses +system.cpu0.dtb.hits 12203902 # DTB hits +system.cpu0.dtb.misses 8341 # DTB misses +system.cpu0.dtb.accesses 12212243 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -930,162 +951,162 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 30639417 # ITB inst hits -system.cpu0.itb.inst_misses 3605 # ITB inst misses +system.cpu0.itb.inst_hits 30237068 # ITB inst hits +system.cpu0.itb.inst_misses 3286 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 727 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2770 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 701 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 28 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2575 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 30643022 # ITB inst accesses -system.cpu0.itb.hits 30639417 # DTB hits -system.cpu0.itb.misses 3605 # DTB misses -system.cpu0.itb.accesses 30643022 # DTB accesses -system.cpu0.numCycles 2625139831 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30240354 # ITB inst accesses +system.cpu0.itb.hits 30237068 # DTB hits +system.cpu0.itb.misses 3286 # DTB misses +system.cpu0.itb.accesses 30240354 # DTB accesses +system.cpu0.numCycles 2626678485 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30062808 # Number of instructions committed -system.cpu0.committedOps 36081752 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 32258130 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5851 # Number of float alu accesses -system.cpu0.num_func_calls 1105626 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3807715 # number of instructions that are conditional controls -system.cpu0.num_int_insts 32258130 # number of integer instructions -system.cpu0.num_fp_insts 5851 # number of float instructions -system.cpu0.num_int_register_reads 58404320 # number of times the integer registers were read -system.cpu0.num_int_register_writes 21560333 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4184 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1670 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 129650201 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 14353458 # number of times the CC registers were written -system.cpu0.num_mem_refs 12793226 # number of memory refs -system.cpu0.num_load_insts 6826552 # Number of load instructions -system.cpu0.num_store_insts 5966674 # Number of store instructions -system.cpu0.num_idle_cycles 2291568668.895058 # Number of idle cycles -system.cpu0.num_busy_cycles 333571162.104942 # Number of busy cycles -system.cpu0.not_idle_fraction 0.127068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.872932 # Percentage of idle cycles -system.cpu0.Branches 5192489 # Number of branches fetched -system.cpu0.op_class::No_OpClass 12678 0.03% 0.03% # Class of executed instruction -system.cpu0.op_class::IntAlu 23764768 64.90% 64.94% # Class of executed instruction -system.cpu0.op_class::IntMult 45316 0.12% 65.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1041 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.06% # Class of executed instruction -system.cpu0.op_class::MemRead 6826552 18.64% 83.71% # Class of executed instruction -system.cpu0.op_class::MemWrite 5966674 16.29% 100.00% # Class of executed instruction +system.cpu0.committedInsts 29654606 # Number of instructions committed +system.cpu0.committedOps 35595186 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 31825632 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5298 # Number of float alu accesses +system.cpu0.num_func_calls 1084226 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 3738020 # number of instructions that are conditional controls +system.cpu0.num_int_insts 31825632 # number of integer instructions +system.cpu0.num_fp_insts 5298 # number of float instructions +system.cpu0.num_int_register_reads 57689563 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21244985 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3888 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1412 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 127837061 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 14183382 # number of times the CC registers were written +system.cpu0.num_mem_refs 12632580 # number of memory refs +system.cpu0.num_load_insts 6723962 # Number of load instructions +system.cpu0.num_store_insts 5908618 # Number of store instructions +system.cpu0.num_idle_cycles 2294291978.637380 # Number of idle cycles +system.cpu0.num_busy_cycles 332386506.362621 # Number of busy cycles +system.cpu0.not_idle_fraction 0.126543 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.873457 # Percentage of idle cycles +system.cpu0.Branches 5094853 # Number of branches fetched +system.cpu0.op_class::No_OpClass 11433 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 23427860 64.87% 64.90% # Class of executed instruction +system.cpu0.op_class::IntMult 44876 0.12% 65.02% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 988 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 65.02% # Class of executed instruction +system.cpu0.op_class::MemRead 6723962 18.62% 83.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 5908618 16.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 36617029 # Class of executed instruction +system.cpu0.op_class::total 36117737 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 83036 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 856376 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.872089 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 60655440 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 856888 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 70.785727 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 19833794250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 155.467241 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 355.404848 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.303647 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.694150 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997797 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 856352 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.872863 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 60653974 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 856864 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 70.785999 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 19832593000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 151.975513 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 358.897350 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.296827 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.700971 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997799 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 268 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 266 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 62369216 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 62369216 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 30172107 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 30483333 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 60655440 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 30172107 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 30483333 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 60655440 # number of demand (read+write) hits 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62367702 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 62367702 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 29784788 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 30869186 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 60653974 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29784788 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 30869186 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 60653974 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29784788 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 30869186 # number of overall hits +system.cpu0.icache.overall_hits::total 60653974 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 452280 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 404584 # number of ReadReq misses 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accesses system.cpu0.icache.demand_miss_rate::total 0.013930 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015252 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012619 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014958 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.012937 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013930 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13599.567191 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13988.578023 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13776.428183 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13599.567191 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13988.578023 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13776.428183 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13599.567191 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13988.578023 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13776.428183 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13608.703120 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.129632 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13771.330393 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13771.330393 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13608.703120 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13953.129632 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13771.330393 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1094,177 +1115,177 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467310 # number of ReadReq MSHR misses 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percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 154.066297 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 357.809909 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.300911 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.698847 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 151.360555 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 360.515733 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.295626 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.704132 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999758 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 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accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 129861 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 117956 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247817 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11018373 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 10760740 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21779113 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11114795 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 10848702 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21963497 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025416 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.025844 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.025628 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025035 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.024914 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.024975 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.547022 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.539358 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.543366 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.049277 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.042769 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 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WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 4822 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2743 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 2602 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 5345 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2743 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 2602 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 5345 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 143380 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 152210 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 295590 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 125540 # number of WriteReq MSHR misses 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546188 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 307203 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 312541 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 619744 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 1717602000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1764563500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3482165500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5365627921 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5380262063 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10745889984 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 643406250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 581822500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1225228750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 69708250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67035000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 136743250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7083229921 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 7144825563 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 14228055484 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7726636171 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 7726648063 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15453284234 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91635621250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90440418250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182076039500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 13169946836 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 13069221001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 26239167837 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 104805568086 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 103509639251 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 208315207337 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024990 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.025588 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.024427 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.024582 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024505 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.405988 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.391579 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.398948 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.048503 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.043758 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.046177 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024724 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025433 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025079 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028001 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028434 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028218 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11979.369508 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11592.953814 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11780.390067 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 42740.384905 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 43022.134234 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42880.988611 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16806.578638 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16494.840246 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16657.087797 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11375.367167 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12612.417686 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11949.947566 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26339.543065 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25768.662677 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26049.740170 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25151.564832 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24722.030271 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24934.947711 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1401,25 +1422,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6516178 # DTB read hits -system.cpu1.dtb.read_misses 7066 # DTB read misses -system.cpu1.dtb.write_hits 5531450 # DTB write hits -system.cpu1.dtb.write_misses 1844 # DTB write misses -system.cpu1.dtb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 6613806 # DTB read hits +system.cpu1.dtb.read_misses 7420 # DTB read misses +system.cpu1.dtb.write_hits 5584575 # DTB write hits +system.cpu1.dtb.write_misses 1868 # DTB write misses +system.cpu1.dtb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 6501 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 6816 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 152 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 238 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6523244 # DTB read accesses -system.cpu1.dtb.write_accesses 5533294 # DTB write accesses +system.cpu1.dtb.perms_faults 246 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 6621226 # DTB read accesses +system.cpu1.dtb.write_accesses 5586443 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 12047628 # DTB hits -system.cpu1.dtb.misses 8910 # DTB misses -system.cpu1.dtb.accesses 12056538 # DTB accesses +system.cpu1.dtb.hits 12198381 # DTB hits +system.cpu1.dtb.misses 9288 # DTB misses +system.cpu1.dtb.accesses 12207669 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1441,87 +1462,87 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 30872911 # ITB inst hits -system.cpu1.itb.inst_misses 3673 # ITB inst misses +system.cpu1.itb.inst_hits 31273770 # ITB inst hits +system.cpu1.itb.inst_misses 4023 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2489 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 2491 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 712 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2794 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 738 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 35 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 3046 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 30876584 # ITB inst accesses -system.cpu1.itb.hits 30872911 # DTB hits -system.cpu1.itb.misses 3673 # DTB misses -system.cpu1.itb.accesses 30876584 # DTB accesses -system.cpu1.numCycles 2627183277 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 31277793 # ITB inst accesses +system.cpu1.itb.hits 31273770 # DTB hits +system.cpu1.itb.misses 4023 # DTB misses +system.cpu1.itb.accesses 31277793 # DTB accesses +system.cpu1.numCycles 2629128939 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 30155336 # Number of instructions committed -system.cpu1.committedOps 35837142 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 32021976 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 4418 # Number of float alu accesses -system.cpu1.num_func_calls 1035067 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3744201 # number of instructions that are conditional controls -system.cpu1.num_int_insts 32021976 # number of integer instructions -system.cpu1.num_fp_insts 4418 # number of float instructions -system.cpu1.num_int_register_reads 57765753 # number of times the integer registers were read -system.cpu1.num_int_register_writes 21325005 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3309 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1110 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 128250854 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 14653287 # number of times the CC registers were written -system.cpu1.num_mem_refs 12466012 # number of memory refs -system.cpu1.num_load_insts 6694911 # Number of load instructions -system.cpu1.num_store_insts 5771101 # Number of store instructions -system.cpu1.num_idle_cycles 2287259017.662607 # Number of idle cycles -system.cpu1.num_busy_cycles 339924259.337393 # Number of busy cycles -system.cpu1.not_idle_fraction 0.129387 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.870613 # Percentage of idle cycles -system.cpu1.Branches 5118153 # Number of branches fetched -system.cpu1.op_class::No_OpClass 15840 0.04% 0.04% # Class of executed instruction -system.cpu1.op_class::IntAlu 23832212 65.55% 65.59% # Class of executed instruction -system.cpu1.op_class::IntMult 42672 0.12% 65.71% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1070 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.71% # Class of executed instruction -system.cpu1.op_class::MemRead 6694911 18.41% 84.13% # Class of executed instruction -system.cpu1.op_class::MemWrite 5771101 15.87% 100.00% # Class of executed instruction +system.cpu1.committedInsts 30562057 # Number of instructions committed +system.cpu1.committedOps 36321926 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 32452923 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4971 # Number of float alu accesses +system.cpu1.num_func_calls 1056400 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3813741 # number of instructions that are conditional controls +system.cpu1.num_int_insts 32452923 # number of integer instructions +system.cpu1.num_fp_insts 4971 # number of float instructions +system.cpu1.num_int_register_reads 58477662 # number of times the integer registers were read +system.cpu1.num_int_register_writes 21639168 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3605 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1368 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 130057431 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 14822724 # number of times the CC registers were written +system.cpu1.num_mem_refs 12626030 # number of memory refs +system.cpu1.num_load_insts 6797131 # Number of load instructions +system.cpu1.num_store_insts 5828899 # Number of store instructions +system.cpu1.num_idle_cycles 2287592720.742589 # Number of idle cycles +system.cpu1.num_busy_cycles 341536218.257411 # Number of busy cycles +system.cpu1.not_idle_fraction 0.129905 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.870095 # Percentage of idle cycles +system.cpu1.Branches 5215542 # Number of branches fetched +system.cpu1.op_class::No_OpClass 17085 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 24167965 65.58% 65.62% # Class of executed instruction +system.cpu1.op_class::IntMult 43107 0.12% 65.74% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1123 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 65.74% # Class of executed instruction +system.cpu1.op_class::MemRead 6797131 18.44% 84.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 5828899 15.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 36357806 # Class of executed instruction +system.cpu1.op_class::total 36855310 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.iocache.tags.replacements 0 # number of replacements @@ -1540,10 +1561,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1781125703750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1781125703750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1781125703750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1779782747750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1779782747750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1779782747750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index bca94218b..442dd3c07 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.129874 # Number of seconds simulated -sim_ticks 5129873616500 # Number of ticks simulated -final_tick 5129873616500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.129877 # Number of seconds simulated +sim_ticks 5129876981500 # Number of ticks simulated +final_tick 5129876981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 122712 # Simulator instruction rate (inst/s) -host_op_rate 242564 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1543734215 # Simulator tick rate (ticks/s) -host_mem_usage 750608 # Number of bytes of host memory used -host_seconds 3323.03 # Real time elapsed on the host -sim_insts 407773893 # Number of instructions simulated -sim_ops 806048632 # Number of ops (including micro ops) simulated +host_inst_rate 179907 # Simulator instruction rate (inst/s) +host_op_rate 355619 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2263051238 # Simulator tick rate (ticks/s) +host_mem_usage 804092 # Number of bytes of host memory used +host_seconds 2266.80 # Real time elapsed on the host +sim_insts 407812863 # Number of instructions simulated +sim_ops 806114915 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1049344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10817792 # Number of bytes read from this memory -system.physmem.bytes_read::total 11900032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1049344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1049344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6600896 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 4096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10832768 # Number of bytes read from this memory +system.physmem.bytes_read::total 11913792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6597248 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9590976 # Number of bytes written to this memory +system.physmem.bytes_written::total 9587328 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16396 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 169028 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185938 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 103139 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 64 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16378 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 169262 # Number of read requests responded to by this memory +system.physmem.num_reads::total 186153 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 103082 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149859 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149802 # Number of write requests responded to by this memory system.physmem.bw_read::pc.south_bridge.ide 5527 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204556 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2108783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2319751 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204556 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204556 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1286756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 204331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2111701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2322432 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 204331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 204331 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1286044 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::pc.south_bridge.ide 582876 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1869632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1286756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 588403 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204556 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2108783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4189384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185938 # Number of read requests accepted -system.physmem.writeReqs 149859 # Number of write requests accepted -system.physmem.readBursts 185938 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 149859 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11881152 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 9589248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11900032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9590976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_write::total 1868920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1286044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 588402 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 204331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2111701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4191352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 186153 # Number of read requests accepted +system.physmem.writeReqs 149802 # Number of write requests accepted +system.physmem.readBursts 186153 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 149802 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11895360 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18432 # Total number of bytes read from write queue +system.physmem.bytesWritten 9586112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11913792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9587328 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 288 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1710 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11383 # Per bank write bursts -system.physmem.perBankRdBursts::1 10659 # Per bank write bursts -system.physmem.perBankRdBursts::2 11850 # Per bank write bursts -system.physmem.perBankRdBursts::3 11657 # Per bank write bursts -system.physmem.perBankRdBursts::4 11883 # Per bank write bursts -system.physmem.perBankRdBursts::5 11508 # Per bank write bursts -system.physmem.perBankRdBursts::6 11028 # Per bank write bursts -system.physmem.perBankRdBursts::7 11462 # Per bank write bursts -system.physmem.perBankRdBursts::8 11217 # Per bank write bursts -system.physmem.perBankRdBursts::9 11477 # Per bank write bursts -system.physmem.perBankRdBursts::10 11649 # Per bank write bursts -system.physmem.perBankRdBursts::11 12129 # Per bank write bursts -system.physmem.perBankRdBursts::12 11737 # Per bank write bursts -system.physmem.perBankRdBursts::13 12518 # Per bank write bursts -system.physmem.perBankRdBursts::14 12268 # Per bank write bursts -system.physmem.perBankRdBursts::15 11218 # Per bank write bursts -system.physmem.perBankWrBursts::0 10090 # Per bank write bursts -system.physmem.perBankWrBursts::1 9375 # Per bank write bursts -system.physmem.perBankWrBursts::2 9103 # Per bank write bursts -system.physmem.perBankWrBursts::3 8918 # Per bank write bursts -system.physmem.perBankWrBursts::4 9314 # Per bank write bursts -system.physmem.perBankWrBursts::5 9243 # Per bank write bursts -system.physmem.perBankWrBursts::6 8603 # Per bank write bursts -system.physmem.perBankWrBursts::7 8925 # Per bank write bursts -system.physmem.perBankWrBursts::8 9240 # Per bank write bursts -system.physmem.perBankWrBursts::9 9268 # Per bank write bursts -system.physmem.perBankWrBursts::10 9747 # Per bank write bursts -system.physmem.perBankWrBursts::11 9397 # Per bank write bursts -system.physmem.perBankWrBursts::12 9475 # Per bank write bursts -system.physmem.perBankWrBursts::13 9702 # Per bank write bursts -system.physmem.perBankWrBursts::14 10013 # Per bank write bursts -system.physmem.perBankWrBursts::15 9419 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 1739 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11465 # Per bank write bursts +system.physmem.perBankRdBursts::1 11004 # Per bank write bursts +system.physmem.perBankRdBursts::2 11873 # Per bank write bursts +system.physmem.perBankRdBursts::3 11540 # Per bank write bursts +system.physmem.perBankRdBursts::4 11961 # Per bank write bursts +system.physmem.perBankRdBursts::5 11322 # Per bank write bursts +system.physmem.perBankRdBursts::6 11640 # Per bank write bursts +system.physmem.perBankRdBursts::7 11420 # Per bank write bursts +system.physmem.perBankRdBursts::8 11351 # Per bank write bursts +system.physmem.perBankRdBursts::9 11861 # Per bank write bursts +system.physmem.perBankRdBursts::10 11826 # Per bank write bursts +system.physmem.perBankRdBursts::11 12031 # Per bank write bursts +system.physmem.perBankRdBursts::12 11538 # Per bank write bursts +system.physmem.perBankRdBursts::13 12375 # Per bank write bursts +system.physmem.perBankRdBursts::14 11569 # Per bank write bursts +system.physmem.perBankRdBursts::15 11089 # Per bank write bursts +system.physmem.perBankWrBursts::0 10234 # Per bank write bursts +system.physmem.perBankWrBursts::1 9627 # Per bank write bursts +system.physmem.perBankWrBursts::2 9640 # Per bank write bursts +system.physmem.perBankWrBursts::3 9149 # Per bank write bursts +system.physmem.perBankWrBursts::4 9237 # Per bank write bursts +system.physmem.perBankWrBursts::5 9047 # Per bank write bursts +system.physmem.perBankWrBursts::6 8744 # Per bank write bursts +system.physmem.perBankWrBursts::7 8727 # Per bank write bursts +system.physmem.perBankWrBursts::8 9070 # Per bank write bursts +system.physmem.perBankWrBursts::9 9221 # Per bank write bursts +system.physmem.perBankWrBursts::10 9815 # Per bank write bursts +system.physmem.perBankWrBursts::11 9405 # Per bank write bursts +system.physmem.perBankWrBursts::12 9499 # Per bank write bursts +system.physmem.perBankWrBursts::13 9604 # Per bank write bursts +system.physmem.perBankWrBursts::14 9640 # Per bank write bursts +system.physmem.perBankWrBursts::15 9124 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 4 # Number of times write queue was full causing retry -system.physmem.totGap 5129873502000 # Total gap between requests +system.physmem.numWrRetry 2 # Number of times write queue was full causing retry +system.physmem.totGap 5129876930000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185938 # Read request sizes (log2) +system.physmem.readPktSize::6 186153 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 149859 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170868 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11901 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 408 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.writePktSize::6 149802 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 171145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2095 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see @@ -159,112 +159,115 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7847 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 8666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 9690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7829 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7668 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 7 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.717718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 177.081512 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 320.465816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27438 38.17% 38.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17395 24.20% 62.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7359 10.24% 72.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4225 5.88% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2947 4.10% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2054 2.86% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1404 1.95% 87.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1166 1.62% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7887 10.97% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71875 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7354 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.241501 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 560.072825 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7353 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 7679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 8641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 9732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 10392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11488 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 224 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 72700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.480165 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 175.038242 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 318.841917 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28215 38.81% 38.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17447 24.00% 62.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7490 10.30% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4112 5.66% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3047 4.19% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2009 2.76% 85.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1387 1.91% 87.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1145 1.57% 89.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7848 10.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 72700 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7372 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.211883 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 559.387781 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7371 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7354 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7354 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.374218 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.656947 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.477131 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6319 85.93% 85.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 51 0.69% 86.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 33 0.45% 87.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 263 3.58% 90.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 273 3.71% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 24 0.33% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 24 0.33% 95.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 15 0.20% 95.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 39 0.53% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.08% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 3 0.04% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.01% 95.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 229 3.11% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 2 0.03% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 25 0.34% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 13 0.18% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.07% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.14% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7354 # Writes before turning the bus around for reads -system.physmem.totQLat 1988147750 # Total ticks spent queuing -system.physmem.totMemAccLat 5468954000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 928215000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10709.52 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7372 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7372 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.317824 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.630780 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.249046 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6322 85.76% 85.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 58 0.79% 86.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 24 0.33% 86.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 276 3.74% 90.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 291 3.95% 94.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 18 0.24% 94.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.16% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.19% 95.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 37 0.50% 95.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 4 0.05% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 95.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.04% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 249 3.38% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 3 0.04% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.05% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 19 0.26% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.09% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 6 0.08% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.09% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7372 # Writes before turning the bus around for reads +system.physmem.totQLat 2030519500 # Total ticks spent queuing +system.physmem.totMemAccLat 5515488250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 929325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10924.70 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29459.52 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29674.70 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.32 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.32 # Average system read bandwidth in MiByte/s @@ -273,119 +276,128 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.59 # Average write queue length when enqueuing -system.physmem.readRowHits 152685 # Number of row buffer hits during reads -system.physmem.writeRowHits 110914 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes -system.physmem.avgGap 15276710.34 # Average gap between requests -system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4923726743250 # Time in different power states +system.physmem.avgRdQLen 1.49 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.68 # Average write queue length when enqueuing +system.physmem.readRowHits 152396 # Number of row buffer hits during reads +system.physmem.writeRowHits 110551 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.80 # Row buffer hit rate for writes +system.physmem.avgGap 15269535.89 # Average gap between requests +system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4923406969000 # Time in different power states system.physmem.memoryStateTime::REF 171297620000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 34849149750 # Time in different power states +system.physmem.memoryStateTime::ACT 35172289500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 4545861 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 662568 # Transaction distribution -system.membus.trans_dist::ReadResp 662557 # Transaction distribution +system.membus.trans_dist::ReadReq 662528 # Transaction distribution +system.membus.trans_dist::ReadResp 662520 # Transaction distribution system.membus.trans_dist::WriteReq 13776 # Transaction distribution system.membus.trans_dist::WriteResp 13776 # Transaction distribution -system.membus.trans_dist::Writeback 103139 # Transaction distribution +system.membus.trans_dist::Writeback 103082 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2217 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1710 # Transaction distribution -system.membus.trans_dist::ReadExReq 133156 # Transaction distribution -system.membus.trans_dist::ReadExResp 133153 # Transaction distribution -system.membus.trans_dist::MessageReq 1644 # Transaction distribution -system.membus.trans_dist::MessageResp 1644 # Transaction distribution -system.membus.trans_dist::BadAddressError 11 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2203 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1739 # Transaction distribution +system.membus.trans_dist::ReadExReq 133413 # Transaction distribution +system.membus.trans_dist::ReadExResp 133410 # Transaction distribution +system.membus.trans_dist::MessageReq 1645 # Transaction distribution +system.membus.trans_dist::MessageResp 1645 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3290 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3290 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471084 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478059 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724235 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94797 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 94797 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1822320 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18472576 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 20264541 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 23289549 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 23289549 # Total data (bytes) -system.membus.snoop_data_through_bus 30144 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 251288000 # Layer occupancy (ticks) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 478447 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724617 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94802 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94802 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1822709 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 241828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18482688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20274653 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23299665 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 943 # Total snoops (count) +system.membus.snoop_fanout::samples 338647 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 338647 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 338647 # Request fanout histogram +system.membus.reqLayer0.occupancy 251233500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583699000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 583254000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3290000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1574361000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1574333248 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 9500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1645000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3158618040 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 3160566012 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54966743 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 55015741 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47579 # number of replacements -system.iocache.tags.tagsinuse 0.103859 # Cycle average of tags in use +system.iocache.tags.replacements 47584 # number of replacements +system.iocache.tags.tagsinuse 0.103867 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47595 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992945696000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103859 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006491 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006491 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4992945897000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.103867 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006492 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.006492 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428706 # Number of tag accesses -system.iocache.tags.data_accesses 428706 # Number of data accesses +system.iocache.tags.tag_accesses 428751 # Number of tag accesses +system.iocache.tags.data_accesses 428751 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses -system.iocache.ReadReq_misses::total 914 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 914 # number of demand (read+write) misses -system.iocache.demand_misses::total 914 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 914 # number of overall misses -system.iocache.overall_misses::total 914 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152667446 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 152667446 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 152667446 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 152667446 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 152667446 # number of overall miss cycles -system.iocache.overall_miss_latency::total 152667446 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses +system.iocache.ReadReq_misses::total 919 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses +system.iocache.demand_misses::total 919 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses +system.iocache.overall_misses::total 919 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 156299196 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 156299196 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 156299196 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 156299196 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 156299196 # number of overall miss cycles +system.iocache.overall_miss_latency::total 156299196 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 914 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 914 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 914 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 914 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 167032.216630 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 167032.216630 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167032.216630 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 167032.216630 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 170075.294886 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 170075.294886 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170075.294886 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 170075.294886 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked @@ -394,22 +406,22 @@ system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 914 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 914 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 914 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 914 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 105114946 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2850047667 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2850047667 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 105114946 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 105114946 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 105114946 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 108481196 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2843906419 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2843906419 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 108481196 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 108481196 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 108481196 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -418,14 +430,14 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 115005.411379 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61002.732598 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61002.732598 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115005.411379 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 115005.411379 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 118042.650707 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60871.284653 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60871.284653 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118042.650707 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 118042.650707 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -439,13 +451,12 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 638663 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 225570 # Transaction distribution -system.iobus.trans_dist::ReadResp 225570 # Transaction distribution +system.iobus.trans_dist::ReadReq 225575 # Transaction distribution +system.iobus.trans_dist::ReadResp 225575 # Transaction distribution system.iobus.trans_dist::WriteReq 57606 # Transaction distribution system.iobus.trans_dist::WriteResp 57606 # Transaction distribution -system.iobus.trans_dist::MessageReq 1644 # Transaction distribution -system.iobus.trans_dist::MessageResp 1644 # Transaction distribution +system.iobus.trans_dist::MessageReq 1645 # Transaction distribution +system.iobus.trans_dist::MessageResp 1645 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) @@ -465,37 +476,36 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 471084 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 569640 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 3276260 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 3276260 # Total data (bytes) -system.iobus.reqLayer0.occupancy 3918185 # Layer occupancy (ticks) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3290 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 569652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 241828 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6580 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3276304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3920684 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -531,155 +541,155 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 422017356 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 422027356 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 460198000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52370257 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 52381259 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1645000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.branchPred.lookups 86877356 # Number of BP lookups -system.cpu.branchPred.condPredicted 86877356 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 902542 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80133511 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78163225 # Number of BTB hits +system.cpu.branchPred.lookups 86898883 # Number of BP lookups +system.cpu.branchPred.condPredicted 86898883 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 901790 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80120336 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78166165 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.541246 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1555611 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 178528 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.560955 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1553548 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 177807 # Number of incorrect RAS predictions. system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449309558 # number of cpu cycles simulated +system.cpu.numCycles 449490093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27651859 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 428959611 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86877356 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79718836 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 417653044 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1892712 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 141479 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 49827 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 205407 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 127451 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 417 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9182196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 444767 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5009 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 446775840 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894723 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.051895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27736713 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 428990683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86898883 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79719713 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 417726391 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1890728 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 147536 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 50079 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 202600 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 127031 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 405 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9184683 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 447260 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5357 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 446936119 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.894164 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.051823 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281257253 62.95% 62.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2318085 0.52% 63.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72134929 16.15% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1613434 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2149929 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2328393 0.52% 80.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1530698 0.34% 81.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1882713 0.42% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81560406 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 281459283 62.98% 62.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2262059 0.51% 63.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72137620 16.14% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1613997 0.36% 79.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2155091 0.48% 80.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2322801 0.52% 80.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1535694 0.34% 81.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1854025 0.41% 81.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81595549 18.26% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 446775840 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193357 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954708 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23023114 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264661195 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150717323 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7427852 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 946356 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838299668 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 946356 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25879231 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223164657 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13208529 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154609969 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 28967098 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 834812666 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 479412 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12346095 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 191662 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13684658 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997151203 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1813191058 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1114665342 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 185 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 963963482 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33187719 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 468373 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 472487 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39006494 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17336272 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10188880 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1345741 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1123547 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829275749 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1209290 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824021244 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 242579 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23492118 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36175819 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 154222 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 446775840 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.844373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418251 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 446936119 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.193328 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.954394 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23065529 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 264763767 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150736142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7425317 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 945364 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838360092 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 945364 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25914691 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 223241691 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13213057 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154633432 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 28987884 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834905613 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 478581 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12335118 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 182483 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 13727584 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997265714 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1813395255 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114768158 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 110 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964051126 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 33214586 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 466449 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 470370 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38986770 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17343174 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10196687 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1348761 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1124760 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829365293 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1208199 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824078412 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 244412 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23515910 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36291432 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152927 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 446936119 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.843839 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.418170 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262561849 58.77% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13882888 3.11% 61.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10086827 2.26% 64.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6921999 1.55% 65.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74315249 16.63% 82.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4452451 1.00% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72780033 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1201096 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 573448 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 262716607 58.78% 58.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13881580 3.11% 61.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 10086185 2.26% 64.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 6914821 1.55% 65.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74322504 16.63% 82.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4455510 1.00% 83.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72776226 16.28% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1206411 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 576275 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 446775840 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 446936119 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1974933 71.79% 71.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 151 0.01% 71.79% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 606 0.02% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.81% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 614459 22.33% 94.15% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161026 5.85% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1975200 71.80% 71.80% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 252 0.01% 71.81% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 1109 0.04% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.85% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 614218 22.33% 94.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160061 5.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 292875 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 795624977 96.55% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150449 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125321 0.02% 96.62% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 293084 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795671914 96.55% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150614 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125303 0.02% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 96.62% # Type of FU issued @@ -706,98 +716,98 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18429310 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9398312 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18435146 2.24% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9402351 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824021244 # Type of FU issued -system.cpu.iq.rate 1.833972 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2751175 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003339 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2097811864 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 853989635 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819447653 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 217 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 292 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 60 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 826479445 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 99 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1882501 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824078412 # Type of FU issued +system.cpu.iq.rate 1.833363 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2750840 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003338 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2098087999 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854102050 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819507550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 195 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 194 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 56 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826536078 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 90 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1879985 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3343168 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14800 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14469 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1764190 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3343174 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14903 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14336 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1767440 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224524 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72794 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2224972 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 73807 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 946356 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205489198 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9385897 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 830485039 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 188872 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17336272 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10188880 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 713065 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415930 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8070911 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14469 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 518528 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 536731 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1055259 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822394413 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18030482 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1492613 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 945364 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205481336 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9444308 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830573492 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 185181 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17343194 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10196687 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 711600 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 416792 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8129202 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14336 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 515306 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 539272 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1054578 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822459197 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18034619 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1483642 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27200783 # number of memory reference insts executed -system.cpu.iew.exec_branches 83281301 # Number of branches executed -system.cpu.iew.exec_stores 9170301 # Number of stores executed -system.cpu.iew.exec_rate 1.830351 # Inst execution rate -system.cpu.iew.wb_sent 821885746 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819447713 # cumulative count of insts written-back -system.cpu.iew.wb_producers 640810294 # num instructions producing a value -system.cpu.iew.wb_consumers 1050192124 # num instructions consuming a value +system.cpu.iew.exec_refs 27209233 # number of memory reference insts executed +system.cpu.iew.exec_branches 83289157 # Number of branches executed +system.cpu.iew.exec_stores 9174614 # Number of stores executed +system.cpu.iew.exec_rate 1.829760 # Inst execution rate +system.cpu.iew.wb_sent 821946704 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819507606 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640910074 # num instructions producing a value +system.cpu.iew.wb_consumers 1050315789 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823793 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610184 # average fanout of values written-back +system.cpu.iew.wb_rate 1.823194 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610207 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24342460 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1055068 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 914367 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443118746 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819035 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675250 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24363502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1055272 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 913280 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 443273616 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.818549 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.675153 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272366005 61.47% 61.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11194221 2.53% 63.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3590232 0.81% 64.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74521712 16.82% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2434404 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1603700 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 952599 0.21% 82.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71009883 16.03% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5445990 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 272516770 61.48% 61.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11195258 2.53% 64.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3583043 0.81% 64.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74523250 16.81% 81.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2432181 0.55% 82.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1605992 0.36% 82.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 951269 0.21% 82.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71009301 16.02% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5456552 1.23% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443118746 # Number of insts commited each cycle -system.cpu.commit.committedInsts 407773893 # Number of instructions committed -system.cpu.commit.committedOps 806048632 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 443273616 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407812863 # Number of instructions committed +system.cpu.commit.committedOps 806114915 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22417793 # Number of memory references committed -system.cpu.commit.loads 13993103 # Number of loads committed -system.cpu.commit.membars 474875 # Number of memory barriers committed -system.cpu.commit.branches 82158924 # Number of branches committed +system.cpu.commit.refs 22429266 # Number of memory references committed +system.cpu.commit.loads 14000019 # Number of loads committed +system.cpu.commit.membars 474889 # Number of memory barriers committed +system.cpu.commit.branches 82168190 # Number of branches committed system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu.commit.int_insts 734892496 # Number of committed integer instructions. -system.cpu.commit.function_calls 1155452 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 174150 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783190673 97.16% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 144749 0.02% 97.20% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121267 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 734958550 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155635 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 174258 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783245185 97.16% 97.18% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144842 0.02% 97.20% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121364 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 97.22% # Class of committed instruction @@ -824,214 +834,225 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13993103 1.74% 98.95% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8424690 1.05% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 14000019 1.74% 98.95% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8429247 1.05% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806048632 # Class of committed instruction -system.cpu.commit.bw_lim_events 5445990 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806114915 # Class of committed instruction +system.cpu.commit.bw_lim_events 5456552 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1267985613 # The number of ROB reads -system.cpu.rob.rob_writes 1664458820 # The number of ROB writes -system.cpu.timesIdled 297027 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2533718 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9810435335 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 407773893 # Number of Instructions Simulated -system.cpu.committedOps 806048632 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.101860 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.101860 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907557 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907557 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092201088 # number of integer regfile reads -system.cpu.int_regfile_writes 655889202 # number of integer regfile writes -system.cpu.fp_regfile_reads 60 # number of floating regfile reads -system.cpu.cc_regfile_reads 416095530 # number of cc regfile reads -system.cpu.cc_regfile_writes 321948927 # number of cc regfile writes -system.cpu.misc_regfile_reads 265553416 # number of misc regfile reads -system.cpu.misc_regfile_writes 402606 # number of misc regfile writes -system.cpu.toL2Bus.throughput 55008962 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 3071462 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3070914 # Transaction distribution +system.cpu.rob.rob_reads 1268217156 # The number of ROB reads +system.cpu.rob.rob_writes 1664635865 # The number of ROB writes +system.cpu.timesIdled 297982 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2553974 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9810264132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407812863 # Number of Instructions Simulated +system.cpu.committedOps 806114915 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.102197 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.102197 # CPI: Total CPI of All Threads +system.cpu.ipc 0.907279 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.907279 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092267062 # number of integer regfile reads +system.cpu.int_regfile_writes 655932610 # number of integer regfile writes +system.cpu.fp_regfile_reads 56 # number of floating regfile reads +system.cpu.cc_regfile_reads 416128291 # number of cc regfile reads +system.cpu.cc_regfile_writes 321990784 # number of cc regfile writes +system.cpu.misc_regfile_reads 265578345 # number of misc regfile reads +system.cpu.misc_regfile_writes 402863 # number of misc regfile writes +system.cpu.toL2Bus.trans_dist::ReadReq 3083726 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3083187 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13776 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13776 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585837 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2242 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2242 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287030 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 11 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1996026 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6130754 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30653 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 164256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8321689 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63869504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207903453 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 978368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5729920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 278481245 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 278457117 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 3731904 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 4072507880 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 1587489 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46722 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2231 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287826 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2007150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6137120 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 34489 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 168921 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8347680 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64225408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 208172445 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1082112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5828032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 279307997 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61506 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4398693 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010831 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4351052 98.92% 98.92% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47641 1.08% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4398693 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4081523356 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 565500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 582000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1501244795 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1509600495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3142652109 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3145861612 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 23061226 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 26384476 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 112150627 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 116845140 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu.icache.tags.replacements 997506 # number of replacements -system.cpu.icache.tags.tagsinuse 509.982226 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8120756 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 998018 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.136883 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147598371250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.982226 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996059 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996059 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1003070 # number of replacements +system.cpu.icache.tags.tagsinuse 510.154171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8117984 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1003582 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.089009 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 147599073250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.154171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996395 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996395 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 140 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10180257 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10180257 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8120756 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8120756 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8120756 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8120756 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8120756 # number of overall hits -system.cpu.icache.overall_hits::total 8120756 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061436 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061436 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061436 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061436 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061436 # number of overall misses -system.cpu.icache.overall_misses::total 1061436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14736249127 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14736249127 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14736249127 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14736249127 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14736249127 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14736249127 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9182192 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9182192 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9182192 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9182192 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9182192 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9182192 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115597 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115597 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115597 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115597 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115597 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115597 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13883.313857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13883.313857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13883.313857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13883.313857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13883.313857 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6673 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10188308 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10188308 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8117984 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8117984 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8117984 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8117984 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8117984 # number of overall hits +system.cpu.icache.overall_hits::total 8117984 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066696 # number of ReadReq misses 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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 22.852740 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 22.943609 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63371 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63371 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63371 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63371 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63371 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63371 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 998065 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 998065 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 998065 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 998065 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 998065 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 998065 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12095503951 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12095503951 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12095503951 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12095503951 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12095503951 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12095503951 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108696 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.108696 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108696 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.108696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12118.954127 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12118.954127 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12118.954127 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12118.954127 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63068 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63068 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63068 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63068 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63068 # number of overall MSHR hits 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12143729999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12143729999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12143729999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109272 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109272 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109272 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109272 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12099.831809 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12099.831809 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12099.831809 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12099.831809 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 14491 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.005977 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 26506 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 14506 # Sample count of references to valid blocks. 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per task id -system.cpu.itb_walker_cache.tags.tag_accesses 99110 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 99110 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26504 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 26504 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.replacements 16690 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.006176 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 23588 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 16704 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.412117 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5099387464000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.006176 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375386 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.375386 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 99931 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 99931 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 23592 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 23592 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26506 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 26506 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26506 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 26506 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15366 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 15366 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15366 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15366 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15366 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15366 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 173869741 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 173869741 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 173869741 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 173869741 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 173869741 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 173869741 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41870 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41870 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 23594 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 23594 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 23594 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 23594 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 17581 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 17581 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 17581 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 17581 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 17581 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 17581 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 194939990 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 194939990 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 194939990 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 194939990 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 194939990 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 194939990 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41173 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41173 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41872 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41872 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41872 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41872 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.366993 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.366993 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.366976 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.366976 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.366976 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.366976 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11315.224587 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11315.224587 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11315.224587 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11315.224587 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11315.224587 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41175 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41175 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41175 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41175 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.427003 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.427003 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.426982 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.426982 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.426982 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.426982 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11088.105910 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11088.105910 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11088.105910 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11088.105910 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11088.105910 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1040,85 +1061,85 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 2963 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 2963 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15366 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15366 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15366 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 15366 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15366 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 15366 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 143113289 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 143113289 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 143113289 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 143113289 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 143113289 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 143113289 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.366993 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.366993 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.366976 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.366976 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.366976 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9313.633281 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9313.633281 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9313.633281 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3261 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3261 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 17581 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 17581 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 17581 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 17581 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 17581 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 17581 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159752038 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159752038 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159752038 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159752038 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159752038 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159752038 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.427003 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.427003 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.426982 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.426982 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.426982 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9086.629771 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9086.629771 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9086.629771 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 73624 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.198399 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 115934 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 73640 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.574335 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 3233327929250 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.198399 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.949900 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.949900 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 76771 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.789364 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 114792 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 76787 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.494941 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 197445175000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.789364 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986835 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986835 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 456046 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 456046 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 115934 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 115934 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 115934 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 115934 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 115934 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 115934 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74726 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 74726 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74726 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 74726 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74726 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 74726 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 911611211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 911611211 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 911611211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 911611211 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 911611211 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 911611211 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190660 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190660 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190660 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190660 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190660 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190660 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391933 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391933 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391933 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391933 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391933 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391933 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12199.384565 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12199.384565 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12199.384565 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12199.384565 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12199.384565 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 463158 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 463158 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114792 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 114792 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114792 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 114792 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114792 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 114792 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 77858 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 77858 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 77858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 77858 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 77858 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 77858 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 943768714 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 943768714 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 943768714 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 943768714 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 943768714 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 943768714 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192650 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 192650 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192650 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 192650 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192650 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 192650 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404142 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404142 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404142 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404142 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404142 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404142 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12121.666547 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12121.666547 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12121.666547 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12121.666547 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12121.666547 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1127,169 +1148,169 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22207 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22207 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74726 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74726 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74726 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 74726 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74726 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 74726 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 762035957 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 762035957 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 762035957 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 762035957 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 762035957 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 762035957 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391933 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391933 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391933 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391933 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10197.735152 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10197.735152 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10197.735152 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 21599 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 21599 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 77858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 77858 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 77858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 77858 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 77858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 77858 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 787936434 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 787936434 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 787936434 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 787936434 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 787936434 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 787936434 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404142 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404142 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404142 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404142 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10120.173059 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10120.173059 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10120.173059 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 1659582 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996805 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19130892 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1660094 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.523981 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 1661725 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996415 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19139703 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1662237 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.514425 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996805 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996415 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999993 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88336593 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88336593 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 10981431 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10981431 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8081664 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8081664 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 65027 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 65027 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19063095 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19063095 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19128122 # number of overall hits -system.cpu.dcache.overall_hits::total 19128122 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1801191 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1801191 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 333463 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 333463 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406345 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406345 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2134654 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2134654 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2540999 # number of overall misses -system.cpu.dcache.overall_misses::total 2540999 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26558757753 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26558757753 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12819840878 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12819840878 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39378598631 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39378598631 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39378598631 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39378598631 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12782622 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12782622 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8415127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8415127 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 471372 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 471372 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21197749 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21197749 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21669121 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21669121 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140909 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140909 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039627 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862047 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862047 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100702 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100702 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117264 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117264 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14745.109071 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14745.109071 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38444.567697 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38444.567697 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18447.298078 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18447.298078 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15497.290094 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15497.290094 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378253 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88377305 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88377305 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10986051 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10986051 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8085611 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8085611 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 65242 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 65242 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19071662 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19071662 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19136904 # number of overall hits +system.cpu.dcache.overall_hits::total 19136904 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1801162 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1801162 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334073 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334073 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406623 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406623 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2135235 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2135235 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2541858 # number of overall misses +system.cpu.dcache.overall_misses::total 2541858 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26563616547 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26563616547 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12873735113 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12873735113 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39437351660 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39437351660 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39437351660 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39437351660 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12787213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12787213 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8419684 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8419684 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 471865 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 471865 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21206897 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21206897 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21678762 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21678762 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140856 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.140856 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039678 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039678 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.861736 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.861736 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.100686 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100686 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117251 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117251 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14748.044067 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14748.044067 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38535.694633 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38535.694633 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18469.794500 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18469.794500 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15515.167118 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15515.167118 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 377678 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 40145 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 40377 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.422170 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.353791 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560667 # number of writebacks -system.cpu.dcache.writebacks::total 1560667 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 830878 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 830878 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44317 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44317 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 875195 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 875195 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 875195 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 875195 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970313 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 970313 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289146 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402890 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402890 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1259459 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1259459 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1662349 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1662349 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12260897766 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12260897766 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11156657127 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11156657127 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5584385500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5584385500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23417554893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23417554893 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29001940393 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29001940393 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364665000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364665000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2539423000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2539423000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99904088000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99904088000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075909 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034360 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854718 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854718 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059415 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059415 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076715 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076715 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12636.023392 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12636.023392 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38584.857224 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38584.857224 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13860.819330 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13860.819330 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18593.344359 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18593.344359 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17446.360778 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17446.360778 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1562629 # number of writebacks +system.cpu.dcache.writebacks::total 1562629 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 829779 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 829779 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44137 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 873916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 873916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 873916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 873916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 971383 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 971383 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289936 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289936 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403164 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403164 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1261319 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1261319 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1664483 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1664483 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12264764518 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12264764518 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11214941849 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11214941849 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5603688502 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5603688502 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23479706367 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23479706367 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29083394869 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29083394869 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97364659500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97364659500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2538935000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2538935000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99903594500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 99903594500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075965 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034435 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034435 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854405 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854405 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059477 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059477 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076779 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076779 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12626.085198 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12626.085198 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38680.749714 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38680.749714 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13899.277966 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13899.277966 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18615.200728 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18615.200728 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17472.929954 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17472.929954 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1297,150 +1318,150 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112856 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64816.166677 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3836348 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176998 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.674527 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112646 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64814.554294 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3852282 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176740 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.796322 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50391.724726 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.855148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.135532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3265.471036 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11143.980235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768917 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000227 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50353.205869 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.791697 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.140401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3275.059967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11170.356359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000241 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049827 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170044 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989016 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 609 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3329 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5865 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54284 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978729 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35070365 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35070365 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67257 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12319 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 981564 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1336552 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2397692 # number of ReadReq hits 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cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4610750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1038765000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10062465280 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11106232530 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89251418000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89251418000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2373087500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2373087500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91624505500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91624505500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823995 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823995 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.464509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.464509 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067678 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000921 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000440 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016321 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067678 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63424.410795 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66919.297156 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65831.101285 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10025.380495 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10025.380495 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57315.934896 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57315.934896 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72042.968750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63424.410795 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.019988 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59710.606556 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt index 591176ec8..9d272e2fa 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_Two_Level/stats.txt @@ -1,79 +1,79 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.304497 # Number of seconds simulated -sim_ticks 5304496799500 # Number of ticks simulated -final_tick 5304496799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.300439 # Number of seconds simulated +sim_ticks 5300438650000 # Number of ticks simulated +final_tick 5300438650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 120327 # Simulator instruction rate (inst/s) -host_op_rate 230715 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5973118168 # Simulator tick rate (ticks/s) -host_mem_usage 829584 # Number of bytes of host memory used -host_seconds 888.06 # Real time elapsed on the host -sim_insts 106858198 # Number of instructions simulated -sim_ops 204889266 # Number of ops (including micro ops) simulated +host_inst_rate 184616 # Simulator instruction rate (inst/s) +host_op_rate 353991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9163289290 # Simulator tick rate (ticks/s) +host_mem_usage 842832 # Number of bytes of host memory used +host_seconds 578.44 # Real time elapsed on the host +sim_insts 106789618 # Number of instructions simulated +sim_ops 204763566 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::pc.south_bridge.ide 35160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 168624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 87432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 563238768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 42054251 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 54624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 20152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 449830560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 51714243 # Number of bytes read from this memory -system.physmem.bytes_read::total 1107203814 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 563238768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 449830560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1013069328 # Number of instructions bytes read from this memory +system.physmem.bytes_read::pc.south_bridge.ide 35184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 121960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 61480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 541981136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 38703389 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 101016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 45856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 470377672 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 54942760 # Number of bytes read from this memory +system.physmem.bytes_read::total 1106370453 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 541981136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 470377672 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1012358808 # Number of instructions bytes read from this memory system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 34106065 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 33949188 # Number of bytes written to this memory -system.physmem.bytes_written::total 71046373 # Number of bytes written to this memory -system.physmem.num_reads::pc.south_bridge.ide 811 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 21078 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 10929 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 70404846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 7007948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6828 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56228820 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 8722584 # Number of read requests responded to by this memory -system.physmem.num_reads::total 142406363 # Number of read requests responded to by this memory +system.physmem.bytes_written::cpu0.data 31533942 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 36447976 # Number of bytes written to this memory +system.physmem.bytes_written::total 70973038 # Number of bytes written to this memory +system.physmem.num_reads::pc.south_bridge.ide 814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 15245 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 7685 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 67747642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 6493671 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12627 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 5732 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 58797209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9219399 # Number of read requests responded to by this memory +system.physmem.num_reads::total 142300024 # Number of read requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 5095102 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 4745797 # Number of write requests responded to by this memory -system.physmem.num_writes::total 9887637 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 6628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 31789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 16483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 106181376 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 7928038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 10298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 84801740 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 9749133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 208729283 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 106181376 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 84801740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190983116 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 563881 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu0.data 4739534 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 5091384 # Number of write requests responded to by this memory +system.physmem.num_writes::total 9877656 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 6638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 23009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 11599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 102252129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 7301922 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 19058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 8651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 88743159 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 10365701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 208731867 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 102252129 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 88743159 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 190995288 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 564313 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6429651 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 6400077 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 13393612 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 570509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 31789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 16486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 106181376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 14357689 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 10298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 84801740 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 16149210 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 222122895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 5949308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 6876407 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 13390031 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 570950 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 23009 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 11602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 102252129 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 13251230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 19058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 8651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 88743159 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 17242108 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 222121898 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 0 # Number of DRAM read bursts, including those serviced by the write queue @@ -253,56 +253,56 @@ system.physmem.readRowHitRate nan # Ro system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests system.physmem.pageHitRate nan # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 5127363440000 # Time in different power states -system.physmem.memoryStateTime::REF 177128640000 # Time in different power states +system.physmem.memoryStateTime::IDLE 5123442263750 # Time in different power states +system.physmem.memoryStateTime::REF 176993180000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem.memoryStateTime::ACT 0 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.ruby.clk_domain.clock 500 # Clock period in ticks system.ruby.delayHist::bucket_size 4 # delay histogram for all message system.ruby.delayHist::max_bucket 39 # delay histogram for all message -system.ruby.delayHist::samples 10864368 # delay histogram for all message -system.ruby.delayHist::mean 0.442902 # delay histogram for all message -system.ruby.delayHist::stdev 1.830573 # delay histogram for all message -system.ruby.delayHist | 10263231 94.47% 94.47% | 1369 0.01% 94.48% | 599393 5.52% 100.00% | 125 0.00% 100.00% | 205 0.00% 100.00% | 8 0.00% 100.00% | 37 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message -system.ruby.delayHist::total 10864368 # delay histogram for all message +system.ruby.delayHist::samples 10855969 # delay histogram for all message +system.ruby.delayHist::mean 0.443071 # delay histogram for all message +system.ruby.delayHist::stdev 1.830936 # delay histogram for all message +system.ruby.delayHist | 10255101 94.47% 94.47% | 1445 0.01% 94.48% | 599037 5.52% 100.00% | 126 0.00% 100.00% | 212 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message +system.ruby.delayHist::total 10855969 # delay histogram for all message system.ruby.outstanding_req_hist::bucket_size 1 system.ruby.outstanding_req_hist::max_bucket 9 -system.ruby.outstanding_req_hist::samples 152246454 +system.ruby.outstanding_req_hist::samples 152130131 system.ruby.outstanding_req_hist::mean 1.000112 system.ruby.outstanding_req_hist::gmean 1.000078 -system.ruby.outstanding_req_hist::stdev 0.010602 -system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152229339 99.99% 99.99% | 17115 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.outstanding_req_hist::total 152246454 +system.ruby.outstanding_req_hist::stdev 0.010599 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 152113038 99.99% 99.99% | 17093 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 152130131 system.ruby.latency_hist::bucket_size 32 system.ruby.latency_hist::max_bucket 319 -system.ruby.latency_hist::samples 152246453 -system.ruby.latency_hist::mean 3.380088 -system.ruby.latency_hist::gmean 3.106160 -system.ruby.latency_hist::stdev 3.773917 -system.ruby.latency_hist | 152072522 99.89% 99.89% | 120 0.00% 99.89% | 79139 0.05% 99.94% | 93729 0.06% 100.00% | 941 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.latency_hist::total 152246453 +system.ruby.latency_hist::samples 152130130 +system.ruby.latency_hist::mean 3.380455 +system.ruby.latency_hist::gmean 3.106132 +system.ruby.latency_hist::stdev 3.781513 +system.ruby.latency_hist | 151955103 99.88% 99.88% | 126 0.00% 99.89% | 79786 0.05% 99.94% | 94134 0.06% 100.00% | 979 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 152130130 system.ruby.hit_latency_hist::bucket_size 1 system.ruby.hit_latency_hist::max_bucket 9 -system.ruby.hit_latency_hist::samples 149587693 +system.ruby.hit_latency_hist::samples 149475024 system.ruby.hit_latency_hist::mean 3 system.ruby.hit_latency_hist::gmean 3.000000 -system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149587693 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.hit_latency_hist::total 149587693 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 149475024 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 149475024 system.ruby.miss_latency_hist::bucket_size 32 system.ruby.miss_latency_hist::max_bucket 319 -system.ruby.miss_latency_hist::samples 2658760 -system.ruby.miss_latency_hist::mean 24.764674 -system.ruby.miss_latency_hist::gmean 21.974787 -system.ruby.miss_latency_hist::stdev 18.711640 -system.ruby.miss_latency_hist | 2484829 93.46% 93.46% | 120 0.00% 93.46% | 79139 2.98% 96.44% | 93729 3.53% 99.96% | 941 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.miss_latency_hist::total 2658760 -system.ruby.l1_cntrl0.L1Dcache.demand_hits 11563536 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Dcache.demand_misses 571523 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Dcache.demand_accesses 12135059 # Number of cache demand accesses -system.ruby.l1_cntrl0.L1Icache.demand_hits 70045998 # Number of cache demand hits -system.ruby.l1_cntrl0.L1Icache.demand_misses 358848 # Number of cache demand misses -system.ruby.l1_cntrl0.L1Icache.demand_accesses 70404846 # Number of cache demand accesses +system.ruby.miss_latency_hist::samples 2655106 +system.ruby.miss_latency_hist::mean 24.799008 +system.ruby.miss_latency_hist::gmean 21.990340 +system.ruby.miss_latency_hist::stdev 18.773320 +system.ruby.miss_latency_hist | 2480079 93.41% 93.41% | 126 0.00% 93.41% | 79786 3.01% 96.42% | 94134 3.55% 99.96% | 979 0.04% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 2655106 +system.ruby.l1_cntrl0.L1Dcache.demand_hits 10730190 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Dcache.demand_misses 525947 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Dcache.demand_accesses 11256137 # Number of cache demand accesses +system.ruby.l1_cntrl0.L1Icache.demand_hits 67423344 # Number of cache demand hits +system.ruby.l1_cntrl0.L1Icache.demand_misses 324298 # Number of cache demand misses +system.ruby.l1_cntrl0.L1Icache.demand_accesses 67747642 # Number of cache demand accesses system.cpu_clk_domain.clock 500 # Clock period in ticks system.ruby.l1_cntrl0.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl0.prefetcher.allocated_streams 0 # number of streams allocated for prefetching @@ -313,30 +313,30 @@ system.ruby.l1_cntrl0.prefetcher.hits 0 # nu system.ruby.l1_cntrl0.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl0.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl0.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl0.fully_busy_cycles 13 # cycles for which number of transistions == max transitions -system.ruby.network.routers0.percent_links_utilized 0.032337 -system.ruby.network.routers0.msg_count.Control::0 930371 -system.ruby.network.routers0.msg_count.Request_Control::2 42522 -system.ruby.network.routers0.msg_count.Response_Data::1 958517 -system.ruby.network.routers0.msg_count.Response_Control::1 545617 -system.ruby.network.routers0.msg_count.Response_Control::2 541977 -system.ruby.network.routers0.msg_count.Writeback_Data::0 316333 -system.ruby.network.routers0.msg_count.Writeback_Data::1 73 -system.ruby.network.routers0.msg_count.Writeback_Control::0 187850 -system.ruby.network.routers0.msg_bytes.Control::0 7442968 -system.ruby.network.routers0.msg_bytes.Request_Control::2 340176 -system.ruby.network.routers0.msg_bytes.Response_Data::1 69013224 -system.ruby.network.routers0.msg_bytes.Response_Control::1 4364936 -system.ruby.network.routers0.msg_bytes.Response_Control::2 4335816 -system.ruby.network.routers0.msg_bytes.Writeback_Data::0 22775976 -system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5256 -system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1502800 -system.ruby.l1_cntrl1.L1Dcache.demand_hits 12207979 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Dcache.demand_misses 1269749 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Dcache.demand_accesses 13477728 # Number of cache demand accesses -system.ruby.l1_cntrl1.L1Icache.demand_hits 55770180 # Number of cache demand hits -system.ruby.l1_cntrl1.L1Icache.demand_misses 458640 # Number of cache demand misses -system.ruby.l1_cntrl1.L1Icache.demand_accesses 56228820 # Number of cache demand accesses +system.ruby.l1_cntrl0.fully_busy_cycles 12 # cycles for which number of transistions == max transitions +system.ruby.network.routers0.percent_links_utilized 0.029767 +system.ruby.network.routers0.msg_count.Control::0 850245 +system.ruby.network.routers0.msg_count.Request_Control::2 42194 +system.ruby.network.routers0.msg_count.Response_Data::1 878350 +system.ruby.network.routers0.msg_count.Response_Control::1 503571 +system.ruby.network.routers0.msg_count.Response_Control::2 500402 +system.ruby.network.routers0.msg_count.Writeback_Data::0 294663 +system.ruby.network.routers0.msg_count.Writeback_Data::1 77 +system.ruby.network.routers0.msg_count.Writeback_Control::0 168221 +system.ruby.network.routers0.msg_bytes.Control::0 6801960 +system.ruby.network.routers0.msg_bytes.Request_Control::2 337552 +system.ruby.network.routers0.msg_bytes.Response_Data::1 63241200 +system.ruby.network.routers0.msg_bytes.Response_Control::1 4028568 +system.ruby.network.routers0.msg_bytes.Response_Control::2 4003216 +system.ruby.network.routers0.msg_bytes.Writeback_Data::0 21215736 +system.ruby.network.routers0.msg_bytes.Writeback_Data::1 5544 +system.ruby.network.routers0.msg_bytes.Writeback_Control::0 1345768 +system.ruby.l1_cntrl1.L1Dcache.demand_hits 13015788 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Dcache.demand_misses 1313354 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Dcache.demand_accesses 14329142 # Number of cache demand accesses +system.ruby.l1_cntrl1.L1Icache.demand_hits 58305702 # Number of cache demand hits +system.ruby.l1_cntrl1.L1Icache.demand_misses 491507 # Number of cache demand misses +system.ruby.l1_cntrl1.L1Icache.demand_accesses 58797209 # Number of cache demand accesses system.ruby.l1_cntrl1.prefetcher.miss_observed 0 # number of misses observed system.ruby.l1_cntrl1.prefetcher.allocated_streams 0 # number of streams allocated for prefetching system.ruby.l1_cntrl1.prefetcher.prefetches_requested 0 # number of prefetch requests made @@ -346,111 +346,111 @@ system.ruby.l1_cntrl1.prefetcher.hits 0 # nu system.ruby.l1_cntrl1.prefetcher.partial_hits 0 # number of misses observed for a block being prefetched system.ruby.l1_cntrl1.prefetcher.pages_crossed 0 # number of prefetches across pages system.ruby.l1_cntrl1.prefetcher.misses_on_prefetched_blocks 0 # number of misses for blocks that were prefetched, yet missed -system.ruby.l1_cntrl1.fully_busy_cycles 12 # cycles for which number of transistions == max transitions -system.ruby.network.routers1.percent_links_utilized 0.054687 -system.ruby.network.routers1.msg_count.Control::0 1728389 -system.ruby.network.routers1.msg_count.Request_Control::2 38822 -system.ruby.network.routers1.msg_count.Response_Data::1 1752004 -system.ruby.network.routers1.msg_count.Response_Control::1 1215403 -system.ruby.network.routers1.msg_count.Response_Control::2 1215696 -system.ruby.network.routers1.msg_count.Writeback_Data::0 257519 -system.ruby.network.routers1.msg_count.Writeback_Data::1 203 -system.ruby.network.routers1.msg_count.Writeback_Control::0 921082 -system.ruby.network.routers1.msg_bytes.Control::0 13827112 -system.ruby.network.routers1.msg_bytes.Request_Control::2 310576 -system.ruby.network.routers1.msg_bytes.Response_Data::1 126144288 -system.ruby.network.routers1.msg_bytes.Response_Control::1 9723224 -system.ruby.network.routers1.msg_bytes.Response_Control::2 9725568 -system.ruby.network.routers1.msg_bytes.Writeback_Data::0 18541368 -system.ruby.network.routers1.msg_bytes.Writeback_Data::1 14616 -system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7368656 -system.ruby.l2_cntrl0.L2cache.demand_hits 2436175 # Number of cache demand hits -system.ruby.l2_cntrl0.L2cache.demand_misses 222585 # Number of cache demand misses -system.ruby.l2_cntrl0.L2cache.demand_accesses 2658760 # Number of cache demand accesses +system.ruby.l1_cntrl1.fully_busy_cycles 13 # cycles for which number of transistions == max transitions +system.ruby.network.routers1.percent_links_utilized 0.057220 +system.ruby.network.routers1.msg_count.Control::0 1804861 +system.ruby.network.routers1.msg_count.Request_Control::2 38457 +system.ruby.network.routers1.msg_count.Response_Data::1 1828237 +system.ruby.network.routers1.msg_count.Response_Control::1 1255902 +system.ruby.network.routers1.msg_count.Response_Control::2 1256112 +system.ruby.network.routers1.msg_count.Writeback_Data::0 279082 +system.ruby.network.routers1.msg_count.Writeback_Data::1 227 +system.ruby.network.routers1.msg_count.Writeback_Control::0 940216 +system.ruby.network.routers1.msg_bytes.Control::0 14438888 +system.ruby.network.routers1.msg_bytes.Request_Control::2 307656 +system.ruby.network.routers1.msg_bytes.Response_Data::1 131633064 +system.ruby.network.routers1.msg_bytes.Response_Control::1 10047216 +system.ruby.network.routers1.msg_bytes.Response_Control::2 10048896 +system.ruby.network.routers1.msg_bytes.Writeback_Data::0 20093904 +system.ruby.network.routers1.msg_bytes.Writeback_Data::1 16344 +system.ruby.network.routers1.msg_bytes.Writeback_Control::0 7521728 +system.ruby.l2_cntrl0.L2cache.demand_hits 2431773 # Number of cache demand hits +system.ruby.l2_cntrl0.L2cache.demand_misses 223333 # Number of cache demand misses +system.ruby.l2_cntrl0.L2cache.demand_accesses 2655106 # Number of cache demand accesses system.ruby.l2_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions -system.ruby.network.routers2.percent_links_utilized 0.091278 -system.ruby.network.routers2.msg_count.Control::0 2832571 -system.ruby.network.routers2.msg_count.Request_Control::2 79701 -system.ruby.network.routers2.msg_count.Response_Data::1 2883607 -system.ruby.network.routers2.msg_count.Response_Control::1 1836255 -system.ruby.network.routers2.msg_count.Response_Control::2 1757673 -system.ruby.network.routers2.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers2.msg_count.Writeback_Data::1 276 -system.ruby.network.routers2.msg_count.Writeback_Control::0 1108932 -system.ruby.network.routers2.msg_bytes.Control::0 22660568 -system.ruby.network.routers2.msg_bytes.Request_Control::2 637608 -system.ruby.network.routers2.msg_bytes.Response_Data::1 207619704 -system.ruby.network.routers2.msg_bytes.Response_Control::1 14690040 -system.ruby.network.routers2.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers2.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8871456 +system.ruby.network.routers2.percent_links_utilized 0.091305 +system.ruby.network.routers2.msg_count.Control::0 2830007 +system.ruby.network.routers2.msg_count.Request_Control::2 78985 +system.ruby.network.routers2.msg_count.Response_Data::1 2882064 +system.ruby.network.routers2.msg_count.Response_Control::1 1837383 +system.ruby.network.routers2.msg_count.Response_Control::2 1756514 +system.ruby.network.routers2.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers2.msg_count.Writeback_Data::1 304 +system.ruby.network.routers2.msg_count.Writeback_Control::0 1108437 +system.ruby.network.routers2.msg_bytes.Control::0 22640056 +system.ruby.network.routers2.msg_bytes.Request_Control::2 631880 +system.ruby.network.routers2.msg_bytes.Response_Data::1 207508608 +system.ruby.network.routers2.msg_bytes.Response_Control::1 14699064 +system.ruby.network.routers2.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers2.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers2.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers2.msg_bytes.Writeback_Control::0 8867496 system.ruby.memctrl_clk_domain.clock 1500 # Clock period in ticks -system.ruby.dir_cntrl0.memBuffer.memReq 316333 # Total number of memory requests -system.ruby.dir_cntrl0.memBuffer.memRead 174271 # Number of memory reads -system.ruby.dir_cntrl0.memBuffer.memWrite 142062 # Number of memory writes -system.ruby.dir_cntrl0.memBuffer.memRefresh 709010 # Number of memory refreshes -system.ruby.dir_cntrl0.memBuffer.memWaitCycles 938353 # Delay stalled at the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.memInputQ 49 # Delay in the input queue -system.ruby.dir_cntrl0.memBuffer.memBankQ 6542 # Delay behind the head of the bank queue -system.ruby.dir_cntrl0.memBuffer.totalStalls 944944 # Total number of stall cycles -system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.987181 # Expected number of stall cycles per request -system.ruby.dir_cntrl0.memBuffer.memBankBusy 926785 # memory stalls due to busy bank -system.ruby.dir_cntrl0.memBuffer.memBusBusy 8256 # memory stalls due to busy bus -system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 98 # memory stalls due to read write turnaround -system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 9 # memory stalls due to read read turnaround -system.ruby.dir_cntrl0.memBuffer.memArbWait 3205 # memory stalls due to arbitration -system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.25% 3.25% | 9688 3.06% 6.31% | 9618 3.04% 9.35% | 9663 3.05% 12.41% | 10044 3.18% 15.58% | 9949 3.15% 18.73% | 9819 3.10% 21.83% | 9702 3.07% 24.90% | 9851 3.11% 28.01% | 9707 3.07% 31.08% | 9714 3.07% 34.15% | 9748 3.08% 37.23% | 9782 3.09% 40.33% | 9588 3.03% 43.36% | 9583 3.03% 46.39% | 8652 2.74% 49.12% | 10210 3.23% 52.35% | 9818 3.10% 55.45% | 9760 3.09% 58.54% | 9707 3.07% 61.61% | 10012 3.17% 64.77% | 9864 3.12% 67.89% | 9722 3.07% 70.96% | 9786 3.09% 74.06% | 10077 3.19% 77.24% | 9920 3.14% 80.38% | 10090 3.19% 83.57% | 10790 3.41% 86.98% | 10587 3.35% 90.33% | 10505 3.32% 93.65% | 10419 3.29% 96.94% | 9676 3.06% 100.00% # Number of accesses per bank -system.ruby.dir_cntrl0.memBuffer.memBankCount::total 316333 # Number of accesses per bank -system.ruby.network.routers3.percent_links_utilized 0.006678 -system.ruby.network.routers3.msg_count.Control::0 173811 -system.ruby.network.routers3.msg_count.Response_Data::1 271445 -system.ruby.network.routers3.msg_count.Response_Control::1 122871 -system.ruby.network.routers3.msg_count.Writeback_Control::0 47547 +system.ruby.dir_cntrl0.memBuffer.memReq 317875 # Total number of memory requests +system.ruby.dir_cntrl0.memBuffer.memRead 175364 # Number of memory reads +system.ruby.dir_cntrl0.memBuffer.memWrite 142511 # Number of memory writes +system.ruby.dir_cntrl0.memBuffer.memRefresh 714751 # Number of memory refreshes +system.ruby.dir_cntrl0.memBuffer.memWaitCycles 942834 # Delay stalled at the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.memInputQ 46 # Delay in the input queue +system.ruby.dir_cntrl0.memBuffer.memBankQ 6611 # Delay behind the head of the bank queue +system.ruby.dir_cntrl0.memBuffer.totalStalls 949491 # Total number of stall cycles +system.ruby.dir_cntrl0.memBuffer.stallsPerReq 2.986995 # Expected number of stall cycles per request +system.ruby.dir_cntrl0.memBuffer.memBankBusy 931351 # memory stalls due to busy bank +system.ruby.dir_cntrl0.memBuffer.memBusBusy 8237 # memory stalls due to busy bus +system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy 87 # memory stalls due to read write turnaround +system.ruby.dir_cntrl0.memBuffer.memDataBusBusy 8 # memory stalls due to read read turnaround +system.ruby.dir_cntrl0.memBuffer.memArbWait 3151 # memory stalls due to arbitration +system.ruby.dir_cntrl0.memBuffer.memBankCount | 10282 3.23% 3.23% | 9701 3.05% 6.29% | 9679 3.04% 9.33% | 9712 3.06% 12.39% | 10010 3.15% 15.54% | 9927 3.12% 18.66% | 9854 3.10% 21.76% | 9702 3.05% 24.81% | 9904 3.12% 27.93% | 9752 3.07% 30.99% | 9805 3.08% 34.08% | 9914 3.12% 37.20% | 9948 3.13% 40.33% | 9724 3.06% 43.39% | 9647 3.03% 46.42% | 8750 2.75% 49.17% | 10266 3.23% 52.40% | 9887 3.11% 55.51% | 9844 3.10% 58.61% | 9758 3.07% 61.68% | 10022 3.15% 64.83% | 9879 3.11% 67.94% | 9766 3.07% 71.01% | 9852 3.10% 74.11% | 10073 3.17% 77.28% | 9931 3.12% 80.41% | 10175 3.20% 83.61% | 10769 3.39% 86.99% | 10605 3.34% 90.33% | 10522 3.31% 93.64% | 10506 3.31% 96.95% | 9709 3.05% 100.00% # Number of accesses per bank +system.ruby.dir_cntrl0.memBuffer.memBankCount::total 317875 # Number of accesses per bank +system.ruby.network.routers3.percent_links_utilized 0.006727 +system.ruby.network.routers3.msg_count.Control::0 174901 +system.ruby.network.routers3.msg_count.Response_Data::1 273155 +system.ruby.network.routers3.msg_count.Response_Control::1 125034 +system.ruby.network.routers3.msg_count.Writeback_Control::0 47550 system.ruby.network.routers3.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers3.msg_bytes.Control::0 1390488 -system.ruby.network.routers3.msg_bytes.Response_Data::1 19544040 -system.ruby.network.routers3.msg_bytes.Response_Control::1 982968 -system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380376 +system.ruby.network.routers3.msg_bytes.Control::0 1399208 +system.ruby.network.routers3.msg_bytes.Response_Data::1 19667160 +system.ruby.network.routers3.msg_bytes.Response_Control::1 1000272 +system.ruby.network.routers3.msg_bytes.Writeback_Control::0 380400 system.ruby.network.routers3.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.routers4.percent_links_utilized 0.000239 -system.ruby.network.routers4.msg_count.Response_Data::1 811 -system.ruby.network.routers4.msg_count.Writeback_Control::0 47547 +system.ruby.network.routers4.percent_links_utilized 0.000240 +system.ruby.network.routers4.msg_count.Response_Data::1 814 +system.ruby.network.routers4.msg_count.Writeback_Control::0 47550 system.ruby.network.routers4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.msg_bytes.Response_Data::1 58392 -system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380376 +system.ruby.network.routers4.msg_bytes.Response_Data::1 58608 +system.ruby.network.routers4.msg_bytes.Writeback_Control::0 380400 system.ruby.network.routers4.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.routers5.percent_links_utilized 0.037045 -system.ruby.network.routers5.msg_count.Control::0 2832571 -system.ruby.network.routers5.msg_count.Request_Control::2 81344 -system.ruby.network.routers5.msg_count.Response_Data::1 2933192 -system.ruby.network.routers5.msg_count.Response_Control::1 1860073 -system.ruby.network.routers5.msg_count.Response_Control::2 1757673 -system.ruby.network.routers5.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers5.msg_count.Writeback_Data::1 276 -system.ruby.network.routers5.msg_count.Writeback_Control::0 1156479 +system.ruby.network.routers5.percent_links_utilized 0.037053 +system.ruby.network.routers5.msg_count.Control::0 2830007 +system.ruby.network.routers5.msg_count.Request_Control::2 80651 +system.ruby.network.routers5.msg_count.Response_Data::1 2931310 +system.ruby.network.routers5.msg_count.Response_Control::1 1860945 +system.ruby.network.routers5.msg_count.Response_Control::2 1756514 +system.ruby.network.routers5.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers5.msg_count.Writeback_Data::1 304 +system.ruby.network.routers5.msg_count.Writeback_Control::0 1155987 system.ruby.network.routers5.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers5.msg_bytes.Control::0 22660568 -system.ruby.network.routers5.msg_bytes.Request_Control::2 650752 -system.ruby.network.routers5.msg_bytes.Response_Data::1 211189824 -system.ruby.network.routers5.msg_bytes.Response_Control::1 14880584 -system.ruby.network.routers5.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers5.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9251832 +system.ruby.network.routers5.msg_bytes.Control::0 22640056 +system.ruby.network.routers5.msg_bytes.Request_Control::2 645208 +system.ruby.network.routers5.msg_bytes.Response_Data::1 211054320 +system.ruby.network.routers5.msg_bytes.Response_Control::1 14887560 +system.ruby.network.routers5.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers5.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers5.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers5.msg_bytes.Writeback_Control::0 9247896 system.ruby.network.routers5.msg_bytes.Writeback_Control::1 373888 -system.ruby.network.msg_count.Control 8497713 -system.ruby.network.msg_count.Request_Control 242389 -system.ruby.network.msg_count.Response_Data 8799576 -system.ruby.network.msg_count.Response_Control 10853238 -system.ruby.network.msg_count.Writeback_Data 1722384 -system.ruby.network.msg_count.Writeback_Control 3609645 -system.ruby.network.msg_byte.Control 67981704 -system.ruby.network.msg_byte.Request_Control 1939112 -system.ruby.network.msg_byte.Response_Data 633569472 -system.ruby.network.msg_byte.Response_Control 86825904 -system.ruby.network.msg_byte.Writeback_Data 124011648 -system.ruby.network.msg_byte.Writeback_Control 28877160 +system.ruby.network.msg_count.Control 8490021 +system.ruby.network.msg_count.Request_Control 240287 +system.ruby.network.msg_count.Response_Data 8793930 +system.ruby.network.msg_count.Response_Control 10852377 +system.ruby.network.msg_count.Writeback_Data 1722147 +system.ruby.network.msg_count.Writeback_Control 3608169 +system.ruby.network.msg_byte.Control 67920168 +system.ruby.network.msg_byte.Request_Control 1922296 +system.ruby.network.msg_byte.Response_Data 633162960 +system.ruby.network.msg_byte.Response_Control 86819016 +system.ruby.network.msg_byte.Writeback_Data 123994584 +system.ruby.network.msg_byte.Writeback_Control 28865352 system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD). @@ -463,737 +463,738 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.throughput 383266 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 858445 # Transaction distribution -system.iobus.trans_dist::ReadResp 858445 # Transaction distribution -system.iobus.trans_dist::WriteReq 37732 # Transaction distribution -system.iobus.trans_dist::WriteResp 37732 # Transaction distribution -system.iobus.trans_dist::MessageReq 1926 # Transaction distribution -system.iobus.trans_dist::MessageResp 1926 # Transaction distribution -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1702 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1646 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3348 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 858433 # Transaction distribution +system.iobus.trans_dist::ReadResp 858433 # Transaction distribution +system.iobus.trans_dist::WriteReq 37701 # Transaction distribution +system.iobus.trans_dist::WriteResp 37701 # Transaction distribution +system.iobus.trans_dist::MessageReq 1920 # Transaction distribution +system.iobus.trans_dist::MessageResp 1920 # Transaction distribution +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1700 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 1644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3344 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 6438 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5246 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 88 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 38 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 934582 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 980 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 984 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 90 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14492 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 14276 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 743206 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 246 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 2126 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1703394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1701984 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 4650 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 5796 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 92 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 408 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 33042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 350 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 33130 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 12392 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 260 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5252 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 89464 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 1796206 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3404 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3292 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6696 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1960 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7246 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486422 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 488 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1972089 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 708 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6088 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 520 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10501 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54249 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 2033034 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 2033034 # Total data (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 250 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 5220 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 90780 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 1796108 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl0.sequencer.pio-slave-port 3400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.ruby.l1_cntrl1.sequencer.pio-slave-port 3288 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6688 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 18 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 2968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 478 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 19 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.speaker.pio 467291 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 1968 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.i_dont_exist.pio 45 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.com_1.pio 7138 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 1486406 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 492 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::system.pc.pciconfig.pio 4252 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl0.sequencer.mem-master-port::total 1971279 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.cmos.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide.pio 3692 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.ide-pciconf 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.keyboard.pio 204 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic1.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.pit.pio 16521 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.south_bridge.io_apic.pio 700 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.i_dont_exist.pio 16565 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.com_1.pio 6196 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl0.sequencer.pio-slave-port 500 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::system.ruby.l1_cntrl1.sequencer.pio-slave-port 10437 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.ruby.l1_cntrl1.sequencer.mem-master-port::total 54937 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2032904 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 44000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 6500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 10235000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 10297000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 144000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 1064500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 1047500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 92000 # Layer occupancy (ticks) +system.iobus.reqLayer5.occupancy 96000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 57500 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 56500 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 30321000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 467293000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 1237000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 1246000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 41501500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 41493500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 23566000 # Layer occupancy (ticks) +system.iobus.reqLayer12.occupancy 23740500 # Layer occupancy (ticks) system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 469636032 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 469005748 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 7824868 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8238216 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1328500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2417900 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2422964 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1790325500 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1790015500 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 80269500 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 80920500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 10608993599 # number of cpu cycles simulated +system.cpu0.numCycles 10600877300 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 60256011 # Number of instructions committed -system.cpu0.committedOps 115558641 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108487069 # Number of integer alu accesses +system.cpu0.committedInsts 58227397 # Number of instructions committed +system.cpu0.committedOps 111982705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 104955708 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 1055482 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 10261722 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108487069 # number of integer instructions +system.cpu0.num_func_calls 986034 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9961508 # number of instructions that are conditional controls +system.cpu0.num_int_insts 104955708 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 204952011 # number of times the integer registers were read -system.cpu0.num_int_register_writes 91998767 # number of times the integer registers were written +system.cpu0.num_int_register_reads 197725542 # number of times the integer registers were read +system.cpu0.num_int_register_writes 89196196 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 62453256 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44908337 # number of times the CC registers were written -system.cpu0.num_mem_refs 12953157 # number of memory refs -system.cpu0.num_load_insts 7847096 # Number of load instructions -system.cpu0.num_store_insts 5106061 # Number of store instructions -system.cpu0.num_idle_cycles 10082177996.950100 # Number of idle cycles -system.cpu0.num_busy_cycles 526815602.049901 # Number of busy cycles -system.cpu0.not_idle_fraction 0.049657 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.950343 # Percentage of idle cycles -system.cpu0.Branches 11678089 # Number of branches fetched -system.cpu0.op_class::No_OpClass 146086 0.13% 0.13% # Class of executed instruction -system.cpu0.op_class::IntAlu 102311234 88.54% 88.66% # Class of executed instruction -system.cpu0.op_class::IntMult 88422 0.08% 88.74% # Class of executed instruction -system.cpu0.op_class::IntDiv 60826 0.05% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 88.79% # Class of executed instruction -system.cpu0.op_class::MemRead 7847096 6.79% 95.58% # Class of executed instruction -system.cpu0.op_class::MemWrite 5106061 4.42% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 60309477 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 43597657 # number of times the CC registers were written +system.cpu0.num_mem_refs 12082037 # number of memory refs +system.cpu0.num_load_insts 7332388 # Number of load instructions +system.cpu0.num_store_insts 4749649 # Number of store instructions +system.cpu0.num_idle_cycles 10090456434.750097 # Number of idle cycles +system.cpu0.num_busy_cycles 510420865.249904 # Number of busy cycles +system.cpu0.not_idle_fraction 0.048149 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.951851 # Percentage of idle cycles +system.cpu0.Branches 11280989 # Number of branches fetched +system.cpu0.op_class::No_OpClass 134403 0.12% 0.12% # Class of executed instruction +system.cpu0.op_class::IntAlu 99628506 88.97% 89.09% # Class of executed instruction +system.cpu0.op_class::IntMult 83751 0.07% 89.16% # Class of executed instruction +system.cpu0.op_class::IntDiv 54749 0.05% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 89.21% # Class of executed instruction +system.cpu0.op_class::MemRead 7332388 6.55% 95.76% # Class of executed instruction +system.cpu0.op_class::MemWrite 4749649 4.24% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 115559725 # Class of executed instruction +system.cpu0.op_class::total 111983446 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu1.numCycles 10606073781 # number of cpu cycles simulated +system.cpu1.numCycles 10598045368 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 46602187 # Number of instructions committed -system.cpu1.committedOps 89330625 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 85693039 # Number of integer alu accesses +system.cpu1.committedInsts 48562221 # Number of instructions committed +system.cpu1.committedOps 92780861 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 89101588 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 1689151 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7994407 # number of instructions that are conditional controls -system.cpu1.num_int_insts 85693039 # number of integer instructions +system.cpu1.num_func_calls 1756989 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 8282079 # number of instructions that are conditional controls +system.cpu1.num_int_insts 89101588 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 165895875 # number of times the integer registers were read -system.cpu1.num_int_register_writes 70974584 # number of times the integer registers were written +system.cpu1.num_int_register_reads 172887570 # number of times the integer registers were read +system.cpu1.num_int_register_writes 73678147 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 49186847 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 31804657 # number of times the CC registers were written -system.cpu1.num_mem_refs 13506592 # number of memory refs -system.cpu1.num_load_insts 8734544 # Number of load instructions -system.cpu1.num_store_insts 4772048 # Number of store instructions -system.cpu1.num_idle_cycles 10285708583.748486 # Number of idle cycles -system.cpu1.num_busy_cycles 320365197.251515 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030206 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969794 # Percentage of idle cycles -system.cpu1.Branches 10261414 # Number of branches fetched -system.cpu1.op_class::No_OpClass 160911 0.18% 0.18% # Class of executed instruction -system.cpu1.op_class::IntAlu 75499496 84.52% 84.70% # Class of executed instruction -system.cpu1.op_class::IntMult 96292 0.11% 84.80% # Class of executed instruction -system.cpu1.op_class::IntDiv 67765 0.08% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.88% # Class of executed instruction -system.cpu1.op_class::MemRead 8734544 9.78% 94.66% # Class of executed instruction -system.cpu1.op_class::MemWrite 4772048 5.34% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 51235949 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 33065863 # number of times the CC registers were written +system.cpu1.num_mem_refs 14350246 # number of memory refs +system.cpu1.num_load_insts 9231791 # Number of load instructions +system.cpu1.num_store_insts 5118455 # Number of store instructions +system.cpu1.num_idle_cycles 10261750383.824707 # Number of idle cycles +system.cpu1.num_busy_cycles 336294984.175294 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031732 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968268 # Percentage of idle cycles +system.cpu1.Branches 10643732 # Number of branches fetched +system.cpu1.op_class::No_OpClass 171960 0.19% 0.19% # Class of executed instruction +system.cpu1.op_class::IntAlu 78085090 84.16% 84.35% # Class of executed instruction +system.cpu1.op_class::IntMult 100662 0.11% 84.45% # Class of executed instruction +system.cpu1.op_class::IntDiv 73682 0.08% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 84.53% # Class of executed instruction +system.cpu1.op_class::MemRead 9231791 9.95% 94.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 5118455 5.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 89331056 # Class of executed instruction +system.cpu1.op_class::total 92781640 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.ruby.network.routers0.throttle0.link_utilization 0.041641 -system.ruby.network.routers0.throttle0.msg_count.Request_Control::2 42522 -system.ruby.network.routers0.throttle0.msg_count.Response_Data::1 918158 -system.ruby.network.routers0.throttle0.msg_count.Response_Control::1 529385 -system.ruby.network.routers0.throttle0.msg_bytes.Request_Control::2 340176 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::1 66107376 -system.ruby.network.routers0.throttle0.msg_bytes.Response_Control::1 4235080 -system.ruby.network.routers0.throttle1.link_utilization 0.023034 -system.ruby.network.routers0.throttle1.msg_count.Control::0 930371 -system.ruby.network.routers0.throttle1.msg_count.Response_Data::1 40359 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::1 16232 -system.ruby.network.routers0.throttle1.msg_count.Response_Control::2 541977 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::0 316333 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Data::1 73 -system.ruby.network.routers0.throttle1.msg_count.Writeback_Control::0 187850 -system.ruby.network.routers0.throttle1.msg_bytes.Control::0 7442968 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Data::1 2905848 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::1 129856 -system.ruby.network.routers0.throttle1.msg_bytes.Response_Control::2 4335816 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-system.ruby.network.routers1.throttle1.msg_count.Response_Control::1 16062 -system.ruby.network.routers1.throttle1.msg_count.Response_Control::2 1215696 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::0 257519 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Data::1 203 -system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::0 921082 -system.ruby.network.routers1.throttle1.msg_bytes.Control::0 13827112 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::1 2413872 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::1 128496 -system.ruby.network.routers1.throttle1.msg_bytes.Response_Control::2 9725568 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::0 18541368 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Data::1 14616 -system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::0 7368656 -system.ruby.network.routers2.throttle0.link_utilization 0.059393 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-system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 886168 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Data::1 12651480 +system.ruby.network.routers3.throttle1.msg_bytes.Response_Control::1 897960 system.ruby.network.routers3.throttle1.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle0.link_utilization 0.000255 -system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 811 +system.ruby.network.routers4.throttle0.msg_count.Response_Data::1 814 system.ruby.network.routers4.throttle0.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58392 +system.ruby.network.routers4.throttle0.msg_bytes.Response_Data::1 58608 system.ruby.network.routers4.throttle0.msg_bytes.Writeback_Control::1 373888 system.ruby.network.routers4.throttle1.link_utilization 0.000224 -system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47547 -system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380376 -system.ruby.network.routers5.throttle0.link_utilization 0.041641 -system.ruby.network.routers5.throttle0.msg_count.Request_Control::2 42522 -system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 918158 -system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 529385 -system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::2 340176 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 66107376 -system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 4235080 -system.ruby.network.routers5.throttle1.link_utilization 0.078728 -system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 38822 -system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 1718478 -system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 1199341 -system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 310576 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 123730416 -system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 9594728 -system.ruby.network.routers5.throttle2.link_utilization 0.059393 -system.ruby.network.routers5.throttle2.msg_count.Control::0 2658760 -system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 198922 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 119247 -system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1757673 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 573852 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 276 -system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 1108932 -system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21270080 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 14322384 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 953976 -system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14061384 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 41317344 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 19872 -system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 8871456 -system.ruby.network.routers5.throttle3.link_utilization 0.005207 -system.ruby.network.routers5.throttle3.msg_count.Control::0 173811 -system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 96823 -system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12100 -system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47547 -system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1390488 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 6971256 -system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 96800 -system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380376 +system.ruby.network.routers4.throttle1.msg_count.Writeback_Control::0 47550 +system.ruby.network.routers4.throttle1.msg_bytes.Writeback_Control::0 380400 +system.ruby.network.routers5.throttle0.link_utilization 0.038084 +system.ruby.network.routers5.throttle0.msg_count.Request_Control::2 42194 +system.ruby.network.routers5.throttle0.msg_count.Response_Data::1 838308 +system.ruby.network.routers5.throttle0.msg_count.Response_Control::1 487492 +system.ruby.network.routers5.throttle0.msg_bytes.Request_Control::2 337552 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Data::1 60358176 +system.ruby.network.routers5.throttle0.msg_bytes.Response_Control::1 3899936 +system.ruby.network.routers5.throttle1.link_utilization 0.082226 +system.ruby.network.routers5.throttle1.msg_count.Request_Control::2 38457 +system.ruby.network.routers5.throttle1.msg_count.Response_Data::1 1794984 +system.ruby.network.routers5.throttle1.msg_count.Response_Control::1 1240066 +system.ruby.network.routers5.throttle1.msg_bytes.Request_Control::2 307656 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Data::1 129238848 +system.ruby.network.routers5.throttle1.msg_bytes.Response_Control::1 9920528 +system.ruby.network.routers5.throttle2.link_utilization 0.059452 +system.ruby.network.routers5.throttle2.msg_count.Control::0 2655106 +system.ruby.network.routers5.throttle2.msg_count.Response_Data::1 199764 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::1 120598 +system.ruby.network.routers5.throttle2.msg_count.Response_Control::2 1756514 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::0 573745 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Data::1 304 +system.ruby.network.routers5.throttle2.msg_count.Writeback_Control::0 1108437 +system.ruby.network.routers5.throttle2.msg_bytes.Control::0 21240848 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Data::1 14383008 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::1 964784 +system.ruby.network.routers5.throttle2.msg_bytes.Response_Control::2 14052112 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::0 41309640 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Data::1 21888 +system.ruby.network.routers5.throttle2.msg_bytes.Writeback_Control::0 8867496 +system.ruby.network.routers5.throttle3.link_utilization 0.005246 +system.ruby.network.routers5.throttle3.msg_count.Control::0 174901 +system.ruby.network.routers5.throttle3.msg_count.Response_Data::1 97440 +system.ruby.network.routers5.throttle3.msg_count.Response_Control::1 12789 +system.ruby.network.routers5.throttle3.msg_count.Writeback_Control::0 47550 +system.ruby.network.routers5.throttle3.msg_bytes.Control::0 1399208 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Data::1 7015680 +system.ruby.network.routers5.throttle3.msg_bytes.Response_Control::1 102312 +system.ruby.network.routers5.throttle3.msg_bytes.Writeback_Control::0 380400 system.ruby.network.routers5.throttle4.link_utilization 0.000255 -system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 811 +system.ruby.network.routers5.throttle4.msg_count.Response_Data::1 814 system.ruby.network.routers5.throttle4.msg_count.Writeback_Control::1 46736 -system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58392 +system.ruby.network.routers5.throttle4.msg_bytes.Response_Data::1 58608 system.ruby.network.routers5.throttle4.msg_bytes.Writeback_Control::1 373888 system.ruby.delayVCHist.vnet_0::bucket_size 4 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_0::max_bucket 39 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::samples 6099217 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::mean 0.754439 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::stdev 2.340051 # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0 | 5524579 90.58% 90.58% | 410 0.01% 90.59% | 573855 9.41% 99.99% | 123 0.00% 100.00% | 205 0.00% 100.00% | 8 0.00% 100.00% | 37 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 -system.ruby.delayVCHist.vnet_0::total 6099217 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::samples 6093802 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::mean 0.755007 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::stdev 2.340941 # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0 | 5519285 90.57% 90.57% | 399 0.01% 90.58% | 573737 9.42% 99.99% | 123 0.00% 100.00% | 210 0.00% 100.00% | 12 0.00% 100.00% | 36 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_0 +system.ruby.delayVCHist.vnet_0::total 6093802 # delay histogram for vnet_0 system.ruby.delayVCHist.vnet_1::bucket_size 2 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_1::max_bucket 19 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::samples 4683807 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::mean 0.044910 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::stdev 0.595023 # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1 | 4656927 99.43% 99.43% | 381 0.01% 99.43% | 370 0.01% 99.44% | 589 0.01% 99.45% | 25416 0.54% 100.00% | 122 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 -system.ruby.delayVCHist.vnet_1::total 4683807 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::samples 4681516 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::mean 0.044663 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::stdev 0.593096 # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1 | 4654718 99.43% 99.43% | 447 0.01% 99.44% | 398 0.01% 99.45% | 648 0.01% 99.46% | 25177 0.54% 100.00% | 123 0.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00% | 1 0.00% 100.00% | 1 0.00% 100.00% # delay histogram for vnet_1 +system.ruby.delayVCHist.vnet_1::total 4681516 # delay histogram for vnet_1 system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::samples 81344 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::mean 0.000123 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::stdev 0.015680 # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2 | 81339 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 -system.ruby.delayVCHist.vnet_2::total 81344 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::samples 80651 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::mean 0.000124 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::stdev 0.015747 # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2 | 80646 99.99% 99.99% | 0 0.00% 99.99% | 5 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 +system.ruby.delayVCHist.vnet_2::total 80651 # delay histogram for vnet_2 system.ruby.LD.latency_hist::bucket_size 16 system.ruby.LD.latency_hist::max_bucket 159 -system.ruby.LD.latency_hist::samples 14937313 -system.ruby.LD.latency_hist::mean 4.746801 -system.ruby.LD.latency_hist::gmean 3.589441 -system.ruby.LD.latency_hist::stdev 6.550511 -system.ruby.LD.latency_hist | 13550250 90.71% 90.71% | 1355967 9.08% 99.79% | 85 0.00% 99.79% | 0 0.00% 99.79% | 9654 0.06% 99.86% | 173 0.00% 99.86% | 20215 0.14% 99.99% | 758 0.01% 100.00% | 186 0.00% 100.00% | 25 0.00% 100.00% -system.ruby.LD.latency_hist::total 14937313 +system.ruby.LD.latency_hist::samples 14920569 +system.ruby.LD.latency_hist::mean 4.752955 +system.ruby.LD.latency_hist::gmean 3.589881 +system.ruby.LD.latency_hist::stdev 6.604009 +system.ruby.LD.latency_hist | 13535034 90.71% 90.71% | 1353292 9.07% 99.78% | 96 0.00% 99.78% | 0 0.00% 99.78% | 9982 0.07% 99.85% | 163 0.00% 99.85% | 20984 0.14% 99.99% | 796 0.01% 100.00% | 200 0.00% 100.00% | 22 0.00% 100.00% +system.ruby.LD.latency_hist::total 14920569 system.ruby.LD.hit_latency_hist::bucket_size 1 system.ruby.LD.hit_latency_hist::max_bucket 9 -system.ruby.LD.hit_latency_hist::samples 13550250 +system.ruby.LD.hit_latency_hist::samples 13535034 system.ruby.LD.hit_latency_hist::mean 3 system.ruby.LD.hit_latency_hist::gmean 3.000000 -system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13550250 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.LD.hit_latency_hist::total 13550250 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 13535034 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 13535034 system.ruby.LD.miss_latency_hist::bucket_size 16 system.ruby.LD.miss_latency_hist::max_bucket 159 -system.ruby.LD.miss_latency_hist::samples 1387063 -system.ruby.LD.miss_latency_hist::mean 21.811342 -system.ruby.LD.miss_latency_hist::gmean 20.705599 -system.ruby.LD.miss_latency_hist::stdev 11.877845 -system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1355967 97.76% 97.76% | 85 0.01% 97.76% | 0 0.00% 97.76% | 9654 0.70% 98.46% | 173 0.01% 98.47% | 20215 1.46% 99.93% | 758 0.05% 99.98% | 186 0.01% 100.00% | 25 0.00% 100.00% -system.ruby.LD.miss_latency_hist::total 1387063 +system.ruby.LD.miss_latency_hist::samples 1385535 +system.ruby.LD.miss_latency_hist::mean 21.877250 +system.ruby.LD.miss_latency_hist::gmean 20.732182 +system.ruby.LD.miss_latency_hist::stdev 12.099590 +system.ruby.LD.miss_latency_hist | 0 0.00% 0.00% | 1353292 97.67% 97.67% | 96 0.01% 97.68% | 0 0.00% 97.68% | 9982 0.72% 98.40% | 163 0.01% 98.41% | 20984 1.51% 99.93% | 796 0.06% 99.98% | 200 0.01% 100.00% | 22 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 1385535 system.ruby.ST.latency_hist::bucket_size 32 system.ruby.ST.latency_hist::max_bucket 319 -system.ruby.ST.latency_hist::samples 9501279 -system.ruby.ST.latency_hist::mean 4.608129 -system.ruby.ST.latency_hist::gmean 3.286792 -system.ruby.ST.latency_hist::stdev 10.643686 -system.ruby.ST.latency_hist | 9375615 98.68% 98.68% | 20 0.00% 98.68% | 64184 0.68% 99.35% | 60844 0.64% 99.99% | 614 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.latency_hist::total 9501279 +system.ruby.ST.latency_hist::samples 9491428 +system.ruby.ST.latency_hist::mean 4.608485 +system.ruby.ST.latency_hist::gmean 3.286938 +system.ruby.ST.latency_hist::stdev 10.640707 +system.ruby.ST.latency_hist | 9365714 98.68% 98.68% | 17 0.00% 98.68% | 64552 0.68% 99.36% | 60510 0.64% 99.99% | 633 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 9491428 system.ruby.ST.hit_latency_hist::bucket_size 1 system.ruby.ST.hit_latency_hist::max_bucket 9 -system.ruby.ST.hit_latency_hist::samples 9151065 +system.ruby.ST.hit_latency_hist::samples 9141411 system.ruby.ST.hit_latency_hist::mean 3 system.ruby.ST.hit_latency_hist::gmean 3.000000 -system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9151065 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.hit_latency_hist::total 9151065 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 9141411 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 9141411 system.ruby.ST.miss_latency_hist::bucket_size 32 system.ruby.ST.miss_latency_hist::max_bucket 319 -system.ruby.ST.miss_latency_hist::samples 350214 -system.ruby.ST.miss_latency_hist::mean 46.628404 -system.ruby.ST.miss_latency_hist::gmean 35.714857 -system.ruby.ST.miss_latency_hist::stdev 35.216783 -system.ruby.ST.miss_latency_hist | 224550 64.12% 64.12% | 20 0.01% 64.12% | 64184 18.33% 82.45% | 60844 17.37% 99.82% | 614 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.ST.miss_latency_hist::total 350214 +system.ruby.ST.miss_latency_hist::samples 350017 +system.ruby.ST.miss_latency_hist::mean 46.617353 +system.ruby.ST.miss_latency_hist::gmean 35.715902 +system.ruby.ST.miss_latency_hist::stdev 35.185303 +system.ruby.ST.miss_latency_hist | 224303 64.08% 64.08% | 17 0.00% 64.09% | 64552 18.44% 82.53% | 60510 17.29% 99.82% | 633 0.18% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 350017 system.ruby.IFETCH.latency_hist::bucket_size 16 system.ruby.IFETCH.latency_hist::max_bucket 159 -system.ruby.IFETCH.latency_hist::samples 126633666 -system.ruby.IFETCH.latency_hist::mean 3.112947 -system.ruby.IFETCH.latency_hist::gmean 3.036567 -system.ruby.IFETCH.latency_hist::stdev 1.654702 -system.ruby.IFETCH.latency_hist | 125816178 99.35% 99.35% | 802052 0.63% 99.99% | 5 0.00% 99.99% | 0 0.00% 99.99% | 3918 0.00% 99.99% | 22 0.00% 99.99% | 11172 0.01% 100.00% | 208 0.00% 100.00% | 111 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.latency_hist::total 126633666 +system.ruby.IFETCH.latency_hist::samples 126544851 +system.ruby.IFETCH.latency_hist::mean 3.112747 +system.ruby.IFETCH.latency_hist::gmean 3.036514 +system.ruby.IFETCH.latency_hist::stdev 1.652226 +system.ruby.IFETCH.latency_hist | 125729046 99.36% 99.36% | 800495 0.63% 99.99% | 4 0.00% 99.99% | 0 0.00% 99.99% | 3856 0.00% 99.99% | 28 0.00% 99.99% | 11079 0.01% 100.00% | 224 0.00% 100.00% | 119 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 126544851 system.ruby.IFETCH.hit_latency_hist::bucket_size 1 system.ruby.IFETCH.hit_latency_hist::max_bucket 9 -system.ruby.IFETCH.hit_latency_hist::samples 125816178 +system.ruby.IFETCH.hit_latency_hist::samples 125729046 system.ruby.IFETCH.hit_latency_hist::mean 3 system.ruby.IFETCH.hit_latency_hist::gmean 3.000000 -system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125816178 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.hit_latency_hist::total 125816178 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 125729046 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 125729046 system.ruby.IFETCH.miss_latency_hist::bucket_size 16 system.ruby.IFETCH.miss_latency_hist::max_bucket 159 -system.ruby.IFETCH.miss_latency_hist::samples 817488 -system.ruby.IFETCH.miss_latency_hist::mean 20.496144 -system.ruby.IFETCH.miss_latency_hist::gmean 19.596306 -system.ruby.IFETCH.miss_latency_hist::stdev 10.954425 -system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 802052 98.11% 98.11% | 5 0.00% 98.11% | 0 0.00% 98.11% | 3918 0.48% 98.59% | 22 0.00% 98.59% | 11172 1.37% 99.96% | 208 0.03% 99.99% | 111 0.01% 100.00% | 0 0.00% 100.00% -system.ruby.IFETCH.miss_latency_hist::total 817488 +system.ruby.IFETCH.miss_latency_hist::samples 815805 +system.ruby.IFETCH.miss_latency_hist::mean 20.488864 +system.ruby.IFETCH.miss_latency_hist::gmean 19.593048 +system.ruby.IFETCH.miss_latency_hist::stdev 10.934190 +system.ruby.IFETCH.miss_latency_hist | 0 0.00% 0.00% | 800495 98.12% 98.12% | 4 0.00% 98.12% | 0 0.00% 98.12% | 3856 0.47% 98.60% | 28 0.00% 98.60% | 11079 1.36% 99.96% | 224 0.03% 99.99% | 119 0.01% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 815805 system.ruby.RMW_Read.latency_hist::bucket_size 16 system.ruby.RMW_Read.latency_hist::max_bucket 159 -system.ruby.RMW_Read.latency_hist::samples 494951 -system.ruby.RMW_Read.latency_hist::mean 5.895220 -system.ruby.RMW_Read.latency_hist::gmean 3.951159 -system.ruby.RMW_Read.latency_hist::stdev 8.211294 -system.ruby.RMW_Read.latency_hist | 429288 86.73% 86.73% | 64260 12.98% 99.72% | 3 0.00% 99.72% | 0 0.00% 99.72% | 989 0.20% 99.92% | 21 0.00% 99.92% | 364 0.07% 99.99% | 22 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.RMW_Read.latency_hist::total 494951 +system.ruby.RMW_Read.latency_hist::samples 494298 +system.ruby.RMW_Read.latency_hist::mean 5.892257 +system.ruby.RMW_Read.latency_hist::gmean 3.949809 +system.ruby.RMW_Read.latency_hist::stdev 8.207792 +system.ruby.RMW_Read.latency_hist | 428816 86.75% 86.75% | 64079 12.96% 99.72% | 2 0.00% 99.72% | 0 0.00% 99.72% | 994 0.20% 99.92% | 20 0.00% 99.92% | 365 0.07% 100.00% | 18 0.00% 100.00% | 3 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 494298 system.ruby.RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.RMW_Read.hit_latency_hist::samples 429288 +system.ruby.RMW_Read.hit_latency_hist::samples 428816 system.ruby.RMW_Read.hit_latency_hist::mean 3 system.ruby.RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 429288 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.RMW_Read.hit_latency_hist::total 429288 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 428816 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 428816 system.ruby.RMW_Read.miss_latency_hist::bucket_size 16 system.ruby.RMW_Read.miss_latency_hist::max_bucket 159 -system.ruby.RMW_Read.miss_latency_hist::samples 65663 -system.ruby.RMW_Read.miss_latency_hist::mean 24.823432 -system.ruby.RMW_Read.miss_latency_hist::gmean 23.914448 -system.ruby.RMW_Read.miss_latency_hist::stdev 9.754848 -system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64260 97.86% 97.86% | 3 0.00% 97.87% | 0 0.00% 97.87% | 989 1.51% 99.37% | 21 0.03% 99.41% | 364 0.55% 99.96% | 22 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00% -system.ruby.RMW_Read.miss_latency_hist::total 65663 +system.ruby.RMW_Read.miss_latency_hist::samples 65482 +system.ruby.RMW_Read.miss_latency_hist::mean 24.832519 +system.ruby.RMW_Read.miss_latency_hist::gmean 23.924296 +system.ruby.RMW_Read.miss_latency_hist::stdev 9.747837 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 64079 97.86% 97.86% | 2 0.00% 97.86% | 0 0.00% 97.86% | 994 1.52% 99.38% | 20 0.03% 99.41% | 365 0.56% 99.97% | 18 0.03% 99.99% | 3 0.00% 100.00% | 1 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 65482 system.ruby.Locked_RMW_Read.latency_hist::bucket_size 16 system.ruby.Locked_RMW_Read.latency_hist::max_bucket 159 -system.ruby.Locked_RMW_Read.latency_hist::samples 339622 -system.ruby.Locked_RMW_Read.latency_hist::mean 5.235927 -system.ruby.Locked_RMW_Read.latency_hist::gmean 3.761812 -system.ruby.Locked_RMW_Read.latency_hist::stdev 6.715360 -system.ruby.Locked_RMW_Read.latency_hist | 301290 88.71% 88.71% | 38000 11.19% 99.90% | 7 0.00% 99.90% | 0 0.00% 99.90% | 176 0.05% 99.96% | 2 0.00% 99.96% | 134 0.04% 100.00% | 12 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.latency_hist::total 339622 +system.ruby.Locked_RMW_Read.latency_hist::samples 339492 +system.ruby.Locked_RMW_Read.latency_hist::mean 5.237555 +system.ruby.Locked_RMW_Read.latency_hist::gmean 3.760998 +system.ruby.Locked_RMW_Read.latency_hist::stdev 6.749704 +system.ruby.Locked_RMW_Read.latency_hist | 301225 88.73% 88.73% | 37910 11.17% 99.89% | 7 0.00% 99.90% | 0 0.00% 99.90% | 190 0.06% 99.95% | 1 0.00% 99.95% | 148 0.04% 100.00% | 10 0.00% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 339492 system.ruby.Locked_RMW_Read.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Read.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301290 +system.ruby.Locked_RMW_Read.hit_latency_hist::samples 301225 system.ruby.Locked_RMW_Read.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Read.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301290 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.hit_latency_hist::total 301290 +system.ruby.Locked_RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 301225 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.hit_latency_hist::total 301225 system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 16 system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 159 -system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38332 -system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.810341 -system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.276488 -system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.169146 -system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 38000 99.13% 99.13% | 7 0.02% 99.15% | 0 0.00% 99.15% | 176 0.46% 99.61% | 2 0.01% 99.62% | 134 0.35% 99.97% | 12 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Read.miss_latency_hist::total 38332 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 38267 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 22.850838 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 22.292446 +system.ruby.Locked_RMW_Read.miss_latency_hist::stdev 7.385228 +system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 37910 99.07% 99.07% | 7 0.02% 99.09% | 0 0.00% 99.09% | 190 0.50% 99.58% | 1 0.00% 99.58% | 148 0.39% 99.97% | 10 0.03% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 38267 system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.latency_hist::samples 339622 +system.ruby.Locked_RMW_Write.latency_hist::samples 339492 system.ruby.Locked_RMW_Write.latency_hist::mean 3 system.ruby.Locked_RMW_Write.latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.latency_hist::total 339622 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339492 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 339492 system.ruby.Locked_RMW_Write.hit_latency_hist::bucket_size 1 system.ruby.Locked_RMW_Write.hit_latency_hist::max_bucket 9 -system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339622 +system.ruby.Locked_RMW_Write.hit_latency_hist::samples 339492 system.ruby.Locked_RMW_Write.hit_latency_hist::mean 3 system.ruby.Locked_RMW_Write.hit_latency_hist::gmean 3.000000 -system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339622 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% -system.ruby.Locked_RMW_Write.hit_latency_hist::total 339622 -system.ruby.L1Cache_Controller.Load | 6583252 44.07% 44.07% | 8354061 55.93% 100.00% -system.ruby.L1Cache_Controller.Load::total 14937313 -system.ruby.L1Cache_Controller.Ifetch | 70404850 55.60% 55.60% | 56228821 44.40% 100.00% -system.ruby.L1Cache_Controller.Ifetch::total 126633671 -system.ruby.L1Cache_Controller.Store | 5551807 52.01% 52.01% | 5123667 47.99% 100.00% -system.ruby.L1Cache_Controller.Store::total 10675474 -system.ruby.L1Cache_Controller.Inv | 16305 50.06% 50.06% | 16265 49.94% 100.00% -system.ruby.L1Cache_Controller.Inv::total 32570 -system.ruby.L1Cache_Controller.L1_Replacement | 902922 34.67% 34.67% | 1701187 65.33% 100.00% -system.ruby.L1Cache_Controller.L1_Replacement::total 2604109 -system.ruby.L1Cache_Controller.Fwd_GETX | 12075 51.03% 51.03% | 11588 48.97% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETX::total 23663 -system.ruby.L1Cache_Controller.Fwd_GETS | 14138 56.31% 56.31% | 10969 43.69% 100.00% -system.ruby.L1Cache_Controller.Fwd_GETS::total 25107 +system.ruby.Locked_RMW_Write.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 339492 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.hit_latency_hist::total 339492 +system.ruby.L1Cache_Controller.Load | 6084011 40.78% 40.78% | 8836558 59.22% 100.00% +system.ruby.L1Cache_Controller.Load::total 14920569 +system.ruby.L1Cache_Controller.Ifetch | 67747645 53.54% 53.54% | 58797210 46.46% 100.00% +system.ruby.L1Cache_Controller.Ifetch::total 126544855 +system.ruby.L1Cache_Controller.Store | 5172126 48.50% 48.50% | 5492584 51.50% 100.00% +system.ruby.L1Cache_Controller.Store::total 10664710 +system.ruby.L1Cache_Controller.Inv | 16156 50.14% 50.14% | 16063 49.86% 100.00% +system.ruby.L1Cache_Controller.Inv::total 32219 +system.ruby.L1Cache_Controller.L1_Replacement | 823129 31.64% 31.64% | 1778072 68.36% 100.00% +system.ruby.L1Cache_Controller.L1_Replacement::total 2601201 +system.ruby.L1Cache_Controller.Fwd_GETX | 12034 51.06% 51.06% | 11535 48.94% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETX::total 23569 +system.ruby.L1Cache_Controller.Fwd_GETS | 14000 56.32% 56.32% | 10859 43.68% 100.00% +system.ruby.L1Cache_Controller.Fwd_GETS::total 24859 system.ruby.L1Cache_Controller.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.Data | 776 45.81% 45.81% | 918 54.19% 100.00% -system.ruby.L1Cache_Controller.Data::total 1694 -system.ruby.L1Cache_Controller.Data_Exclusive | 274584 21.48% 21.48% | 1003769 78.52% 100.00% -system.ruby.L1Cache_Controller.Data_Exclusive::total 1278353 -system.ruby.L1Cache_Controller.DataS_fromL1 | 10969 43.68% 43.68% | 14142 56.32% 100.00% -system.ruby.L1Cache_Controller.DataS_fromL1::total 25111 -system.ruby.L1Cache_Controller.Data_all_Acks | 631829 47.45% 47.45% | 699649 52.55% 100.00% -system.ruby.L1Cache_Controller.Data_all_Acks::total 1331478 -system.ruby.L1Cache_Controller.Ack | 12213 55.20% 55.20% | 9911 44.80% 100.00% -system.ruby.L1Cache_Controller.Ack::total 22124 -system.ruby.L1Cache_Controller.Ack_all | 12989 54.53% 54.53% | 10829 45.47% 100.00% -system.ruby.L1Cache_Controller.Ack_all::total 23818 -system.ruby.L1Cache_Controller.WB_Ack | 504183 29.96% 29.96% | 1178601 70.04% 100.00% -system.ruby.L1Cache_Controller.WB_Ack::total 1682784 -system.ruby.L1Cache_Controller.NP.Load | 306639 22.41% 22.41% | 1061542 77.59% 100.00% -system.ruby.L1Cache_Controller.NP.Load::total 1368181 -system.ruby.L1Cache_Controller.NP.Ifetch | 358742 43.90% 43.90% | 458479 56.10% 100.00% -system.ruby.L1Cache_Controller.NP.Ifetch::total 817221 -system.ruby.L1Cache_Controller.NP.Store | 238565 56.70% 56.70% | 182190 43.30% 100.00% -system.ruby.L1Cache_Controller.NP.Store::total 420755 -system.ruby.L1Cache_Controller.NP.Inv | 5465 60.99% 60.99% | 3496 39.01% 100.00% -system.ruby.L1Cache_Controller.NP.Inv::total 8961 -system.ruby.L1Cache_Controller.I.Load | 8460 44.80% 44.80% | 10422 55.20% 100.00% -system.ruby.L1Cache_Controller.I.Load::total 18882 -system.ruby.L1Cache_Controller.I.Ifetch | 106 39.70% 39.70% | 161 60.30% 100.00% -system.ruby.L1Cache_Controller.I.Ifetch::total 267 -system.ruby.L1Cache_Controller.I.Store | 5646 49.83% 49.83% | 5684 50.17% 100.00% -system.ruby.L1Cache_Controller.I.Store::total 11330 -system.ruby.L1Cache_Controller.I.L1_Replacement | 8703 52.15% 52.15% | 7984 47.85% 100.00% -system.ruby.L1Cache_Controller.I.L1_Replacement::total 16687 -system.ruby.L1Cache_Controller.S.Load | 576531 53.67% 53.67% | 497753 46.33% 100.00% -system.ruby.L1Cache_Controller.S.Load::total 1074284 -system.ruby.L1Cache_Controller.S.Ifetch | 70045998 55.67% 55.67% | 55770180 44.33% 100.00% -system.ruby.L1Cache_Controller.S.Ifetch::total 125816178 -system.ruby.L1Cache_Controller.S.Store | 12213 55.20% 55.20% | 9911 44.80% 100.00% -system.ruby.L1Cache_Controller.S.Store::total 22124 -system.ruby.L1Cache_Controller.S.Inv | 10713 46.06% 46.06% | 12547 53.94% 100.00% -system.ruby.L1Cache_Controller.S.Inv::total 23260 -system.ruby.L1Cache_Controller.S.L1_Replacement | 390036 43.12% 43.12% | 514602 56.88% 100.00% -system.ruby.L1Cache_Controller.S.L1_Replacement::total 904638 -system.ruby.L1Cache_Controller.E.Load | 1291134 33.50% 33.50% | 2563123 66.50% 100.00% -system.ruby.L1Cache_Controller.E.Load::total 3854257 -system.ruby.L1Cache_Controller.E.Store | 85252 51.14% 51.14% | 81438 48.86% 100.00% -system.ruby.L1Cache_Controller.E.Store::total 166690 -system.ruby.L1Cache_Controller.E.Inv | 54 73.97% 73.97% | 19 26.03% 100.00% -system.ruby.L1Cache_Controller.E.Inv::total 73 -system.ruby.L1Cache_Controller.E.L1_Replacement | 187850 16.94% 16.94% | 921082 83.06% 100.00% -system.ruby.L1Cache_Controller.E.L1_Replacement::total 1108932 -system.ruby.L1Cache_Controller.E.Fwd_GETX | 211 75.09% 75.09% | 70 24.91% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETX::total 281 -system.ruby.L1Cache_Controller.E.Fwd_GETS | 1011 47.55% 47.55% | 1115 52.45% 100.00% -system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2126 -system.ruby.L1Cache_Controller.M.Load | 4400488 51.04% 51.04% | 4221221 48.96% 100.00% -system.ruby.L1Cache_Controller.M.Load::total 8621709 -system.ruby.L1Cache_Controller.M.Store | 5210131 51.82% 51.82% | 4844444 48.18% 100.00% -system.ruby.L1Cache_Controller.M.Store::total 10054575 -system.ruby.L1Cache_Controller.M.Inv | 73 26.45% 26.45% | 203 73.55% 100.00% -system.ruby.L1Cache_Controller.M.Inv::total 276 -system.ruby.L1Cache_Controller.M.L1_Replacement | 316333 55.12% 55.12% | 257519 44.88% 100.00% -system.ruby.L1Cache_Controller.M.L1_Replacement::total 573852 -system.ruby.L1Cache_Controller.M.Fwd_GETX | 11864 50.74% 50.74% | 11518 49.26% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23382 -system.ruby.L1Cache_Controller.M.Fwd_GETS | 13127 57.12% 57.12% | 9854 42.88% 100.00% -system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22981 +system.ruby.L1Cache_Controller.Data | 734 41.99% 41.99% | 1014 58.01% 100.00% +system.ruby.L1Cache_Controller.Data::total 1748 +system.ruby.L1Cache_Controller.Data_Exclusive | 250298 19.59% 19.59% | 1027587 80.41% 100.00% +system.ruby.L1Cache_Controller.Data_Exclusive::total 1277885 +system.ruby.L1Cache_Controller.DataS_fromL1 | 10859 43.68% 43.68% | 14004 56.32% 100.00% +system.ruby.L1Cache_Controller.DataS_fromL1::total 24863 +system.ruby.L1Cache_Controller.Data_all_Acks | 576417 43.38% 43.38% | 752379 56.62% 100.00% +system.ruby.L1Cache_Controller.Data_all_Acks::total 1328796 +system.ruby.L1Cache_Controller.Ack | 11937 54.72% 54.72% | 9877 45.28% 100.00% +system.ruby.L1Cache_Controller.Ack::total 21814 +system.ruby.L1Cache_Controller.Ack_all | 12671 53.78% 53.78% | 10891 46.22% 100.00% +system.ruby.L1Cache_Controller.Ack_all::total 23562 +system.ruby.L1Cache_Controller.WB_Ack | 462884 27.52% 27.52% | 1219298 72.48% 100.00% +system.ruby.L1Cache_Controller.WB_Ack::total 1682182 +system.ruby.L1Cache_Controller.NP.Load | 278313 20.36% 20.36% | 1088632 79.64% 100.00% +system.ruby.L1Cache_Controller.NP.Load::total 1366945 +system.ruby.L1Cache_Controller.NP.Ifetch | 324200 39.75% 39.75% | 491378 60.25% 100.00% +system.ruby.L1Cache_Controller.NP.Ifetch::total 815578 +system.ruby.L1Cache_Controller.NP.Store | 221640 52.68% 52.68% | 199086 47.32% 100.00% +system.ruby.L1Cache_Controller.NP.Store::total 420726 +system.ruby.L1Cache_Controller.NP.Inv | 5298 59.26% 59.26% | 3642 40.74% 100.00% +system.ruby.L1Cache_Controller.NP.Inv::total 8940 +system.ruby.L1Cache_Controller.I.Load | 8389 45.13% 45.13% | 10201 54.87% 100.00% +system.ruby.L1Cache_Controller.I.Load::total 18590 +system.ruby.L1Cache_Controller.I.Ifetch | 98 43.17% 43.17% | 129 56.83% 100.00% +system.ruby.L1Cache_Controller.I.Ifetch::total 227 +system.ruby.L1Cache_Controller.I.Store | 5668 50.49% 50.49% | 5558 49.51% 100.00% +system.ruby.L1Cache_Controller.I.Store::total 11226 +system.ruby.L1Cache_Controller.I.L1_Replacement | 8737 52.26% 52.26% | 7980 47.74% 100.00% +system.ruby.L1Cache_Controller.I.L1_Replacement::total 16717 +system.ruby.L1Cache_Controller.S.Load | 550351 51.54% 51.54% | 517372 48.46% 100.00% +system.ruby.L1Cache_Controller.S.Load::total 1067723 +system.ruby.L1Cache_Controller.S.Ifetch | 67423344 53.63% 53.63% | 58305702 46.37% 100.00% +system.ruby.L1Cache_Controller.S.Ifetch::total 125729046 +system.ruby.L1Cache_Controller.S.Store | 11937 54.72% 54.72% | 9877 45.28% 100.00% +system.ruby.L1Cache_Controller.S.Store::total 21814 +system.ruby.L1Cache_Controller.S.Inv | 10724 46.84% 46.84% | 12170 53.16% 100.00% +system.ruby.L1Cache_Controller.S.Inv::total 22894 +system.ruby.L1Cache_Controller.S.L1_Replacement | 351508 38.96% 38.96% | 550794 61.04% 100.00% +system.ruby.L1Cache_Controller.S.L1_Replacement::total 902302 +system.ruby.L1Cache_Controller.E.Load | 1120765 29.13% 29.13% | 2726807 70.87% 100.00% +system.ruby.L1Cache_Controller.E.Load::total 3847572 +system.ruby.L1Cache_Controller.E.Store | 80620 48.39% 48.39% | 85993 51.61% 100.00% +system.ruby.L1Cache_Controller.E.Store::total 166613 +system.ruby.L1Cache_Controller.E.Inv | 57 70.37% 70.37% | 24 29.63% 100.00% +system.ruby.L1Cache_Controller.E.Inv::total 81 +system.ruby.L1Cache_Controller.E.L1_Replacement | 168221 15.18% 15.18% | 940216 84.82% 100.00% +system.ruby.L1Cache_Controller.E.L1_Replacement::total 1108437 +system.ruby.L1Cache_Controller.E.Fwd_GETX | 207 58.81% 58.81% | 145 41.19% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETX::total 352 +system.ruby.L1Cache_Controller.E.Fwd_GETS | 1001 46.45% 46.45% | 1154 53.55% 100.00% +system.ruby.L1Cache_Controller.E.Fwd_GETS::total 2155 +system.ruby.L1Cache_Controller.M.Load | 4126193 47.87% 47.87% | 4493546 52.13% 100.00% +system.ruby.L1Cache_Controller.M.Load::total 8619739 +system.ruby.L1Cache_Controller.M.Store | 4852261 48.31% 48.31% | 5192070 51.69% 100.00% +system.ruby.L1Cache_Controller.M.Store::total 10044331 +system.ruby.L1Cache_Controller.M.Inv | 77 25.33% 25.33% | 227 74.67% 100.00% +system.ruby.L1Cache_Controller.M.Inv::total 304 +system.ruby.L1Cache_Controller.M.L1_Replacement | 294663 51.36% 51.36% | 279082 48.64% 100.00% +system.ruby.L1Cache_Controller.M.L1_Replacement::total 573745 +system.ruby.L1Cache_Controller.M.Fwd_GETX | 11827 50.94% 50.94% | 11390 49.06% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETX::total 23217 +system.ruby.L1Cache_Controller.M.Fwd_GETS | 12999 57.25% 57.25% | 9705 42.75% 100.00% +system.ruby.L1Cache_Controller.M.Fwd_GETS::total 22704 system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR | 4 100.00% 100.00% | 0 0.00% 100.00% system.ruby.L1Cache_Controller.M.Fwd_GET_INSTR::total 4 -system.ruby.L1Cache_Controller.IS.Data_Exclusive | 274584 21.48% 21.48% | 1003769 78.52% 100.00% -system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1278353 -system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10969 43.68% 43.68% | 14142 56.32% 100.00% -system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 25111 -system.ruby.L1Cache_Controller.IS.Data_all_Acks | 388394 43.10% 43.10% | 512693 56.90% 100.00% -system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 901087 -system.ruby.L1Cache_Controller.IM.Data | 776 45.81% 45.81% | 918 54.19% 100.00% -system.ruby.L1Cache_Controller.IM.Data::total 1694 -system.ruby.L1Cache_Controller.IM.Data_all_Acks | 243435 56.56% 56.56% | 186956 43.44% 100.00% -system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 430391 -system.ruby.L1Cache_Controller.SM.Ack | 12213 55.20% 55.20% | 9911 44.80% 100.00% -system.ruby.L1Cache_Controller.SM.Ack::total 22124 -system.ruby.L1Cache_Controller.SM.Ack_all | 12989 54.53% 54.53% | 10829 45.47% 100.00% -system.ruby.L1Cache_Controller.SM.Ack_all::total 23818 -system.ruby.L1Cache_Controller.M_I.Ifetch | 4 80.00% 80.00% | 1 20.00% 100.00% -system.ruby.L1Cache_Controller.M_I.Ifetch::total 5 -system.ruby.L1Cache_Controller.M_I.WB_Ack | 504183 29.96% 29.96% | 1178601 70.04% 100.00% -system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1682784 -system.ruby.L2Cache_Controller.L1_GET_INSTR 817488 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETS 1387273 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_GETX 432085 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_UPGRADE 22124 0.00% 0.00% -system.ruby.L2Cache_Controller.L1_PUTX 1682784 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement 94886 0.00% 0.00% -system.ruby.L2Cache_Controller.L2_Replacement_clean 12189 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Data 173811 0.00% 0.00% -system.ruby.L2Cache_Controller.Mem_Ack 108923 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data 23261 0.00% 0.00% -system.ruby.L2Cache_Controller.WB_Data_clean 2126 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack 1643 0.00% 0.00% -system.ruby.L2Cache_Controller.Ack_all 6833 0.00% 0.00% -system.ruby.L2Cache_Controller.Unblock 25111 0.00% 0.00% -system.ruby.L2Cache_Controller.Exclusive_Unblock 1732562 0.00% 0.00% -system.ruby.L2Cache_Controller.MEM_Inv 3696 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15431 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETS 31011 0.00% 0.00% -system.ruby.L2Cache_Controller.NP.L1_GETX 127369 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 802025 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETS 83603 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_GETX 1729 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L1_UPGRADE 22124 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement 253 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6503 0.00% 0.00% -system.ruby.L2Cache_Controller.SS.MEM_Inv 4 0.00% 0.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive | 250298 19.59% 19.59% | 1027587 80.41% 100.00% +system.ruby.L1Cache_Controller.IS.Data_Exclusive::total 1277885 +system.ruby.L1Cache_Controller.IS.DataS_fromL1 | 10859 43.68% 43.68% | 14004 56.32% 100.00% +system.ruby.L1Cache_Controller.IS.DataS_fromL1::total 24863 +system.ruby.L1Cache_Controller.IS.Data_all_Acks | 349843 38.93% 38.93% | 548749 61.07% 100.00% +system.ruby.L1Cache_Controller.IS.Data_all_Acks::total 898592 +system.ruby.L1Cache_Controller.IM.Data | 734 41.99% 41.99% | 1014 58.01% 100.00% +system.ruby.L1Cache_Controller.IM.Data::total 1748 +system.ruby.L1Cache_Controller.IM.Data_all_Acks | 226574 52.67% 52.67% | 203630 47.33% 100.00% +system.ruby.L1Cache_Controller.IM.Data_all_Acks::total 430204 +system.ruby.L1Cache_Controller.SM.Ack | 11937 54.72% 54.72% | 9877 45.28% 100.00% +system.ruby.L1Cache_Controller.SM.Ack::total 21814 +system.ruby.L1Cache_Controller.SM.Ack_all | 12671 53.78% 53.78% | 10891 46.22% 100.00% +system.ruby.L1Cache_Controller.SM.Ack_all::total 23562 +system.ruby.L1Cache_Controller.M_I.Ifetch | 3 75.00% 75.00% | 1 25.00% 100.00% +system.ruby.L1Cache_Controller.M_I.Ifetch::total 4 +system.ruby.L1Cache_Controller.M_I.WB_Ack | 462884 27.52% 27.52% | 1219298 72.48% 100.00% +system.ruby.L1Cache_Controller.M_I.WB_Ack::total 1682182 +system.ruby.L2Cache_Controller.L1_GET_INSTR 815805 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETS 1385683 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_GETX 431953 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_UPGRADE 21814 0.00% 0.00% +system.ruby.L2Cache_Controller.L1_PUTX 1682182 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement 95349 0.00% 0.00% +system.ruby.L2Cache_Controller.L2_Replacement_clean 12864 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Data 174901 0.00% 0.00% +system.ruby.L2Cache_Controller.Mem_Ack 110229 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data 23012 0.00% 0.00% +system.ruby.L2Cache_Controller.WB_Data_clean 2155 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack 1666 0.00% 0.00% +system.ruby.L2Cache_Controller.Ack_all 6687 0.00% 0.00% +system.ruby.L2Cache_Controller.Unblock 24863 0.00% 0.00% +system.ruby.L2Cache_Controller.Exclusive_Unblock 1731651 0.00% 0.00% +system.ruby.L2Cache_Controller.MEM_Inv 4032 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GET_INSTR 15306 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETS 32147 0.00% 0.00% +system.ruby.L2Cache_Controller.NP.L1_GETX 127448 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GET_INSTR 800467 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETS 82791 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_GETX 1783 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L1_UPGRADE 21814 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement 268 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.L2_Replacement_clean 6335 0.00% 0.00% +system.ruby.L2Cache_Controller.SS.MEM_Inv 3 0.00% 0.00% system.ruby.L2Cache_Controller.M.L1_GET_INSTR 28 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETS 1247342 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L1_GETX 279324 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement 94480 0.00% 0.00% -system.ruby.L2Cache_Controller.M.L2_Replacement_clean 5571 0.00% 0.00% -system.ruby.L2Cache_Controller.M.MEM_Inv 1763 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETS 1245738 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L1_GETX 279152 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement 94920 0.00% 0.00% +system.ruby.L2Cache_Controller.M.L2_Replacement_clean 6421 0.00% 0.00% +system.ruby.L2Cache_Controller.M.MEM_Inv 1897 0.00% 0.00% system.ruby.L2Cache_Controller.MT.L1_GET_INSTR 4 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETS 25107 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_GETX 23663 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L1_PUTX 1682784 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement 153 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 115 0.00% 0.00% -system.ruby.L2Cache_Controller.MT.MEM_Inv 81 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.Mem_Ack 108923 0.00% 0.00% -system.ruby.L2Cache_Controller.M_I.MEM_Inv 1763 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.WB_Data 187 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.Ack_all 47 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_I.MEM_Inv 81 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.WB_Data 89 0.00% 0.00% -system.ruby.L2Cache_Controller.MCT_I.Ack_all 26 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack 1386 0.00% 0.00% -system.ruby.L2Cache_Controller.I_I.Ack_all 6503 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack 257 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.Ack_all 257 0.00% 0.00% -system.ruby.L2Cache_Controller.S_I.MEM_Inv 4 0.00% 0.00% -system.ruby.L2Cache_Controller.ISS.Mem_Data 31011 0.00% 0.00% -system.ruby.L2Cache_Controller.IS.Mem_Data 15431 0.00% 0.00% -system.ruby.L2Cache_Controller.IM.Mem_Data 127369 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.L1_GETS 164 0.00% 0.00% -system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23853 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.L1_GETS 46 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708709 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22985 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2126 0.00% 0.00% -system.ruby.L2Cache_Controller.MT_SB.Unblock 25111 0.00% 0.00% -system.ruby.DMA_Controller.ReadRequest 811 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETS 24859 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_GETX 23569 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L1_PUTX 1682182 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement 161 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.L2_Replacement_clean 108 0.00% 0.00% +system.ruby.L2Cache_Controller.MT.MEM_Inv 116 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.Mem_Ack 110229 0.00% 0.00% +system.ruby.L2Cache_Controller.M_I.MEM_Inv 1897 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.WB_Data 229 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.Ack_all 48 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_I.MEM_Inv 116 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.WB_Data 75 0.00% 0.00% +system.ruby.L2Cache_Controller.MCT_I.Ack_all 33 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack 1395 0.00% 0.00% +system.ruby.L2Cache_Controller.I_I.Ack_all 6335 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack 271 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.Ack_all 271 0.00% 0.00% +system.ruby.L2Cache_Controller.S_I.MEM_Inv 3 0.00% 0.00% +system.ruby.L2Cache_Controller.ISS.Mem_Data 32147 0.00% 0.00% +system.ruby.L2Cache_Controller.IS.Mem_Data 15306 0.00% 0.00% +system.ruby.L2Cache_Controller.IM.Mem_Data 127448 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.L1_GETS 111 0.00% 0.00% +system.ruby.L2Cache_Controller.SS_MB.Exclusive_Unblock 23597 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETS 37 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.L1_GETX 1 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_MB.Exclusive_Unblock 1708054 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data 22706 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.WB_Data_clean 2155 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IIB.Unblock 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_IB.WB_Data 2 0.00% 0.00% +system.ruby.L2Cache_Controller.MT_SB.Unblock 24861 0.00% 0.00% +system.ruby.DMA_Controller.ReadRequest 814 0.00% 0.00% system.ruby.DMA_Controller.WriteRequest 46736 0.00% 0.00% -system.ruby.DMA_Controller.Data 811 0.00% 0.00% +system.ruby.DMA_Controller.Data 814 0.00% 0.00% system.ruby.DMA_Controller.Ack 46736 0.00% 0.00% -system.ruby.DMA_Controller.READY.ReadRequest 811 0.00% 0.00% +system.ruby.DMA_Controller.READY.ReadRequest 814 0.00% 0.00% system.ruby.DMA_Controller.READY.WriteRequest 46736 0.00% 0.00% -system.ruby.DMA_Controller.BUSY_RD.Data 811 0.00% 0.00% +system.ruby.DMA_Controller.BUSY_RD.Data 814 0.00% 0.00% system.ruby.DMA_Controller.BUSY_WR.Ack 46736 0.00% 0.00% -system.ruby.Directory_Controller.Fetch 173811 0.00% 0.00% -system.ruby.Directory_Controller.Data 96823 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Data 174271 0.00% 0.00% -system.ruby.Directory_Controller.Memory_Ack 142062 0.00% 0.00% -system.ruby.Directory_Controller.DMA_READ 811 0.00% 0.00% +system.ruby.Directory_Controller.Fetch 174901 0.00% 0.00% +system.ruby.Directory_Controller.Data 97440 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Data 175364 0.00% 0.00% +system.ruby.Directory_Controller.Memory_Ack 142511 0.00% 0.00% +system.ruby.Directory_Controller.DMA_READ 814 0.00% 0.00% system.ruby.Directory_Controller.DMA_WRITE 46736 0.00% 0.00% -system.ruby.Directory_Controller.CleanReplacement 12100 0.00% 0.00% -system.ruby.Directory_Controller.I.Fetch 173811 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_READ 460 0.00% 0.00% -system.ruby.Directory_Controller.I.DMA_WRITE 45239 0.00% 0.00% -system.ruby.Directory_Controller.ID.Memory_Data 460 0.00% 0.00% -system.ruby.Directory_Controller.ID_W.Memory_Ack 45239 0.00% 0.00% -system.ruby.Directory_Controller.M.Data 94975 0.00% 0.00% +system.ruby.Directory_Controller.CleanReplacement 12789 0.00% 0.00% +system.ruby.Directory_Controller.I.Fetch 174901 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_READ 463 0.00% 0.00% +system.ruby.Directory_Controller.I.DMA_WRITE 45071 0.00% 0.00% +system.ruby.Directory_Controller.ID.Memory_Data 463 0.00% 0.00% +system.ruby.Directory_Controller.ID_W.Memory_Ack 45071 0.00% 0.00% +system.ruby.Directory_Controller.M.Data 95424 0.00% 0.00% system.ruby.Directory_Controller.M.DMA_READ 351 0.00% 0.00% -system.ruby.Directory_Controller.M.DMA_WRITE 1497 0.00% 0.00% -system.ruby.Directory_Controller.M.CleanReplacement 12100 0.00% 0.00% -system.ruby.Directory_Controller.IM.Memory_Data 173811 0.00% 0.00% -system.ruby.Directory_Controller.MI.Memory_Ack 94975 0.00% 0.00% +system.ruby.Directory_Controller.M.DMA_WRITE 1665 0.00% 0.00% +system.ruby.Directory_Controller.M.CleanReplacement 12789 0.00% 0.00% +system.ruby.Directory_Controller.IM.Memory_Data 174901 0.00% 0.00% +system.ruby.Directory_Controller.MI.Memory_Ack 95424 0.00% 0.00% system.ruby.Directory_Controller.M_DRD.Data 351 0.00% 0.00% system.ruby.Directory_Controller.M_DRDI.Memory_Ack 351 0.00% 0.00% -system.ruby.Directory_Controller.M_DWR.Data 1497 0.00% 0.00% -system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1497 0.00% 0.00% +system.ruby.Directory_Controller.M_DWR.Data 1665 0.00% 0.00% +system.ruby.Directory_Controller.M_DWRI.Memory_Ack 1665 0.00% 0.00% ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index f26bf1c54..cf390c4d1 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,159 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.137881 # Number of seconds simulated -sim_ticks 5137881357500 # Number of ticks simulated -final_tick 5137881357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.133872 # Number of seconds simulated +sim_ticks 5133872107500 # Number of ticks simulated +final_tick 5133872107500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 401147 # Simulator instruction rate (inst/s) -host_op_rate 797370 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8430324111 # Simulator tick rate (ticks/s) -host_mem_usage 944704 # Number of bytes of host memory used -host_seconds 609.45 # Real time elapsed on the host -sim_insts 244480058 # Number of instructions simulated -sim_ops 485958826 # Number of ops (including micro ops) simulated +host_inst_rate 287663 # Simulator instruction rate (inst/s) +host_op_rate 571806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6046720341 # Simulator tick rate (ticks/s) +host_mem_usage 1024224 # Number of bytes of host memory used +host_seconds 849.03 # Real time elapsed on the host +sim_insts 244235751 # Number of instructions simulated +sim_ops 485482573 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 396800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5697984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 149888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1826880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 430976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2905472 # Number of bytes read from this memory -system.physmem.bytes_read::total 11438656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 396800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 149888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 430976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 977664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6187584 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5572928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 164928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1639680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 412864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3220800 # Number of bytes read from this memory +system.physmem.bytes_read::total 11438848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 164928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 412864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 974528 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6205312 # Number of bytes written to this memory system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory -system.physmem.bytes_written::total 9177664 # Number of bytes written to this memory +system.physmem.bytes_written::total 9195392 # Number of bytes written to this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6200 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 89031 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 28545 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6734 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 45398 # Number of read requests responded to by this memory -system.physmem.num_reads::total 178729 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96681 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6199 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 87077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 25620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 35 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 6451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 50325 # Number of read requests responded to by this memory +system.physmem.num_reads::total 178732 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96958 # Number of write requests responded to by this memory system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143401 # Number of write requests responded to by this memory -system.physmem.bw_read::pc.south_bridge.ide 5518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 77230 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1109014 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 29173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 355571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 83882 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 565500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2226337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 77230 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 29173 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 83882 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 190285 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1204307 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::pc.south_bridge.ide 581968 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1786274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1204307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 587486 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 77230 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1109014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 29173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 355571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 386 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 83882 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 565500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4012611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 83494 # Number of read requests accepted -system.physmem.writeReqs 76163 # Number of write requests accepted -system.physmem.readBursts 83494 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 76163 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5331584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 12032 # Total number of bytes read from write queue -system.physmem.bytesWritten 4872768 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5343616 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4874432 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 188 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 143678 # Number of write requests responded to by this memory +system.physmem.bw_read::pc.south_bridge.ide 5523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 77278 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1085521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 32125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 319385 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 80420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 627363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2228113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 77278 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 32125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 80420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 189823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1208700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::pc.south_bridge.ide 582422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1791122 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1208700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 587945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 77278 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1085521 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 32125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 319385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 80420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 627363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4019235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 85451 # Number of read requests accepted +system.physmem.writeReqs 85019 # Number of write requests accepted +system.physmem.readBursts 85451 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 85019 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5457024 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 11840 # Total number of bytes read from write queue +system.physmem.bytesWritten 5440128 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5468864 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5441216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 185 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 873 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 4736 # Per bank write bursts -system.physmem.perBankRdBursts::1 4757 # Per bank write bursts -system.physmem.perBankRdBursts::2 5051 # Per bank write bursts -system.physmem.perBankRdBursts::3 5281 # Per bank write bursts -system.physmem.perBankRdBursts::4 5400 # Per bank write bursts -system.physmem.perBankRdBursts::5 4765 # Per bank write bursts -system.physmem.perBankRdBursts::6 4961 # Per bank write bursts -system.physmem.perBankRdBursts::7 5223 # Per bank write bursts -system.physmem.perBankRdBursts::8 5069 # Per bank write bursts -system.physmem.perBankRdBursts::9 5177 # Per bank write bursts -system.physmem.perBankRdBursts::10 4953 # Per bank write bursts -system.physmem.perBankRdBursts::11 4660 # Per bank write bursts -system.physmem.perBankRdBursts::12 5195 # Per bank write bursts -system.physmem.perBankRdBursts::13 6216 # Per bank write bursts -system.physmem.perBankRdBursts::14 6082 # Per bank write bursts -system.physmem.perBankRdBursts::15 5780 # Per bank write bursts -system.physmem.perBankWrBursts::0 4915 # Per bank write bursts -system.physmem.perBankWrBursts::1 4846 # Per bank write bursts -system.physmem.perBankWrBursts::2 4413 # Per bank write bursts -system.physmem.perBankWrBursts::3 4685 # Per bank write bursts -system.physmem.perBankWrBursts::4 5227 # Per bank write bursts -system.physmem.perBankWrBursts::5 4409 # Per bank write bursts -system.physmem.perBankWrBursts::6 4642 # Per bank write bursts -system.physmem.perBankWrBursts::7 4533 # Per bank write bursts -system.physmem.perBankWrBursts::8 4328 # Per bank write bursts -system.physmem.perBankWrBursts::9 4737 # Per bank write bursts -system.physmem.perBankWrBursts::10 4592 # Per bank write bursts -system.physmem.perBankWrBursts::11 4470 # Per bank write bursts -system.physmem.perBankWrBursts::12 4760 # Per bank write bursts -system.physmem.perBankWrBursts::13 5234 # Per bank write bursts -system.physmem.perBankWrBursts::14 5550 # Per bank write bursts -system.physmem.perBankWrBursts::15 4796 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 868 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5096 # Per bank write bursts +system.physmem.perBankRdBursts::1 5035 # Per bank write bursts +system.physmem.perBankRdBursts::2 5503 # Per bank write bursts +system.physmem.perBankRdBursts::3 5713 # Per bank write bursts +system.physmem.perBankRdBursts::4 5011 # Per bank write bursts +system.physmem.perBankRdBursts::5 4756 # Per bank write bursts +system.physmem.perBankRdBursts::6 4921 # Per bank write bursts +system.physmem.perBankRdBursts::7 5413 # Per bank write bursts +system.physmem.perBankRdBursts::8 5128 # Per bank write bursts +system.physmem.perBankRdBursts::9 4999 # Per bank write bursts +system.physmem.perBankRdBursts::10 4701 # Per bank write bursts +system.physmem.perBankRdBursts::11 5348 # Per bank write bursts +system.physmem.perBankRdBursts::12 5396 # Per bank write bursts +system.physmem.perBankRdBursts::13 6167 # Per bank write bursts +system.physmem.perBankRdBursts::14 6376 # Per bank write bursts +system.physmem.perBankRdBursts::15 5703 # Per bank write bursts +system.physmem.perBankWrBursts::0 5743 # Per bank write bursts +system.physmem.perBankWrBursts::1 5870 # Per bank write bursts +system.physmem.perBankWrBursts::2 5006 # Per bank write bursts +system.physmem.perBankWrBursts::3 5323 # Per bank write bursts +system.physmem.perBankWrBursts::4 4689 # Per bank write bursts +system.physmem.perBankWrBursts::5 4481 # Per bank write bursts +system.physmem.perBankWrBursts::6 5327 # Per bank write bursts +system.physmem.perBankWrBursts::7 5300 # Per bank write bursts +system.physmem.perBankWrBursts::8 5281 # Per bank write bursts +system.physmem.perBankWrBursts::9 5131 # Per bank write bursts +system.physmem.perBankWrBursts::10 5421 # Per bank write bursts +system.physmem.perBankWrBursts::11 5658 # Per bank write bursts +system.physmem.perBankWrBursts::12 5171 # Per bank write bursts +system.physmem.perBankWrBursts::13 5597 # Per bank write bursts +system.physmem.perBankWrBursts::14 5966 # Per bank write bursts +system.physmem.perBankWrBursts::15 5038 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5136881165000 # Total gap between requests +system.physmem.totGap 5132871981000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 83494 # Read request sizes (log2) +system.physmem.readPktSize::6 85451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 76163 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 78715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3589 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 535 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 37 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34 # What read queue length does an incoming req see +system.physmem.writePktSize::6 85019 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 78990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 949 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see 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111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 34 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38507 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 264.993274 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 160.426697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 294.053955 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15907 41.31% 41.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9655 25.07% 66.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3981 10.34% 76.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2127 5.52% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1469 3.81% 86.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1046 2.72% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 664 1.72% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 555 1.44% 91.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3103 8.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38507 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3853 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.615365 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 121.265146 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-255 3842 99.71% 99.71% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-511 8 0.21% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-767 1 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2815 1 0.03% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6656-6911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3853 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3853 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.760446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.599143 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.462049 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 66 1.71% 1.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 8 0.21% 1.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 10 0.26% 2.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3269 84.84% 87.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 44 1.14% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 26 0.67% 88.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 135 3.50% 92.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 114 2.96% 95.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 3 0.08% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.36% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 8 0.21% 95.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.34% 96.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.05% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 2 0.05% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 96 2.49% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.03% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.13% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 13 0.34% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.10% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.05% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.03% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.13% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 4 0.10% 99.95% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 39962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 272.686252 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 163.690614 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.316153 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16345 40.90% 40.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9834 24.61% 65.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4112 10.29% 75.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2230 5.58% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1552 3.88% 85.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1069 2.68% 87.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 711 1.78% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 597 1.49% 91.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3512 8.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 39962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4105 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 20.770767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 117.592245 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-255 4095 99.76% 99.76% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-511 7 0.17% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-767 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2815 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6656-6911 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4105 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.706943 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.214534 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.616872 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 63 1.53% 1.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 7 0.17% 1.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 1 0.02% 1.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 4 0.10% 1.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3359 81.83% 83.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 49 1.19% 84.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.63% 85.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 173 4.21% 89.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 182 4.43% 94.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 7 0.17% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 12 0.29% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.19% 94.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 10 0.24% 95.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 2 0.05% 95.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.02% 95.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.02% 95.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 157 3.82% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 1 0.02% 98.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 3 0.07% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 10 0.24% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.05% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 2 0.05% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 5 0.12% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.05% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.19% 99.95% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::140-143 2 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3853 # Writes before turning the bus around for reads -system.physmem.totQLat 942120750 # Total ticks spent queuing -system.physmem.totMemAccLat 2504108250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 416530000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11309.16 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 4105 # Writes before turning the bus around for reads +system.physmem.totQLat 1041221500 # Total ticks spent queuing +system.physmem.totMemAccLat 2639959000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 426330000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12211.45 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30059.16 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.04 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.95 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.04 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.95 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30961.45 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.06 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing -system.physmem.avgWrQLen 7.45 # Average write queue length when enqueuing -system.physmem.readRowHits 65566 # Number of row buffer hits during reads -system.physmem.writeRowHits 55368 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.70 # Row buffer hit rate for writes -system.physmem.avgGap 32174481.33 # Average gap between requests -system.physmem.pageHitRate 75.84 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 4942580735250 # Time in different power states -system.physmem.memoryStateTime::REF 171564900000 # Time in different power states +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 6.94 # Average write queue length when enqueuing +system.physmem.readRowHits 67077 # Number of row buffer hits during reads +system.physmem.writeRowHits 63228 # Number of row buffer hits during writes +system.physmem.readRowHitRate 78.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.37 # Row buffer hit rate for writes +system.physmem.avgGap 30110118.97 # Average gap between requests +system.physmem.pageHitRate 76.52 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 4938526642750 # Time in different power states +system.physmem.memoryStateTime::REF 171431260000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 23734191750 # Time in different power states +system.physmem.memoryStateTime::ACT 23914099250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.membus.throughput 5877722 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 425622 # Transaction distribution -system.membus.trans_dist::ReadResp 425619 # Transaction distribution -system.membus.trans_dist::WriteReq 7303 # Transaction distribution -system.membus.trans_dist::WriteResp 7303 # Transaction distribution -system.membus.trans_dist::Writeback 54691 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 21472 # Transaction distribution -system.membus.trans_dist::UpgradeReq 873 # Transaction distribution -system.membus.trans_dist::UpgradeResp 873 # Transaction distribution -system.membus.trans_dist::ReadExReq 56661 # Transaction distribution -system.membus.trans_dist::ReadExResp 56661 # Transaction distribution -system.membus.trans_dist::MessageReq 1005 # Transaction distribution -system.membus.trans_dist::MessageResp 1005 # Transaction distribution -system.membus.trans_dist::BadAddressError 3 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 2010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 2010 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 313168 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 498446 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 222539 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 6 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1034159 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 44112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 44112 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1080281 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 4020 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.apicbridge.master::total 4020 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 160913 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 996889 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 8815488 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 9973290 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 1402560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 1402560 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 11379870 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 30180989 # Total data (bytes) -system.membus.snoop_data_through_bus 18048 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 165986000 # Layer occupancy (ticks) +system.membus.trans_dist::ReadReq 5056260 # Transaction distribution +system.membus.trans_dist::ReadResp 5056258 # Transaction distribution +system.membus.trans_dist::WriteReq 13754 # Transaction distribution +system.membus.trans_dist::WriteResp 13754 # Transaction distribution +system.membus.trans_dist::Writeback 96958 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1654 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1654 # Transaction distribution +system.membus.trans_dist::ReadExReq 129924 # Transaction distribution +system.membus.trans_dist::ReadExResp 129924 # Transaction distribution +system.membus.trans_dist::MessageReq 1664 # Transaction distribution +system.membus.trans_dist::MessageResp 1664 # Transaction distribution +system.membus.trans_dist::BadAddressError 2 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7028524 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3012958 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 456844 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 10498330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 94955 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10596613 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3520458 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6025913 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17615808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27162179 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3029056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 3029056 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30197891 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 297 # Total snoops (count) +system.membus.snoop_fanout::samples 324529 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 324529 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 324529 # Request fanout histogram +system.membus.reqLayer0.occupancy 165183000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 315728000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 315920500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2010000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1960000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 815495498 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 897247500 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3500 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1005000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 980000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1662343876 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1679098885 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 28017243 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 35042997 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 105452 # number of replacements -system.l2c.tags.tagsinuse 64826.295665 # Cycle average of tags in use -system.l2c.tags.total_refs 3690842 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169644 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.756396 # Average number of references to valid blocks. +system.l2c.tags.replacements 105529 # number of replacements +system.l2c.tags.tagsinuse 64826.632454 # Cycle average of tags in use +system.l2c.tags.total_refs 3692969 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169653 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.767779 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50973.887089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131156 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1039.864675 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3857.355286 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 297.125354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1525.078899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.736641 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.003210 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1792.530465 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5328.582890 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.777800 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50921.041202 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134275 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1022.158767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3887.538850 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 285.540185 # Average occupied blocks per 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-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60476.811663 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59840.380543 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59610.269001 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57550.329737 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77612.903226 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65275.616276 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60476.811663 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59840.380543 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10090.899015 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.992877 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56109.581907 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 59677.836285 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 58315.512045 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60432.285603 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57647.550784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60432.285603 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57647.550784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 67521.428571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65657.766238 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61919.579534 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 60870.660914 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -783,98 +758,98 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 47572 # number of replacements -system.iocache.tags.tagsinuse 0.093953 # Cycle average of tags in use +system.iocache.tags.replacements 47571 # number of replacements +system.iocache.tags.tagsinuse 0.081570 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47588 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47587 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000192642009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.093953 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005872 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.005872 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000192639009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081570 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005098 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005098 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428643 # Number of tag accesses -system.iocache.tags.data_accesses 428643 # Number of data accesses +system.iocache.tags.tag_accesses 428634 # Number of tag accesses +system.iocache.tags.data_accesses 428634 # Number of data accesses system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits -system.iocache.ReadReq_misses::pc.south_bridge.ide 907 # number of ReadReq misses -system.iocache.ReadReq_misses::total 907 # number of ReadReq misses -system.iocache.demand_misses::pc.south_bridge.ide 907 # number of demand (read+write) misses -system.iocache.demand_misses::total 907 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 907 # number of overall misses -system.iocache.overall_misses::total 907 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132008537 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132008537 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132008537 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132008537 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132008537 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132008537 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 907 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 907 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_misses::pc.south_bridge.ide 906 # number of ReadReq misses +system.iocache.ReadReq_misses::total 906 # number of ReadReq misses +system.iocache.demand_misses::pc.south_bridge.ide 906 # number of demand (read+write) misses +system.iocache.demand_misses::total 906 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 906 # number of overall misses +system.iocache.overall_misses::total 906 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132202779 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132202779 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132202779 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132202779 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132202779 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132202779 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 906 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 906 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 907 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 907 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 907 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 907 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 906 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 906 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 906 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 906 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 145544.142227 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 145544.142227 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145544.142227 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 145544.142227 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 145919.182119 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 145919.182119 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 145919.182119 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 471 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 39 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 12.076923 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 46720 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 725 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 725 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21472 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 21472 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 725 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 725 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 725 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94282037 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1310743323 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1310743323 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94282037 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94282037 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94282037 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.799338 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.459589 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.459589 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.799338 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.799338 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.799338 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 130044.188966 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 61044.305281 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 61044.305281 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 130044.188966 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 130044.188966 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 740 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 740 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 28368 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 28368 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 740 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 740 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 740 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 740 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 93698779 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 1718205368 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1718205368 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 93698779 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 93698779 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 93698779 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.816777 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.607192 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.607192 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.816777 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.816777 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.816777 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 126619.971622 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 60568.435138 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 60568.435138 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 126619.971622 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 126619.971622 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. @@ -884,109 +859,121 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.throughput 53202678 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1873297 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1872762 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 7303 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 7303 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 935388 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 21472 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 157258 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 157258 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 3 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1081926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3727147 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 42874 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 142768 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4994715 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 34620672 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 124341034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 151600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 524032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 159637338 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 270199237 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 3149808 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 5231949371 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::ReadReq 7367165 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7366643 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13756 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13756 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1548978 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 28368 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1663 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1663 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296632 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296632 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740682 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14873990 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 71302 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 198555 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 16884529 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55700736 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213654403 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 264160 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 728920 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270348219 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69633 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4254339 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011195 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105211 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4206713 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47626 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 4254339 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 5229007845 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 868500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 990000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2437443949 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2442789502 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4869271823 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4872933864 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 23963155 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 24776404 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 77561882 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 82986153 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 1275815 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 151004 # Transaction distribution -system.iobus.trans_dist::ReadResp 151004 # Transaction distribution -system.iobus.trans_dist::WriteReq 27777 # Transaction distribution -system.iobus.trans_dist::WriteResp 27777 # Transaction distribution -system.iobus.trans_dist::MessageReq 1005 # Transaction distribution -system.iobus.trans_dist::MessageResp 1005 # Transaction distribution +system.iobus.trans_dist::ReadReq 3504325 # Transaction distribution +system.iobus.trans_dist::ReadResp 3504325 # Transaction distribution +system.iobus.trans_dist::WriteReq 57563 # Transaction distribution +system.iobus.trans_dist::WriteResp 39211 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 18352 # Transaction distribution +system.iobus.trans_dist::MessageReq 1664 # Transaction distribution +system.iobus.trans_dist::MessageResp 1664 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 5602 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 2 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1160 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 50 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 287262 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 594 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 142 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 16180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 6984892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27280 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2048 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 313168 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 44394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 44394 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 2010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 2010 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 359572 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 2 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 3164 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 4 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 580 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 25 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 9 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 143631 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 1188 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 71 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 8090 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 160913 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 1410472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 1410472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 4020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 4020 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 1575405 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 6554984 # Total data (bytes) -system.iobus.reqLayer0.occupancy 2375600 # Layer occupancy (ticks) +system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7028524 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95252 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7127104 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3492446 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 3520458 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6656 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6554906 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2324808 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4638000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 4502000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer5.occupancy 758000 # Layer occupancy (ticks) system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 42000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) @@ -994,11 +981,11 @@ system.iobus.reqLayer8.occupancy 18000 # La system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 143632000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 469000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 361000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer11.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12075000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11636000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) @@ -1008,431 +995,431 @@ system.iobus.reqLayer16.occupancy 9000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 194319603 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 256433144 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 1024000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 306863000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 306163000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 26743757 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33668003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1005000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 980000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 1069887436 # number of cpu cycles simulated +system.cpu0.numCycles 1069607129 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 70857782 # Number of instructions committed -system.cpu0.committedOps 144307609 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 132405898 # Number of integer alu accesses +system.cpu0.committedInsts 70538619 # Number of instructions committed +system.cpu0.committedOps 143755687 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 131850662 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 941314 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14024705 # number of instructions that are conditional controls -system.cpu0.num_int_insts 132405898 # number of integer instructions +system.cpu0.num_func_calls 928819 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13976393 # number of instructions that are conditional controls +system.cpu0.num_int_insts 131850662 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 243097330 # number of times the integer registers were read -system.cpu0.num_int_register_writes 113712565 # number of times the integer registers were written +system.cpu0.num_int_register_reads 241989475 # number of times the integer registers were read +system.cpu0.num_int_register_writes 113259644 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 82467233 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55021807 # number of times the CC registers were written -system.cpu0.num_mem_refs 13631596 # number of memory refs -system.cpu0.num_load_insts 10001277 # Number of load instructions -system.cpu0.num_store_insts 3630319 # Number of store instructions -system.cpu0.num_idle_cycles 1016044794.752217 # Number of idle cycles -system.cpu0.num_busy_cycles 53842641.247783 # Number of busy cycles -system.cpu0.not_idle_fraction 0.050326 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.949674 # Percentage of idle cycles -system.cpu0.Branches 15304700 # Number of branches fetched -system.cpu0.op_class::No_OpClass 96295 0.07% 0.07% # Class of executed instruction -system.cpu0.op_class::IntAlu 130472194 90.41% 90.48% # Class of executed instruction -system.cpu0.op_class::IntMult 58212 0.04% 90.52% # Class of executed instruction -system.cpu0.op_class::IntDiv 49897 0.03% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.55% # Class of executed instruction -system.cpu0.op_class::MemRead 10001277 6.93% 97.48% # Class of executed instruction -system.cpu0.op_class::MemWrite 3630319 2.52% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82136389 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 54810829 # number of times the CC registers were written +system.cpu0.num_mem_refs 13501731 # number of memory refs +system.cpu0.num_load_insts 9912408 # Number of load instructions +system.cpu0.num_store_insts 3589323 # Number of store instructions +system.cpu0.num_idle_cycles 1016224343.330366 # Number of idle cycles +system.cpu0.num_busy_cycles 53382785.669634 # Number of busy cycles +system.cpu0.not_idle_fraction 0.049909 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.950091 # Percentage of idle cycles +system.cpu0.Branches 15238819 # Number of branches fetched +system.cpu0.op_class::No_OpClass 94852 0.07% 0.07% # Class of executed instruction +system.cpu0.op_class::IntAlu 130054750 90.47% 90.53% # Class of executed instruction +system.cpu0.op_class::IntMult 56051 0.04% 90.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 48845 0.03% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.61% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.61% # Class of executed instruction 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number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 147420132000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.471919 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.049993 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.702632 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.245062 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.267676 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.483794 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.996532 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 869835 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.810026 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128546541 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 870347 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 147.695736 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 147420125000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 125.953257 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 137.567270 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 247.289498 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.246002 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.268686 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.482987 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997676 # Average percentage of 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86126688 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 39841426 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3472426 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 129440540 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 86126688 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 39841426 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3472426 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 129440540 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 86126688 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 39841426 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3472426 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 129440540 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003811 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004064 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117261 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006886 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004151 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.115315 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006907 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003811 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004064 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117261 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006886 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004151 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.115315 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006907 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003811 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004064 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117261 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006886 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13953.064780 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14253.712685 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8943.153684 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13953.064780 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14253.712685 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8943.153684 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13953.064780 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14253.712685 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8943.153684 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5197 # number of cycles access was blocked +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004151 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.115315 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006907 # miss rate for overall accesses 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number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1989596000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4688278233 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 6677874233 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004151 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.108507 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004188 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004151 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.108507 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004188 # mshr miss rate for demand accesses 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254.719707 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 235.128668 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 22.151075 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.497499 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.459236 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.043264 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id 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11961749403 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14330296153 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2359034692 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3857271379 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6216306071 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 4727581442 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 15819020782 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 20546602224 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 4727581442 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 15819020782 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 20546602224 # number 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accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 211967 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466050 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8856784 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4626166 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7731133 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21214083 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9023127 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4713906 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7943100 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21680133 # number of overall (read+write) accesses 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ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11160.492946 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36804.709998 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31623.977265 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19019.649216 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20044.440194 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 18120.028891 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12755.083151 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 15171.663710 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15005.967453 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10190.993553 # average overall miss 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# miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.039522 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.034500 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.040642 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038872 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.893230 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.862572 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.853851 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.869513 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.057565 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050880 # miss rate for demand accesses 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32561.311943 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18841.990618 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19327.209704 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 19249.105917 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13313.284047 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 14602.266020 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 15987.586490 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10656.437768 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 138914 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 26365 # number of cycles access was blocked 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33314384500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63971861500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 501111500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 893222000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394333500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31158588500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34207606500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65366195000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060792 # mshr miss rate for ReadReq accesses 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-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16741.448211 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1548978 # number of writebacks +system.cpu0.dcache.writebacks::total 1548978 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 70 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 359132 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 359202 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1638 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 26497 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 28135 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1708 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 385629 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 387337 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1708 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 385629 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 387337 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 171029 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 408794 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 579823 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 59295 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 97205 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 156500 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 75065 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 179480 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 254545 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 230324 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 505999 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 736323 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 305389 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 685479 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 990868 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2019901500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5830950588 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7850852088 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1912820354 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3255992760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5168813114 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 995266500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2770573261 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3765839761 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3932721854 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9086943348 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13019665202 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 4927988354 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11857516609 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 16785504963 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30674705000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33246369000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63921074000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 534053500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 811227000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1345280500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 31208758500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 34057596000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 65266354500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.061209 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.084010 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045295 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033572 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031937 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018640 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.862400 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.842514 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.545962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050505 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.063972 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034738 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.065711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.084391 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.045740 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11810.286560 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14263.787110 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13540.083936 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32259.387031 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33496.144849 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33027.559834 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13258.729101 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 15436.668492 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.396908 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17074.737561 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17958.421554 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17682.002602 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16136.757886 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17298.147148 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16940.202896 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1443,376 +1430,376 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2606024060 # number of cpu cycles simulated +system.cpu1.numCycles 2604021576 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35944624 # Number of instructions committed -system.cpu1.committedOps 69816061 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64937038 # Number of integer alu accesses +system.cpu1.committedInsts 35901808 # Number of instructions committed +system.cpu1.committedOps 69778761 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 64893692 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 484528 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6597164 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64937038 # number of integer instructions +system.cpu1.num_func_calls 487874 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6598396 # number of instructions that are conditional controls +system.cpu1.num_int_insts 64893692 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120144832 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55989327 # number of times the integer registers were written +system.cpu1.num_int_register_reads 119938204 # number of times the integer registers were read +system.cpu1.num_int_register_writes 55974127 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36928761 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27400948 # number of times the CC registers were written -system.cpu1.num_mem_refs 4904439 # number of memory refs -system.cpu1.num_load_insts 3100845 # Number of load instructions -system.cpu1.num_store_insts 1803594 # Number of store instructions -system.cpu1.num_idle_cycles 2475176569.081452 # Number of idle cycles -system.cpu1.num_busy_cycles 130847490.918548 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050210 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949790 # Percentage of idle cycles -system.cpu1.Branches 7263647 # Number of branches fetched -system.cpu1.op_class::No_OpClass 35052 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64819822 92.84% 92.89% # Class of executed instruction -system.cpu1.op_class::IntMult 29822 0.04% 92.94% # Class of executed instruction -system.cpu1.op_class::IntDiv 27277 0.04% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.98% # Class of executed instruction -system.cpu1.op_class::MemRead 3100845 4.44% 97.42% # Class of executed instruction -system.cpu1.op_class::MemWrite 1803594 2.58% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36929560 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 27415142 # number of times the CC registers were written +system.cpu1.num_mem_refs 4838216 # number of memory refs +system.cpu1.num_load_insts 3070311 # Number of load instructions +system.cpu1.num_store_insts 1767905 # Number of store instructions +system.cpu1.num_idle_cycles 2474835372.874957 # Number of idle cycles +system.cpu1.num_busy_cycles 129186203.125043 # Number of busy cycles +system.cpu1.not_idle_fraction 0.049610 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.950390 # Percentage of idle cycles +system.cpu1.Branches 7267731 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34873 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 64849393 92.94% 92.99% # Class of executed instruction +system.cpu1.op_class::IntMult 30804 0.04% 93.03% # Class of executed instruction +system.cpu1.op_class::IntDiv 25762 0.04% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.07% # Class of executed instruction +system.cpu1.op_class::MemRead 3070311 4.40% 97.47% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767905 2.53% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69816412 # Class of executed instruction +system.cpu1.op_class::total 69779048 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29512659 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29512659 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 322904 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26886254 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 26249300 # Number of BTB hits +system.cpu2.branchPred.lookups 29537500 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29537500 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 323734 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26929505 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 26224950 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.630931 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 591365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 64668 # Number of incorrect RAS predictions. -system.cpu2.numCycles 155365551 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.383706 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 595117 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 63666 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155672620 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10587640 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 145508462 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29512659 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26840665 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 143230873 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 673912 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 95091 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 7931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 8903 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 52631 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 2801 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 311 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3432374 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167414 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3341 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 154322486 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.857387 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.033367 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 10607285 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145694636 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29537500 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26820067 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 143529975 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 676631 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 97153 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 5039 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8049 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 56841 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 4424 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 421 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3472431 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 167012 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3661 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154646852 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.855079 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.032629 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 98410042 63.77% 63.77% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 833989 0.54% 64.31% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 24035117 15.57% 79.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 597750 0.39% 80.27% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 798628 0.52% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 859445 0.56% 81.35% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 568143 0.37% 81.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 716402 0.46% 82.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27502970 17.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98720699 63.84% 63.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 840447 0.54% 64.38% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23990695 15.51% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 599923 0.39% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 812589 0.53% 80.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 861055 0.56% 81.36% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 574182 0.37% 81.73% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 718315 0.46% 82.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27528947 17.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 154322486 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189956 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.936556 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10280285 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 95091051 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 22517334 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5911995 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 337607 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 283677190 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 337607 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 12887048 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 76613528 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4915145 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 25582017 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 13802994 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 282449598 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 208301 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 6363616 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 49211 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4861555 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 337331977 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 615247721 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 378014471 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 38 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 325050122 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12281853 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 158846 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160455 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 28628976 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6469632 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3638513 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 420201 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 343826 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 280493266 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 428842 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 278404006 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 102314 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8748691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13528194 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 64074 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 154322486 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.804040 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.401684 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154646852 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189741 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.935904 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10277789 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 95381782 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 22559618 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 5904125 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 338966 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283871353 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 338966 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12885148 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 76664692 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4829048 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 25619792 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14124701 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 282624473 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 211024 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 6375709 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 73879 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 5159969 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 337473501 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 616062521 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 378507156 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 50 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 325128635 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12344864 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 162095 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 163797 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 28599466 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6606628 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3716011 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 425441 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 346966 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 280674873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 430305 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 278581977 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 102725 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 8814114 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 13599788 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 65362 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154646852 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.801407 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.400759 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 91177599 59.08% 59.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5361636 3.47% 62.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3887403 2.52% 65.08% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4108764 2.66% 67.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 21799190 14.13% 81.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 3056480 1.98% 83.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 24267786 15.73% 99.57% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 453628 0.29% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 210000 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91425932 59.12% 59.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5392264 3.49% 62.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3912324 2.53% 65.14% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4126244 2.67% 67.80% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 21795400 14.09% 81.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 3071037 1.99% 83.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 24235245 15.67% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 469170 0.30% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 219236 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 154322486 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154646852 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2321368 89.34% 89.34% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 246 0.01% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.35% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 217075 8.35% 97.70% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 59662 2.30% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2310389 89.01% 89.01% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 246 0.01% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 89.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 223101 8.59% 97.61% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 62004 2.39% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 72561 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 268083598 96.29% 96.32% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 57882 0.02% 96.34% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 47134 0.02% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.36% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6794594 2.44% 98.80% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3348237 1.20% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 76436 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 268041478 96.22% 96.24% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 58746 0.02% 96.26% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 49744 0.02% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.28% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 6933130 2.49% 98.77% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3422443 1.23% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 278404006 # Type of FU issued -system.cpu2.iq.rate 1.791929 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 2598351 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.009333 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 713831099 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 289675272 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 276815941 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 63 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 70 # Number of floating instruction queue writes +system.cpu2.iq.FU_type_0::total 278581977 # Type of FU issued +system.cpu2.iq.rate 1.789537 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 2595740 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.009318 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 714509188 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289923619 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 276984093 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 82 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 98 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 18 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 280929766 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 30 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 708692 # Number of loads that had data forwarded from stores +system.cpu2.iq.int_alu_accesses 281101244 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 37 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 733638 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1202973 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6613 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 5162 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 660777 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1227908 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 6601 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5025 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 667461 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 754641 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21520 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 754863 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 24022 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 337607 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 71713264 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1590839 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 280922108 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 41019 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6469632 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3638513 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 247100 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 199459 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1088059 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 5162 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 186556 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 187873 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374429 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 277824668 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6659327 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 530499 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 338966 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71689555 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 1628683 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 281105178 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 39439 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6606628 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3716011 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 250069 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 194031 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 1131651 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5025 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 186633 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 188127 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 374760 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 278001109 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 6795315 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 530943 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9922055 # number of memory reference insts executed -system.cpu2.iew.exec_branches 28210243 # Number of branches executed -system.cpu2.iew.exec_stores 3262728 # Number of stores executed -system.cpu2.iew.exec_rate 1.788200 # Inst execution rate -system.cpu2.iew.wb_sent 277637651 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 276815959 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 215923076 # num instructions producing a value -system.cpu2.iew.wb_consumers 354065892 # num instructions consuming a value +system.cpu2.iew.exec_refs 10133053 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28226522 # Number of branches executed +system.cpu2.iew.exec_stores 3337738 # Number of stores executed +system.cpu2.iew.exec_rate 1.785806 # Inst execution rate +system.cpu2.iew.wb_sent 277806882 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 276984111 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215977189 # num instructions producing a value +system.cpu2.iew.wb_consumers 354208085 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.781707 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609839 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.779273 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609747 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9085200 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 364768 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325355 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152966387 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.777091 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.654040 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9156375 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 364943 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 326343 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153280377 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.774187 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.653000 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 95002675 62.11% 62.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4175839 2.73% 64.84% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1266091 0.83% 65.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24954040 16.31% 81.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 981729 0.64% 82.62% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 650164 0.43% 83.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 435006 0.28% 83.33% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23529501 15.38% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1971342 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95267512 62.15% 62.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4211429 2.75% 64.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1288351 0.84% 65.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24928908 16.26% 82.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 992667 0.65% 82.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 656859 0.43% 83.08% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 436979 0.29% 83.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23484943 15.32% 98.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2012729 1.31% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152966387 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 137677652 # Number of instructions committed -system.cpu2.commit.committedOps 271835156 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153280377 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137795324 # Number of instructions committed +system.cpu2.commit.committedOps 271948125 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8244394 # Number of memory references committed -system.cpu2.commit.loads 5266658 # Number of loads committed -system.cpu2.commit.membars 166791 # Number of memory barriers committed -system.cpu2.commit.branches 27802655 # Number of branches committed +system.cpu2.commit.refs 8427269 # Number of memory references committed +system.cpu2.commit.loads 5378719 # Number of loads committed +system.cpu2.commit.membars 165391 # Number of memory barriers committed +system.cpu2.commit.branches 27813078 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 248203210 # Number of committed integer instructions. -system.cpu2.commit.function_calls 440588 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 43200 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 263446464 96.91% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 55564 0.02% 96.95% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 45534 0.02% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.97% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5266658 1.94% 98.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2977736 1.10% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 248363308 # Number of committed integer instructions. +system.cpu2.commit.function_calls 444774 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 44974 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 263371453 96.85% 96.86% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56553 0.02% 96.88% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 47876 0.02% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5378719 1.98% 98.88% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3048550 1.12% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 271835156 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1971342 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 271948125 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2012729 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 431889681 # The number of ROB reads -system.cpu2.rob.rob_writes 563202973 # The number of ROB writes -system.cpu2.timesIdled 114782 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1043065 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4908353341 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 137677652 # Number of Instructions Simulated -system.cpu2.committedOps 271835156 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.128473 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.128473 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.886153 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.886153 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 369541594 # number of integer regfile reads -system.cpu2.int_regfile_writes 221773447 # number of integer regfile writes -system.cpu2.fp_regfile_reads 72930 # number of floating regfile reads -system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes -system.cpu2.cc_regfile_reads 140769340 # number of cc regfile reads -system.cpu2.cc_regfile_writes 108468562 # number of cc regfile writes -system.cpu2.misc_regfile_reads 90221682 # number of misc regfile reads -system.cpu2.misc_regfile_writes 135530 # number of misc regfile writes +system.cpu2.rob.rob_reads 432344700 # The number of ROB reads +system.cpu2.rob.rob_writes 563581737 # The number of ROB writes +system.cpu2.timesIdled 114304 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1025768 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4904031691 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137795324 # Number of Instructions Simulated +system.cpu2.committedOps 271948125 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.129738 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.129738 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.885161 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.885161 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370036745 # number of integer regfile reads +system.cpu2.int_regfile_writes 221903617 # number of integer regfile writes +system.cpu2.fp_regfile_reads 72874 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72912 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140867740 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108480868 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90412070 # number of misc regfile reads +system.cpu2.misc_regfile_writes 138782 # number of misc regfile writes system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed |